JP2888181B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash memory type nonvolatile semiconductor memory device having a floating gate and arrayed electrically rewritable and erasable memory cell transistors.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device of a flash memory type having a floating gate and a plurality of memory cell transistors capable of electrically writing and erasing data and arranged in a row direction and a column direction stores a predetermined amount of stored data. , And can be collectively erased electrically in units of.

FIGS. 2A and 2B show a typical example of such a nonvolatile semiconductor memory device.

This nonvolatile semiconductor memory device includes a memory cell array 1 having a floating gate and a plurality of memory cell transistors MC11 to MCmn which can be electrically written and erased in a row direction and a column direction, and a plurality of memory cells. A plurality of word lines WL1 to WLm provided corresponding to each row of cell transistors MC11 to MCmn and connected to the control gates of the memory cell transistors in the corresponding row
And a plurality of memory cell transistors MC11 to MCmn
And a plurality of bit lines BL1 to BLn connected to the drains of the memory cell transistors in the corresponding column provided in correspondence with the respective columns, and a row address signal ADx in a write operation and a read operation (including a test mode after erasure). And an X decoder 2a for supplying a voltage during the operation and setting all word lines WL1 to WLm to the ground potential level during an erase operation, and a predetermined word line according to a column address signal ADy during a write operation and a read operation. When a bit line is selected and erase operation is performed, bit lines BL1 to BLn
Y decoder 3 in which all are in a floating state and not selected
a and Y switch circuit 4, a write circuit 5 for supplying a write voltage to a selected bit line according to write data DI during a write operation, and a signal (data) of a selected bit line during a read operation And a sense amplifier 6 for comparing and amplifying the output with a reference signal REF and outputting (DO). Note that, as shown in FIG. 2B, the Y decoder 3a includes NAND gates and inverters corresponding to the bit lines BL1 to BLn, respectively (however, all the bit lines BL1 to BLn are not selected). The circuit is omitted).

Next, with respect to the operation of the nonvolatile semiconductor memory device, a write operation will be described first.

In order to set the selected word line (the control gate of the memory cell transistor) to about 12 V,
The selected bit line (drain) is set to about 6V and the source line WS
L is set to 0 V, and hot electrons generated near the drain are injected into the floating gate. As a result, the threshold voltage of the memory cell transistor increases.

Next, the erasing operation will be described. To set the erase state, all the word lines WL1 to WLm are set to 0V, the source line SL is set to about 12V, and the bit lines BL1 to
With all BLn in a floating state, electrons are extracted from the floating gate to the source by the FN tunneling effect, and the operation is performed for all memory cell transistors at once. As a result, the memory cell transistors MC11-MC
mn becomes lower.

At the time of this erasing operation, the erasing speed characteristics of the individual memory cell transistors are different due to variations in the manufacturing process and the like. Therefore, there are memory cell transistors having a high erasing speed and memory cell transistors having a low erasing speed. In addition, since the erase operation time is set to the memory cell transistor having a slow erase speed, the memory cell transistor having a fast erase speed is over-erased with respect to the memory cell transistor having a slow erase speed, and its threshold voltage becomes negative. There is a risk of becoming. If the threshold voltage becomes negative, a current always flows through the memory cell transistor, so that accurate data cannot be read.
Therefore, it is necessary to check the threshold voltages of all memory cell transistors after erasing. The operation is as follows. After erasing, a voltage of, for example, about 0.5 V is applied to the control gate of the memory cell transistor, that is, a word line, and bit lines connected to the drain are sequentially selected and connected to the sense amplifier 6. Is determined by the sense amplifier 6 whether or not the memory cell transistor connected to the memory cell transistor is in an off state (hereinafter, this is referred to as a depletion check). .

Next, the depletion check operation will be described.

After erasing, by setting the test mode, a voltage of about 0.5 V is applied to the selected word line by the X decoder 2a. The number of selected word lines was initially one, but recently all word lines have been used, and the test time has been shortened accordingly.

Next, bit lines BL1 to BLn are sequentially selected by an external column address signal ADy, connected to sense amplifier 6, and all bit lines connected to one bit line connected to sense amplifier 6 are connected. The current flowing through the memory cell transistor is compared with a reference signal REF. If the threshold voltages of these memory cell transistors are all equal to or higher than the word line voltage (0.5 V), all of these memory cell transistors are off and no current flows through the selected bit line. If there is a depletion state, a current flows to the selected bit line, so that it is possible to determine whether or not there is a memory cell transistor that is overerased (depletion state).
This determination operation is sequentially performed for all bit lines.

Since the read operation is the same as that of a normal semiconductor memory device, the description is omitted.

[0013]

In the conventional nonvolatile semiconductor memory device, when performing a depletion check (check for excessive erasure) after erasing, a bit line is selected one by one and sent to the sense amplifier 6. The current flowing through the selected bit line is compared with a reference signal REF to determine whether or not there is a memory cell transistor in a depletion state (excessively erased state).
There is a problem that the time required for the depression check becomes long.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening the time required for a depression check.

[0015]

Further, the pre-Symbol column decoder provided corresponding to the bit line selection signals, respectively, the plurality of P-channel type which the predetermined bit of the column address signal to the gate is received corresponding parallel connection A plurality of N-channel type transistors connected in series between the drains of the plurality of P-channel type first transistors and a ground potential point, receiving a predetermined bit of the column address signal corresponding to one transistor and the gate; A NAND gate comprising a first transistor; an inverter for inverting the level of an output signal of the NAND gate;
P-channel second transistor connected between the source of the channel-type first transistor and the power supply potential point
As a circuit including a second transistor connected N-channel type between the the Gate and drain of the first transistor of the total column selection control signal receiving the plurality of P-channel type and a ground potential point Be composed.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A and 1B are a circuit diagram showing an embodiment of the present invention and a circuit diagram showing a specific example of a Y decoder portion thereof.

In this embodiment, a memory cell array 1 having a floating gate, in which a plurality of memory cell transistors MC11 to MCmn capable of electrically writing and erasing data are arranged in a row direction and a column direction, and a plurality of memory cell transistors A plurality of word lines WL1 to WLm provided corresponding to each row of MC11 to MCmn and connected to the control gates of the memory cell transistors in the corresponding row, and provided corresponding to each column of the plurality of memory cell transistors. A plurality of bit lines BL1 to BLn connected to the drains of the memory cell transistors in the column to be connected, and a predetermined word line among the plurality of word lines WL1 to WLm are selected in accordance with a row address signal ADx during a write operation and a read operation. Select the level during the operation, during the erase operation and during the test operation after the erase Selects an X decoder 2 that sets all word lines WL1 to WLm to a predetermined potential during the operation, and selects a predetermined bit line among a plurality of bit lines BL1 to BLn according to a column address signal ADy during a write operation and a read operation. During the erase operation, a plurality of bit lines BL1 to BLn
In a test operation after erasing all the cells in a non-selected state, Y of a column selection circuit for selecting all of the plurality of bit lines BL1 to BLn is selected.
A decoder 3 and a Y switch circuit 4; a write circuit 5 for supplying a write voltage to a selected bit line according to write data DI during a write operation; and a signal level of the selected bit line during a read operation A sense amplifier 6 which detects and determines by comparing with a reference signal REF, and at the time of a test operation after erasing, detects and determines the level of all signals of a plurality of bit lines BL1 to BLn selected at the same time by comparing with a reference signal REF. And a configuration having:

The Y decoder 3 has a plurality of bit lines B
L1 to BLn are provided corresponding to the respective bits, and a predetermined bit (AY1 to AYN) of the column address signal ADy is provided at the gate.
), A plurality of P-channel transistors Qp1 connected in parallel and a column address signal A
A NAND gate including a plurality of N-channel transistors Qn1 connected in series between the drains of a plurality of P-channel transistors Qp1 and a ground potential point in response to receiving predetermined bits (AY1 to AYN, etc.) of Dy Department and
Inverter IV for inverting the level of the output signal of the NAND gate and outputting a corresponding column selection signal (Y1 or the like)
A P-channel transistor Qp2 connected between the source of a plurality of P-channel transistors Qp1 and a power supply potential point (potential Vcc) at the gate to receive the all-column selection control signal YA; N-channel transistor Qn connected between the drains of a plurality of P-channel transistors and ground potential point upon receiving control signal YA
2 is included. Note that a circuit for setting all the bit lines BL1 to BLn to a non-selected state is omitted in FIG.

Next, the operation of this embodiment will be described. Since the write operation, erase operation and read operation in this embodiment are performed in the same manner as in the conventional example shown in FIGS. 2A and 2B, further description will be omitted.

The test operation after erase (test mode) is as follows.
In the test mode, the X decoder 2 selects all the word lines WL1 to WLm by the all row selection control signal XA and the all column selection control signal YA which are at the active level to about 0.5 V
And the Y decoder 3 and the Y switch circuit 4 set all the column selection signals Y1 to Yn to the active level to select all the bit lines BL1 to BLn, and
Connect to

As a result, all the memory cell transistors MC11 to MCmn of the memory cell array 1 are selected, and their drains are connected to the sense amplifier 6 through the bit lines BL1 to BLn. And this sense amplifier 6
Accordingly, the total current flowing through the bit lines BL1 to BLn is compared with the reference signal REF, and is detected and determined.

Memory cell transistors MC11 to MCm
If all of the memory cell transistors MC11 to MCmn are in the off state and no current flows, all of the memory cell transistors MC11 to MCmn are in the normal erase state and there is no overvoltage state or depletion state. The sense amplifier 6 determines this state and outputs a signal of a level corresponding to this state.
On the other hand, the memory cell transistors MC11 to MCm
If at least one of n has an overerased state or a depleted state, the memory transistor is turned on and a current flows, and the sense amplifier 6 detects this current and outputs a signal of a corresponding level. I do.

Thus, the memory cell transistor M
It is possible to test by one operation whether or not there is an overerased state or a depleted state among C11 to MCmn, and a test (depression check)
Can be shortened.

In the Y decoder 3, a circuit for selecting all bit lines by the all column selection control signal YA is connected to a generally used NAND gate for decoding shown in FIG. NAND gate of two inputs (one inputs the output of the NAND gate and the other inputs the all-column select control signal YA) or N
In the configuration provided with the OR gate, four transistors are required for a two-input NAND gate (NOR gate). However, the configuration shown in FIG.
The number of transistors can be reduced.

[0027]

As described above, according to the present invention, the depletion check after erasing is performed by selecting all the word lines and simultaneously selecting a plurality of bit lines and connecting them to the sense amplifier. Since the signal level is detected and determined, the depletion check of all memory cell transistors connected to a plurality of bit lines can be performed at once, and the time required for the depletion check can be reduced. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention and its Y
FIG. 3 is a circuit diagram illustrating a specific example of a decoder section.

FIG. 2 is a circuit diagram showing an example of a conventional nonvolatile semiconductor memory device and a circuit diagram showing a specific example of a Y decoder portion thereof.

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2, 2a X decoder 3, 3a Y decoder 4 Y switch circuit 5 write circuit 6 sense amplifier BL1 to BLn bit line MC11 to MCmn memory cell transistor Qn1, Qn2, Qp1, Qp2 transistor WL1 to WLm word line

Claims (1)

(57) [Claims] 1. A column decoder having column activating means for controlling activation and deactivation of a column selection signal by an all column selection control signal for selecting all bit lines, and all word lines during a test operation after erasure. A row decoder that outputs a row selection signal activated by an all row selection control signal for selecting all the word lines at a predetermined positive potential during the operation, and in a test mode after erasing data, By simultaneously selecting all of the word lines and all of the bit lines with the column selection signal and the row selection signal activated by the column selection control signal and the all row selection control signal, respectively, in a single test operation, One of the memory transistors
An electrically writable non-volatile semiconductor memory device which detects a conduction current of any transistor in an over-erased state or a depletion state by a sense amplifier and outputs a signal of a corresponding level. In which the column decoder is paired with each of the bit line selection signals.
A corresponding gate is provided with a predetermined address of a column address signal.
P-channel type connected in parallel to receive the data
The first transistor and the gate of the column address signal
Of the plurality of P-channel types
Between the drain of the first transistor and the ground potential point
A plurality of N-channel first transistors connected in series
Gate unit comprising the same, and the NAND gate unit
An inverter that inverts the level of the output signal of
Receiving a column selection control signal;
Connected between the source of the transistor and the power supply potential point
The P-channel type second transistor and the gate are connected to the entire column.
Receiving the selection control signal, the plurality of P-channel type first tones;
Connected between the drain of the transistor and the ground potential point
A nonvolatile semiconductor memory device , comprising a circuit including an N-channel second transistor .