JP3588553B2 - Non-volatile semiconductor memory - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory, and in particular, performs a read operation by driving a word line with a boosted power supply supplied from a booster circuit and detecting a voltage change in discharging a precharged bit line voltage. It is used for low voltage, low power consumption non-volatile semiconductor memories.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a nonvolatile semiconductor memory (hereinafter, referred to as an EPROM; Electrically Programmable Read Only Memory) that includes a flip-flop type sense amplifier and performs a read operation by a precharge / discharge method. Here, the precharge / discharge method refers to an EPROM reading method for detecting a voltage change in discharging a precharged bit line voltage.
[0003]
The operation principle of the EPROM will be described based on the circuit configuration shown in FIG. In the present specification, the read operation of the EPROM is the subject of the present invention, and therefore, a storage area usually called a memory cell array is used as a comparison between a read cell array in which storage data is written and a read state of a read cell. The description will be made separately for a plurality of reference cells to be used.
[0004]
FIG. 5 shows a part of a circuit configuration of a nonvolatile semiconductor memory including a read cell array, a plurality of reference cells, and a sense amplifier. A sense amplifier 10 is provided at the center, and an I-type (intrinsic type) transistor 1, a column select transistor 2, and floating gate transistors of m rows and n columns (m and n are integers of 1 or more) are provided above and below the sense amplifier 10. , A NOR-type read cell array 3, a NOR-type reference cell 4 of one row similarly composed of n floating gate transistors, a discharge transistor 5, a word line 6, a reference word line 6 a, and a source line 7. , And bit lines 8, and memory planes B and 12 are arranged so as to have a mirror image with respect to sense amplifier 10 including precharge transistor 9.
[0005]
Here, the word lines are m word lines 6 commonly connected to the control gates of read cells in the same row, and one reference word line commonly connected to the control gates of the one row of reference cells. 6a. The bit line is composed of n bit lines 8 via a column select transistor for selecting a column of the read cell.
[0006]
The I-type transistor 1 has a fixed bias V of about 1 V _BIAS When a precharge voltage is applied to the bit line 8 via the precharge transistor 9, the power supply voltage (V _CC ) Serves as a buffer so as not to be directly added to the bit line. The bit line 8 is selected by inputting the output of the column address decoder to the gate of the column select transistor 2.
[0007]
Further, the output of the row (row) address decoder is input to a word line, and a read target read cell (hereinafter, referred to as a selected read cell) 3 connected to the selected word line 6 and the selected bit line 8 is shown in FIG. Are shown in a circle on the memory surface A.
[0008]
Reading of the selected read cell 3 is performed as follows. Before the read operation, for example, “0” or “1” data is written in the selected read cell 3 in advance.
[0009]
In a NOR type EPROM, the read cell 3 and the reference 4 are designed such that the neutral threshold values are all constant positive values. Here, the neutral threshold refers to the threshold of a cell in a state where electrons are not injected into the floating gate (erased state).
[0010]
In the “0” write state, electrons are injected into the floating gate of the transistor constituting the cell, and the threshold value of the select gate cell 3 further shifts from the neutral threshold value in the positive direction. In the “1” write state, electrons are not injected into the floating gate, and the positive neutral threshold in the erased state is maintained.
[0011]
In the circuit shown in FIG. 5, for example, when a selected read cell 3 on the memory surface A is read, a reference cell (hereinafter referred to as a selected reference cell) 4 corresponding to the selected read cell 3 indicated by a circle on the memory surface B is selected. Is done.
[0012]
Prior to reading, the discharge transistors 5 on the memory surfaces A and B are turned off, and the precharge signal PR (bar) transferred from the precharge signal generation circuit to the gate of the precharge transistor 9 connected to the input of the sense amplifier 10 in advance. ), The precharge voltage is supplied to the selected bit lines on the memory surfaces A and B via the I-type transistor 1 and the column select transistor 2.
[0013]
Next, a read voltage is applied to the selected word line 6 on the memory surface A and the reference word line 6a on the memory surface B, and the discharge transistor 5 is turned on by the discharge signal DIS. The selected bit line 8 is discharged via the selected read cell and the selected reference cell, respectively.
[0014]
The precharged voltage of the selected bit line 8 on the memory surfaces A and B is connected to the input of a sense amplifier 10 composed of two NOR gates connected to a flip-flop (hereinafter abbreviated as F / F), respectively. Its binary output F / F-OUT ₁ And F / F-OUT ₂ As a result, the state of writing to the selected read cell 3 is read out in comparison with the reference cell 4.
[0015]
Here, the read operation of the sense amplifier 10 including the flip-flop circuit will be described in more detail. The difference between the read cell 3 and the reference cell 4 is that the transconductance g of the floating gate transistor forming the read cell 3 is different. _m Is designed to be larger than that of the reference cell 4.
[0016]
When the selected read cell 3 is in the “1” write state, no electrons are injected into the floating gate, and its neutral threshold value is a positive value equal to that of the selected reference cell 4. Reading is performed by applying a positive reading voltage to the selected word line 6 and the reference word line 6a to turn them on, and comparing the discharge current of the precharged bit line 8.
[0017]
However, the selected read cell 3 has g _m Is designed to be large, if the precharge state of the bit line 8 is the same, the charge of the bit line 8 on the selected read cell side is discharged earlier, and the input voltage on the selected read cell side of the sense amplifier 10 is selected by the reference voltage. After the discharge starts, the bit line potential on the selected read cell side exceeds the threshold value of the F / F circuit and the output F / F-OUT of the sense amplifier 10 after the discharge starts. ₁ Is inverted from “0” to “1”.
[0018]
On the other hand, when the selected read cell 3 is in the “0” write state, electrons are injected into the floating gate, so that the threshold value further shifts from the neutral threshold value to the positive side, and the read voltage is applied to the selected word line 6. Is applied, the selected read cell 6 is turned off. Therefore, the bit line potential on the reference side, which is always on, first exceeds the circuit threshold value of the F / F, and the F / F-OUT ₂ Is inverted from "0" to "1", and even if the bit line potential on the selected read cell side exceeds the threshold value of the F / F circuit due to off-leakage or the like, F / F-OUT ₁ "0" state is maintained.
[0019]
Thus, the output F / F-OUT of the F / F circuit constituting the sense amplifier ₁ “1” or “0” state (F / F-OUT ₂ ("0" or "1" state), the "1" write state or "0" write state to the selected read cell 3 is read out to the F / F circuit.
[0020]
A differential amplification type sense amplifier using a generally used current mirror circuit has a complicated circuit configuration, so that the characteristic deteriorates significantly outside an optimized operating voltage range, whereas an F / F circuit is used. The sense amplifier 10 can operate in a wide voltage range because the output of the cell is received by a simple NOR gate.
[0021]
Further, by boosting the word line, the power supply voltage V _CC By applying the boosted potential to the word line and the reference word line of the cell, a read operation at a low power supply voltage has been enabled.
[0022]
However, in such a conventional reading method, since the word line is boosted in order to secure a reading margin at a low power supply voltage, for example, after the ultraviolet erasing of a nonvolatile semiconductor memory (hereinafter referred to as UV erasing), Threshold V _th For the read cell 3 with a low readout, the readout is performed under a loose condition, and as the verify after erasure (check by reading whether or not the data has been erased), the readout is performed under a severe condition in the sense of securing a read margin. There was a problem that it was not possible.
[0023]
Also, considering the evaluation and analysis of the read cells after UV erasing, the word line potential cannot be externally changed in the word line boosting method, and the conventional flip-flop type sense amplifier 10 is used. According to the method of comparing the selected read cell 3 and the reference cell 4, the threshold V _th There was a problem that it could not be monitored.
[0024]
[Problems to be solved by the invention]
As described above, in a read operation of a conventional nonvolatile memory, particularly a UV erasing type EPROM using a precharge / discharge method, a read cell and a reference cell are connected to two inputs of a sense amplifier including an F / F circuit, respectively. By inputting the potential of the bit line, and applying a boosted potential to the word line and the reference word line, operation with low power supply voltage and low power consumption has been enabled, and a read operation with a wide voltage range has been realized.
[0025]
However, in this read operation, the threshold voltage V _th And cell current I _cell However, there is a problem that it is not possible to monitor in detail whether or not the read cell after UV erasing has been erased to a sufficient extent to secure an operation margin.
[0026]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in consideration of the threshold voltage V of a read cell. _th And cell current I _cell It is an object of the present invention to provide an EPROM capable of monitoring details of the read and the like and verifying whether or not a read cell after UV erasing has been erased to a sufficient extent to secure an operation margin.
[0027]
[Means for Solving the Problems]
In the EPROM of the present invention, the read cell threshold V _th And cell current I _cell And a power supply of the word line driving level shifter in the test mode. _PP , And by setting the word line potential to an arbitrary value and reading it out, the cell threshold voltage V _th And cell current I _cell , And accurately selecting defective read cells due to threshold variation after UV erasing.
[0028]
In the test mode, the effect of the variation of the reference cell is avoided by using a single-ended sense amplifier including the F / F circuit (single input is used for the differential input). Regardless of the read cell threshold V _th And cell current I _cell To be able to monitor.
[0029]
Specifically, the present invention The nonvolatile semiconductor memory of the aspect A read cell array in which memory cells for data storage are arranged in m rows and n columns (m and n are integers equal to or greater than 1), and a one-row reference including n reference memory cells that are turned on when selected. A cell, m word lines commonly connected to the control gates of the read cells in the same row in the read cell array, and one reference word commonly connected to the control gates of the one row of reference cells. And a booster circuit for applying a boosted potential to the word line and the reference word line at the time of reading, and an output potential of the booster circuit as a power supply for the word line and the reference word line. writing A power supply switching circuit for switching between an output potential from the power supply for use and the power supply switching circuit, writing A test mode for outputting a potential that can be set to an arbitrary value from the write power supply during an operation period other than the operation is provided. And a control circuit for setting the reference word line to a non-selected state in the test mode. It is characterized by the following.
[0030]
Also, The nonvolatile semiconductor memory is a flip-flop type. A read operation is performed by including a sense amplifier and detecting a voltage change in discharging the precharged bit line voltage.
[0031]
Preferably, the power supply switching circuit includes a two-input NOR circuit that inputs a switching signal for switching between a read operation and a write operation and a mode signal for selecting the test mode, and an output from the two-input NOR circuit via an inverter. First and second level shifters connected in parallel to each other, third and fourth level shifters connected in parallel to the output of the two-input NOR circuit, and first to fourth MOS transistors connected in series Consisting of
The power supply terminals of the first and third level shifters are connected to the output of the power supply for writing, and the power supply terminals of the second and fourth level shifters are connected to the output of the booster circuit. Outputs of the fourth to fourth level shifters are connected to gates of the first to fourth MOS transistors connected in series, respectively.
The output of the power supply for writing is connected to the power supply terminal on the drain side of the first to fourth MOS transistors connected in series, and the output of the booster circuit is connected to the power supply terminal on the source side thereof. , The substrates of the first and third MOS transistors are connected to respective drains, and the substrates of the second and fourth MOS transistors are connected to respective sources,
One of an output potential of the writing power supply and an output potential of the booster circuit is output from a connection point of the second and third MOS transistors.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a circuit configuration of an EPROM according to a first embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 5 are denoted by the same reference numerals, and detailed description will be omitted.
[0033]
The memory planes A and B and the sense amplifier 10 include, as peripheral circuits, a column decoder 13 for receiving a column address signal, a level shifter 14 for controlling the output level, a row address signal and a selection signal SLCT for the memory planes A and B. ₁ In response, a row decoder 15 for selecting the word line 6, a level shifter 16 for controlling the output level thereof,
Select signal SLCT for memory planes A and B ₀ And a signal EV for forcibly deselecting the reference word line at the time of writing. _PP And a reference cell word line selection circuit 17 for selecting the reference word line 6a, a level shifter 18 for controlling the output level thereof,
A precharge generating circuit 19 for inputting a precharge signal PR (bar) to the precharge transistor 9; _BIAS And a discharge signal generation circuit 21 that outputs a discharge signal DIS to the discharge transistor 5.
[0034]
As described above, conventionally, the power supply voltage V _CC Is boosted to V _BB , And applying the same to a word line and a reference word line, an EPROM with a wide read operation range that operates down to a low power supply voltage has been realized.
[0035]
However, generally, in the booster circuit 22, V _CC Cannot be changed continuously, and the threshold voltage of the cell cannot be monitored by reading the word line with an arbitrary potential.
[0036]
Therefore, in the EPROM of the present invention, a power supply switching circuit 23 newly operated by the MODE signal is additionally provided, and the write voltage V which can be set arbitrarily from the outside is increased. _PP Is input, and the normal operation mode and the test mode are switched by the MODE signal. In the test mode, the voltage applied to the word line and the reference word line can be arbitrarily set via the level shifters 16 and 18, respectively.
[0037]
An example of the power supply switching circuit 23 that switches the SWR according to the MODE signal will be described with reference to FIG. Conventionally, SWR is V _CC Boosted potential V _BB , Write voltage V during writing _PP In contrast, in the circuit shown in FIG. 2, when the MODE signal is "1", the write voltage V which can be arbitrarily set from the outside as SWR is changed. _PP Is output. That is, when the MODE signal is set to “1”, the power of the level shifter 16 of the row decoder 15 is changed to V _PP And the level of the word line can be set to an arbitrary potential.
[0038]
A power supply switching circuit 23 shown in FIG. 2 includes a two-input NOR circuit 24 that inputs a switching signal SW for switching between a read operation and a write operation in a normal operation mode, and a signal MODE for selecting the normal operation mode and a test mode. First and second level shifters 26 and 27 connected in parallel to the output of the two-input NOR circuit 24 via an inverter 25, and third and second level shifters 26 and 27 connected in parallel to the output of the two-input NOR circuit 24. It comprises four level shifters 28 and 29 and first to fourth MOS transistors 30 to 33 connected in series. The level shifters 26 to 29 are all inverted logic level shifters.
[0039]
The power supply terminals of the first and third level shifters 26 and 28 are connected to the output V of the write power supply. _PP And the power supply terminals of the second and fourth level shifters 27 and 29 are connected to the output V of the booster circuit. _BB And the outputs of the first to fourth level shifters 26 to 29 are connected to the gates of the first to fourth P-type MOS transistors 30 to 33 connected in series, respectively.
The drain-side (30-side) power supply terminal of the first to fourth P-type MOS transistors 30 to 33 connected in series is connected to the output V of the write power supply. _PP Is connected to the power supply terminal on the source side (33 side), and the output V _BB Are connected, the substrates of the first and third P-type MOS transistors are connected to respective drains, and the substrates of the second and fourth P-type MOS transistors are connected to respective sources. 2. From the connection point of the third P-type MOS transistor, the output potential V _PP And the output potential V of the booster circuit _BB Is output as the output SWR.
[0040]
In this way, in the normal operation mode in which MODE is “0”, SW becomes “0” during the read operation, and VWR is applied to SWR. _CC Boosted potential V _BB Is output, SW becomes “1” during the write operation, and the write voltage V is applied to SWR. _PP Is output.
[0041]
In the test mode in which MODE is “1”, the write voltage V is applied to SWR. _PP Is output, and as described above, V _PP Can be set to any value externally, and by applying it to the word line and reference word line, the threshold value of the cell after UV erasure can be monitored.
[0042]
Next, referring to FIG. _cell And the word line voltage level V _g Will be described. Note that the cell current I _cell V where is zero _g Is the cell threshold V _th Is equivalent to
[0043]
As described above, the word line voltage level V _g Can be arbitrarily set, so that the word line voltage level V _g At a lower voltage, in other words, under a condition in which the read margin is more strict, a slight change in threshold value due to injected electrons remaining in the floating gate of the cell after UV erasure is read, and the threshold value after UV erasure is verified. be able to.
[0044]
In FIG. 3, the horizontal axis represents the voltage level V applied to the word line. _g (Gate voltage), the vertical axis represents the cell current I _cell (Drain current). The solid line schematically shows the relationship between the gate voltage and the drain current of the "1" write cell and the reference cell. Since the neutral thresholds of the two cells are equal in design, the drain current rises at point P on the horizontal axis. However, as described above, the transconductance g of the “1” write cell is higher than that of the reference cell. _m Is larger, the “1” write cell has a steeper drain current I _cell Shows the rise of.
[0045]
On the other hand, in the "0" write cell indicated by the broken line in FIG. 3, since electrons are injected into the floating gate, the threshold value shifts in the positive direction as compared with the "1" write cell, and the rise of the drain current rises. Moves to point Q. However, the transconductance g _m Does not change, the drain current of the "0" write cell and the drain current of the "1" write cell have a relationship of parallel movement from P to Q. Note that the voltage values at points P and Q on the horizontal axis in FIG. 3 correspond to the neutral threshold of the reference cell and the threshold of the "0" write memory cell, respectively.
[0046]
In FIG. 3, the word line level can be arbitrarily set as described above, so that it is possible to perform the verification at a potential lower than the word line level at the time of normal reading. At this time, the difference between the current (drain current of both cells) flowing between the bit line on the read cell side and the bit line on the reference cell side at the time of reading and the difference between the currents at the time of verification are represented by vertical arrows R and V, respectively. It is shown.
[0047]
At this time, if the "1" write cell (the cell in which the erase state is maintained) is subjected to UV erasure and the erase state is insufficient, the intersection P of the "1" write cell in FIG. Side, the lengths of the arrows R and V both decrease accordingly. At this time, the decrease rate of the arrow V indicating the difference between the currents of the read cell and the reference cell at the time of verification is larger than the decrease rate of the arrow R indicating the difference between the currents of the read cell and the reference cell at the time of reading.
[0048]
The difference between the two is that the word line level V _g Is remarkable as is smaller, and in some cases, the sign may be inverted. From this, it can be seen that the lower the word line level at the time of verification, the easier it is to detect a cell whose erasure state in UV erasure is insufficient by the verify eye operation.
[0049]
As described above, by focusing on the difference between the cell currents flowing through the read cell and the reference cell, it becomes possible to indirectly monitor the threshold value of the cell, and to lower the verify voltage compared to the read voltage. Accordingly, a slight increase in the threshold value generated in the lead cell can be monitored with extremely high sensitivity. In other words, after UV erasing, it is possible to easily determine the presence of an incompletely erased cell whose threshold value is in the immediate vicinity of the read margin. It can be prevented before it happens.
[0050]
Further, as shown in FIG. 4, when the MODE signal is "1", by combining with a circuit that does not select the selection signal on the reference cell side, there is no influence of the threshold cell variation of the reference cell, and purely. Input data of the sense amplifier corresponding to the threshold value of the read cell is obtained.
[0051]
That is, in FIG. 4, if the MODE signal is "1", the output of the NOR gate 24 becomes "0", and the output of the reference cell word line selection circuit 17 becomes the selection signal SLCT of the memory planes A and B. ₁ Become irrelevant.
[0052]
If the MODE signal is "0", the selection signal SLCT ₁ Selects the reference word line 6a via the reference cell word line selection circuit 17 and the level shifter 18.
[0053]
If the reference word line is not selected, the sense amplifier 10 operates as a single-ended amplifier, so that an output corresponding to only the threshold value of the read cell is obtained. In this way, a slight threshold shift after UV erasing can be easily monitored, and the influence of the reference cell is eliminated particularly on the "0" write side (the side where the threshold value of the cell is high). It is possible to accurately verify the 0 "written state.
[0054]
The present invention is not limited to the above embodiment. For example, in the first embodiment, an EPROM that performs writing and reading of binary data has been described. However, if the power supply switching circuit of the present invention is modified, it is possible to provide an EPROM that operates similarly for multi-valued data. it can. Also, the case where the level shifter of the power supply switching circuit has an inverted logic has been described. However, if the P-type MOS transistor is changed to an N-type, a non-inverted logic level shifter can be used.
[0055]
In the first embodiment, the case where the change in the threshold value after the UV erasure is monitored has been described. However, the present invention is not necessarily limited to the UV erasure. Electrically erasable EEPROM (Electrically Erasable and Programmable Read Only)
Memory) can be similarly implemented.
[0056]
In the first embodiment, the case where the NOR type cell array is provided has been described. However, the read operation of the present invention can be applied to the NAND type cell array by changing peripheral circuits. In addition, various modifications can be made without departing from the scope of the present invention.
[0057]
【The invention's effect】
As described above, according to the EPROM of the present invention, a word line is driven by a non-volatile semiconductor memory operable with a low power supply voltage and low power consumption, in particular, a boosting power supply supplied by a boosting circuit, and a precharge / discharge method is used. In the memory that performs reading, the potential of the word line can be arbitrarily applied from the outside, and the threshold value of the cell can be monitored indirectly by reading the memory by setting the potential of the word line arbitrarily. For example, it is possible to accurately select defective cells due to variations in the threshold voltage of cells after UV erasing.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of an EPROM according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a power supply switching circuit of the present invention.
FIG. 3 is a diagram showing a relationship between a cell current and a word line level.
FIG. 4 is a partial configuration diagram of a circuit that deselects a reference word line.
FIG. 5 is a diagram showing a configuration of a conventional EPROM cell array and a sense amplifier.
[Explanation of symbols]
1 .... I-type transistor
2: Column select transistor
3: Lead cell group
4: Reference cell group
5 ... Discharge transistor
6 ... word line
6a: Reference word line
7 ... source line
8 ... bit line
9 ... Precharge transistor
10 Sense amplifier
11 ... Memory side A
12 ... Memory side B
13 ... column decoder
14, 16, 18 ... Level shifter
15 Row decoder
17 Word line selection circuit for reference cell
19 ... Precharge signal generation circuit
20 ... Bias circuit
21 ... Discharge signal generation circuit.
22 ... Booster circuit
23 Power supply switching circuit
25… Inverter
26… NOR circuit
26-29 ... Level shifter
30-33 ... PMOS transistor

Claims (3)

A read cell array in which memory cells for data storage are arranged in m rows and n columns (m and n are integers of 1 or more);
One row of reference cells consisting of n reference memory cells that are turned on when selected,
M word lines commonly connected to control gates of read cells in the same row in the read cell array,
One reference word line commonly connected to the control gates of the one row of reference cells;
A booster circuit for applying a boosted potential to the word line and a reference word line at the time of reading;
A power supply switching circuit that switches between an output potential of the booster circuit and an output potential from a writing power supply as a power supply of the word line and a reference word line;
The power switching circuit is in the operation period excluding the write operation, Bei example a test mode for outputting a settable potential to any value from the write power,
A non-volatile semiconductor memory , comprising: a control circuit for setting the reference word line to a non-selection state in the test mode . The non-volatile semiconductor memory comprises a flip-flop type sense amplifier by detecting the voltage change at the discharge of the precharged bit line voltage, according to claim 1, characterized in that the read operation Non-volatile semiconductor memory. The power supply switching circuit includes a two-input NOR circuit that inputs a switching signal for switching between a read operation and a write operation and a mode signal for selecting the test mode, and is connected in parallel to an output of the two-input NOR circuit via an inverter. First and second level shifters, third and fourth level shifters connected in parallel to the output of the two-input NOR circuit, and first to fourth MOS transistors connected in series,
The power supply terminals of the first and third level shifters are connected to the power supply for writing, and the power supply terminals of the second and fourth level shifters are connected to the output of the booster circuit. The outputs of the four level shifters are respectively connected to the gates of the first to fourth MOS transistors connected in series,
An output of the writing power supply is connected to a power supply terminal on a drain side of the first to fourth MOS transistors connected in series, and a source side of the first to fourth MOS transistors connected in series. The power supply terminal is connected to the output of the booster circuit,
Substrates of the first and third MOS transistors are connected to respective drains, and substrates of the second and fourth MOS transistors are connected to respective sources and are connected to the second and third MOS transistors. 3. The nonvolatile semiconductor memory according to claim 1, wherein one of an output potential of the writing power supply and an output potential of the booster circuit is output from a connection point.

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