JP3414587B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable / erasable non-volatile semiconductor memory device, and particularly to grouping non-volatile memory cells with a judgment voltage different from a desired verify judgment voltage and grouping them into groups. The present invention relates to a nonvolatile semiconductor memory device in which an appropriate voltage is applied to a bit line to adjust a writing speed.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices have the advantage that the data stored in the memory are not lost even when the power is turned off. Therefore, the demand for portable telephones, pagers and the like has greatly increased. A flash memory, which is a non-volatile semiconductor memory device that can be electrically collectively erased, can configure a memory cell with one transistor, unlike a two-transistor byte type non-volatile semiconductor memory device. It is possible to reduce the size of the disk, and it is expected to be used as a substitute for a large-capacity magnetic disk.

In these non-volatile semiconductor memory devices, memory cells composed of MOS transistors having a floating gate are arranged in a matrix to form a memory cell, and a tunnel phenomenon or impact ionization phenomenon is used to make the floating gate a floating gate. Electrons are injected, the threshold value of the MOS transistor is changed, and information is stored by the change.
Further, the electrons injected into the floating gate are confined in the floating gate due to the energy barrier. Therefore, the information once stored in the floating gate is not lost, and it functions as a nonvolatile memory device.

Further, in the nonvolatile semiconductor device, data is stored by setting the threshold level of a MOS transistor forming a memory cell to a binary value of a high state (a state where data is accumulated) and a low state (an erased state). There are two types, one is for storing data and the other is for storing data with the threshold level being multi-valued (three or more).

Here, the former non-volatile semiconductor memory device capable of binary storage will be described by taking a NAND flash memory as an example. FIG. 14 shows a main block diagram of the nonvolatile semiconductor memory device. Nonvolatile semiconductor memory device 993
Is a row decoder 994, a column decoder 995, an I /
It is composed of an O buffer, a sense amplifier block 997, a column gate transistor group 998, and a memory cell array 999.

A memory cell array 999 in which NAND type memory cells are arranged in a matrix has thousands of word lines and thousands of bit lines. One end of the word line is connected to the row decoder 994, and the row decoder 994 selects the word line based on an external address signal. Further, one end of the bit line is connected to the column transistor group 998, and the column transistor group 998 receives a signal decoded by the column decoder 995 based on an address signal from the outside, and selects the selected bit line to the sense amplifier block 997. Connect to. The signal sense-amplified by the sense amplifier block 997 is transferred to the I / O buffer 99.
6, and the I / O buffer 996 interfaces with the outside of the nonvolatile semiconductor memory device 993.

Next, FIG. 15 shows a memory cell array 999,
Column gate transistor group 998, column decoder,
A detailed diagram of the row decoder portion is shown. Where BL1
BL4 bit line, WL1 to WL5 word lines, 99
Reference numeral 2 indicates a NAND memory cell, and 989 indicates a write and verify circuit.

FIG. 16 shows a detailed view of the NAND type memory cell 992. One NAND memory cell 992
Are memory cells MC11 to MC18 connected in series eight
Each of the memory cells MC11 to MC18 has a floating gate for accumulating electrons.

Further, memory cells MC1 connected in series
One end of each of 1 to MC18 has a first selection transistor SGD.
The other ends of the memory cells MC11 to MC18 connected to the bit line BL1 via 1 and connected in series are connected to the common source line via the second selection transistor SGS1. All NAND memory cells 992 are configured as described above.

FIG. 17 is a sectional view of the NAND type memory cell 992 on the integrated circuit. A P-WELL is formed on an N-type semiconductor substrate (N-SUBSTRATE), and memory cells MC11 to MC1 are formed on this P-WELL.
8. Select transistors SGS1 and SGD1 are formed. Further, the diffusion layer N + used as the source / drain of these transistors is shared with the adjacent transistor, and the other diffusion layer of the selection transistor SGS1 is connected to the bit line.

Next, the write operation of this nonvolatile semiconductor memory device will be described. FIG. 18A shows a detailed circuit diagram of the memory cell array 992 and the write / verify circuit 989.

As shown in FIG. 18, one end of the current path of the NAND type memory cell array 992 is connected to the bit line BL1, and this bit line BL1 is connected to the column gate via the write / verify circuit 989. .

A write / verify circuit 989
Has a latch sense circuit 989 in which an inverter I and a clocked inverter CI are connected in antiparallel. The node N1 is connected to the bit line BL1 via the transistor Q1, and the signal φ1 is applied to the gate terminal of the transistor Q1.

Two transistors Q11 and Q12 connected in series are connected to the bit line BL1 and the high power supply voltage VD.
The gate terminal of the transistor Q12 is connected to the signal CON, and the gate terminal of Q11 is connected to the node N1 and the column gate.

A transistor Q is provided on the bit line BL1.
9 and Q10 are connected, and a signal b is applied to these gate terminals.
A signal PRE (meaning an inverted signal of PRE) and a signal RST are provided.

Next, the write operation of the nonvolatile semiconductor memory device will be described. Here, the memory cell MC11
An example will be described in which "0" data is written to. First, the signal RST is set to a high level voltage (hereinafter, written as H or 1) and the transistor Q10 is turned on to reset the bit line BL1. Then, the signal bPRE is set to a low level voltage (hereinafter, L or 0), and the transistor Q9 is turned on, so that the bit line B
Precharge L1 to VM (eg, 10V). After that, the transistor Q9 is turned off, and the bit line BL
Float 1

Next, the selection transistor SGD1 is turned on and the selection transistor SGS1 is turned off. Also,
Select word line WL11 to Vpp (for example, 20V),
The non-selected word lines WL12 to WL18 are set to VM (for example, 1
0V) is applied. Therefore, the selection transistor SGS1
All other than the above are turned on.

Next, the write signal is latched by the latch circuit 988 from the column gate, and the potential of the node N1 becomes L.
Becomes After that, the signal φ1 is set to H, and the transistor Q1
When turned on, the bit line BL1 is discharged and its potential becomes 0V.

Therefore, unselected memory cells MC12 to MC
Since only a low voltage of 10 V is applied between the control gate and drain of 18, no data is written to this memory cell, but a high voltage of 20 V (20 V-0 V) is applied between the control gate and drain of the selected memory cell MC11. Is applied, and data is written in this memory cell.

FIG. 19 shows such a state. As shown in FIG. 19 (1), in this case, the drain terminal D of the selected memory cell MC11 is marked with 0 V and the control gate CG is marked with 20 V.
Electrons are injected into the floating gate FG by an FN tunnel current.

Further, FIG. 19B shows a distribution diagram of the number of threshold voltages of the memory cells. As shown in FIG. 19 (2), when electrons are injected into the floating gate, the threshold voltage of the memory cell in the erased state "1" transits to the storage state "0" having a high threshold voltage. .

Further, all memory cells used in the nonvolatile semiconductor memory device do not have the threshold value raised to the same extent, but vary depending on individual memory cells. Therefore, the threshold value of the memory cells in the storage state has a certain number distribution. For example, the threshold range R0 for "0" data
Is -2.5V to -1.5V, and the threshold range R1 for "1" data is 1.5V to 2.5V.

On the other hand, since a voltage as low as 10 V is applied between the control gate and drain of the non-selected memory cell, no electrons are injected into the floating gate of the non-selected memory cell, and the non-selected memory cell stores "1" data. Will remain.

As described above, the data is written only in the selected memory cell, and the writing operation is completed. Next, the verify operation for checking whether the data written in the memory cell is normal will be described. Here, a case where "0" data is written in the memory cell MC11 will be described as an example.

First, the signal RST is set to a high level voltage (hereinafter referred to as H or 1) to turn on the transistor Q1.
By turning 0 on, the bit line BL1 is reset. Then, the signal bPRE is changed to a low level voltage (hereinafter, L
Alternatively, the bit line BL1 is precharged to Vcc (for example, 5V) by turning it on (0) and turning on the transistor Q9. After that, the transistor Q9 is turned off and the bit line BL1 is brought into a floating state.

Next, select transistors SGD1 and SG
Turn on S1. Further, the selected word line WL11 is applied to the verify voltage Vvfy (for example, 1.5V), and the unselected word lines WL12 to WL18 are applied to Vcc (for example, 5V).

Here, the threshold voltage of the selected memory cell is
If it is lower than the verify voltage Vvfy, this memory cell is turned on and the potential of the bit line BL1 is discharged from H to L. When the threshold voltage of the selected memory cell is higher than the verify voltage Vvfy, this memory cell is OF
After that, the potential of the bit line BL1 remains H and does not discharge.

A summary of the above is shown in FIG. When the potential of the node N1 is 0, “0” data is written in the selected memory cell, and when verification is performed in this state, the potential of the bit line BL1 precharged to the high potential (Vcc) is Depending on the threshold
It is determined whether to discharge to GND (0V) or to remain H and not discharge.

On the other hand, when the potential of the node N1 is 1, the selected memory cell remains "1" data, and if verification is performed in this state, the bit line BL precharged to a high potential is
No. 1 did not discharge and remained at high potential. This bit line BL
By sensing the change in the potential of 1, it is determined whether or not the data written in the selected memory cell is normal. According to this determination, if the data written in the selected memory cell is normal, the process ends. If abnormal, the data is written again.

FIG. 2 shows this series of sequences.
It is 0 (2). As shown in FIG. 20B, address data is input to the nonvolatile semiconductor memory device, and a memory cell is selected based on this address data (step 1). After that, data is written to the selected memory cell (step 2), and a verify operation (step 3) for determining whether the written data is normal is performed.

When the result of the verify operation is received and the operation is normal, a series of operations is completed (step 4). On the other hand, if there is an abnormality, data is again written to this memory cell, and this operation is repeated until the result of verification becomes normal. As described above, the write and verify operations are completed.

When the above operation is completed, the data written in the nonvolatile memory becomes a normal value, and the threshold voltage is distributed in the range of R0 (1.5V to 2.5V in this case). This is true (see Figure 19).

[0033]

As described above, the threshold voltage has a certain distribution width. Next, the distribution width of the threshold voltage and malfunction of the nonvolatile semiconductor memory device will be described. . Consider a case where the memory cell MC11 in FIG. 16 is in the written state (“0” data) and the data in the memory cell MC12 is read. As described above, when reading data, the selected word line (in this case,
(Equivalent to WL12) is applied with a read voltage, for example, 0 V, and unselected word lines WL11, WL13 to WL18,
5V is applied to WL1S and WL1D. That is, all except the selected memory cell MC12 are turned on.

In this state, the threshold voltage of the selected memory cell MC12 determines whether the selected memory cell MC12 is turned on or off. Selected memory cell MC12 is O
Then, all the elements in the memory cell 992 are turned on, and the bit line BL1 is connected to VS. When the selected memory cell MC12 is turned off, the current path of the memory cell 992 is cut off.

FIG. 21 shows a distribution of threshold voltage numbers. When the distribution width R of the threshold voltage is wide, if the threshold voltage of the memory cell MC11 is 5 V or more, the memory cell M
C11 does not turn on but turns off. Therefore, regardless of the threshold voltage of the memory cell MC12 from which data is read, the current path of the memory cell 992 is cut off, and the nonvolatile semiconductor memory device does not operate normally. Therefore, if the distribution width R is wide, the reliability of the nonvolatile semiconductor memory device is deteriorated.

Further, in order to narrow the distribution width in the prior art, it is necessary to perform writing and verifying in small steps,
Writing time becomes long. The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of narrowing the distribution width of the threshold voltage without significantly increasing the writing time. And

[0037]

A nonvolatile semiconductor memory device according to the present invention comprises a plurality of latch senses for holding data read from a nonvolatile memory cell and data written in the nonvolatile memory cell. Circuit, a voltage switching circuit for switching the potential of the bit line based on the data held in the plurality of latch / sense circuits, and the nonvolatile memory when verifying the data written in the nonvolatile memory. The first feature is to have a bypass circuit for forcibly setting the potential of the bit line to a high-level potential in accordance with the data to be written to the memory cell.

Further, in the verifying method of the nonvolatile semiconductor memory device according to the present invention, the first method for selecting one of the plurality of nonvolatile memory cells and writing the data in the selected nonvolatile memory cell Write operation, a judgment voltage is applied to the word line connected to the selected nonvolatile memory cell, the data written in the selected nonvolatile memory cell is read, and the threshold of the nonvolatile memory cell is read. To determine whether the voltage is in the erased state, in the written state, above the judgment voltage, or in the written state, below the judgment voltage. Threshold voltage determination operation and the selection by changing the potential of the bit line based on the determination of the threshold voltage in the threshold voltage determination operation. A second write operation that adjusts the write speed when writing data to the selected non-volatile memory cell, and a verify voltage is applied to the word line connected to the selected non-volatile memory cell. The first feature is to have a read operation for determining whether or not the threshold voltage of the memory cell is normal.

According to the present invention, after the write operation, the threshold voltage is determined to be in the erased state range, in the written state range or higher than the determination voltage, or in the written state range. It has a threshold voltage judgment operation for judging whether it is in a range lower than the voltage, and based on the judgment result, the voltage applied to the bit line is optimized and the writing speed at the time of the next writing operation is set. By adjusting, the width of distribution of the threshold voltage is narrowed. Since the present invention is configured as described above, it is possible to suppress an increase in write time and narrow the threshold distribution width of the nonvolatile memory cell.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described in detail with reference to the drawings. The schematic view of the nonvolatile semiconductor memory device is as shown in FIG. 14, the enlarged view of the memory cell portion is as shown in FIG. 15, and the NAND type memory cell is as shown in FIG.

FIG. 1 is a schematic diagram of a nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 1, the nonvolatile semiconductor memory device according to the present invention comprises a memory cell, a first sense / latch circuit, a second sense / latch circuit, a voltage switching circuit, and a bypass circuit.

The bit line BLi connected to the memory cell is connected to the first sense / latch circuit. This first sense / latch circuit is for writing data to the memory cell,
Also, it is for latching the data read from the memory cell, and also acts as a sense amplifier when reading the data from the memory cell.

Further, the second sense / latch circuit connected to the bit line BLi serves to latch the data read from the memory cell at the time of read operation, and thus also operates as a sense amplifier. Further, unlike the first sense latch circuit, the second sense latch circuit is not used during the write operation.

The voltage switching circuit, which is also connected to the bit line BLi, switches the potential of the bit line BLi according to the information latched by the first and second sense / latch circuits.

Further, the bypass circuit verifies the data written in the non-volatile memory, and when the write data in the non-volatile memory cell is "1" (erased state),
This is for forcibly setting the potential of the bit line to a high level potential.

Next, FIG. 2 shows a detailed circuit diagram of the nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 2, in the memory cell array 100, the current paths of the non-volatile memory cells are connected in series, the selection transistors SGD and SGS are connected to both sides of the current path, and the memory cell array 100 is selected. It is connected to the bit line BLi via the transistor SGD.

The first sense / latch circuit 110 is connected to the bit line BLi via the selection transistor Q1 and is composed of an inverter 130 and a clocked inverter 140 connected in antiparallel. The second sense / latch circuit has the same structure. Further, control signals bLAT1 and bLAT2 are supplied to the clocked inverters 140 and 160, respectively.

The voltage switching circuit 160 is composed of a transistor Q8 and four transistors Q4, Q5, Q6, Q7 connected in series between the reference voltage Vref and GND, and the gate terminal of the transistor Q4 is a node bN1.
(Meaning the inverted potential of N1), the gate terminal of the transistor Q7 is connected to the node N1.

The gate terminal of the transistor Q8 is connected to the node bN1, the drain terminal is connected to the node N3, and the source terminal is connected to the node N1. The node N3 is connected to the bit line BLi via the selection transistor Q3.

The bypass circuit 170 has transistors Q11 and Q12 whose current paths are connected in series, and the gate terminal of the transistor Q11 is connected to the column gate and the node N1. Also, the transistor Q
A signal CON is supplied to the 12 gate terminals.

In addition, the memory cell array 10 shown in FIG.
As shown in FIG. 0, this embodiment takes a NAND type memory cell array as an example. Next, FIG. 3 shows a program sequence used in this embodiment.

In the address / data input operation of the program sequence shown in FIG. 3, via the column gate,
A predetermined potential for writing data is latched in the latch / sense circuit 110.

Next, in the first program operation,
Data is written in the selected memory cell based on the potential latched in the latch / sense circuit 110. Then, in the threshold read operation, the potential of the bit line changes according to the state of the threshold voltage of the memory cell written in the first program operation described above. The potential of the bit line is sensed and latched by the latch sense circuit 120.
At this time, based on the data latched by the latch / sense circuits 110 and 120, the state of the threshold voltage of the selected memory cell is set to three states (“1” data write state,
It is classified into a written state but not fully written and a sufficiently written state.

Next, in the second programming operation (simply referred to as programming in FIG. 3), the voltage switching circuit is selected according to which of the above-mentioned three states the selected memory cell is in. 160 charges the bit line to a predetermined potential. Data is written again in the selected memory cell according to the potential of the bit line. At the time of this writing, the writing speed is adjusted according to the state 3 of the selected memory cell, and the width of the threshold voltage of the selected memory cell can be shortened (details will be described later).

Next, in the verify operation, it is judged whether or not the threshold voltage of the selected memory cell is normal, and if normal, a series of sequence is ended. If the threshold voltage of the selected memory cell is abnormal, the program and verify operations are repeated until it becomes normal.

Next, the series of program sequences shown in FIG. 3 will be described in more detail with reference to FIG. In a non-volatile semiconductor memory device, normally, a state in which the threshold voltage of a memory cell is low is an erased state (“1” data), and a state in which the threshold voltage is high is a written state (“0”).
Data). Here, all the memory cells MC0 to MC0
It is assumed that MC15 is in the erased state, that is, in "1" data. In the following description, the memory cell MC15
The case of writing data to the memory will be described as an example.

First, the address / data input operation will be described. The word line is selected according to the address data input to the nonvolatile semiconductor memory device shown in FIG. Here, it is assumed that the word line WL15 is selected. In addition, the latch
A predetermined potential is latched in the sense circuit 110.
In the case of writing "0" data, the low level potential (L) is held at the node N1.

Next, the first write operation will be described. Signal RST is a high level voltage (hereinafter referred to as H)
To turn on the transistor Q10 to turn on the bit line BL.
i is reset. That is, it is set to the GND potential. Next, set the signal bPRE to L and turn on the transistor Q9.
The bit line to the write inhibit voltage VM1 (for example,
10V) and then turn off the transistor Q9.

Further, a high level voltage VM2 (for example, 12V) is applied to the non-selected word lines WL0 to WL14,
Turn them on. Further, the selection transistor SGS is turned off and the selection transistor SGD is turned on. Further, a write voltage (for example, 20V) is applied to the selected word line WL15.

Then, the signal φ1 is set to H to turn on the transistor Q1. Then, the node N1 changes to the bit line BL.
connected to i. At this time, since the potential of the node N1 is L, the potential of the bit line BLi is discharged from H to L.

When the bit line BLi is discharged to L, a potential difference of 20V is generated between the channel portion of the selected memory cell MC15 and the gate terminal (terminal connected to the selected word line WL15). Therefore, electrons are injected into the floating gate of the selected memory cell MC15 and data is written. In other words, the threshold voltage of the selected memory cell MC15 rises and becomes "0" data.

In addition, unselected memory cells MC0 to MC14
Channel portion and gate terminal (non-selected word lines WL0 to WL0
A potential difference of 12V is not generated between the terminals connected to WL14). Therefore, unselected memory cells MC0 to MC
No electrons are injected into the floating gate of 14 and no data is written. In other words, the threshold voltage of the selected memory cells MC0 to MC14 remains unchanged and "1" data is retained. This completes the first program in FIG.

Next, the threshold value read operation (threshold voltage determination operation) will be described. The signal RST is set to H, the transistor Q10 is turned on, and the bit line BLi is reset. That is, it is set to the GND potential. Next, the signal bP
RE is set to L, the transistor Q9 is turned on, the bit line is precharged to Vcc (for example, 5 V), and then the transistor Q9 is turned off to set the potential of the bit line to a floating state.

Further, Vcc (for example, 5V) is applied to the unselected word lines WL0 to WL14 to turn them on. Further, the threshold judgment voltage V is applied to the selected word line WL15.
Apply L. In addition, the selection transistors SGS and SGD
To ON state.

In the first programming operation described above, the threshold voltage of the selected memory cell MC15 has risen, and the threshold judgment voltage VL is set to be at the center of the threshold distribution (this The setting method will be described later). Here, in the “0” data, a region higher than the threshold judgment voltage VL is defined as a region L2, and a lower region is defined as a region L1 (see FIG. 4).

Consider the case where the threshold voltage of the selected memory cell MC15 in which data is written is in the region L1 in the first programming operation. Since the potential VL of the selected word line WL15 is higher than the threshold voltage, the selected memory cell MC15 is turned on and the bit line BLi is discharged from H to L. In addition, after waiting for a time required for discharging the bit line BLi, the clocked inverter 16 is set with bLAT2 = L.
0 is inactivated, signal φ2 is set to H, and transistor Q
Turn on 2. Then, the bit line BLi and the node N2 are connected.

Then, the clocked inverter 160 is activated by bLAT2 = H, and the sense / latch circuit 120 is activated.
The result of the threshold read is latched at node N2 of
In this case, since the bit line BLi is discharged to L, L is latched at the node N2. Also, the node N
The potential of 1 is in the L state, which is the written state as it is. The threshold value read operation is completed as described above (see FIG. 3).

Next, the first program operation described above,
FIG. 5 shows a summary of the potential states of the nodes N1 and N2 after the threshold read operation. As shown in FIG. 5, in the first program operation, the node N1 = L
As a result, "0" data is written in the selected memory cell MC15. In the subsequent threshold read operation,
As described above, the potential of the node N2 becomes L when the threshold voltage of the selected memory cell in which "0" data is written is in the region of L1.

When the threshold voltage of the selected memory cell in which "0" data is written is in the region L2, the threshold judgment voltage VL is lower than the region L2, so the selected memory cell MC15 is not turned on. . Therefore, the bit line BLi
Is not discharged, the potential of the node N2 becomes H.

In the first program operation,
When data is not written in the selected memory cell MC15,
The potential of the node N1 is set to H. In the subsequent threshold read operation, the potential held at the node N2 is
It is either L or H depending on the threshold value of the memory cell.

As described above, the two nodes N1 and N2 are
The potential of the memory cell after the programming operation is "1" data written state (L3), which is a written state but is not sufficiently written (L
It can be classified into three, 1) and a sufficiently written state (L2).

Next, the second programming operation will be described. Now, when the threshold voltage of the memory cell MC15 in which the data has been written in the first programming is in the region L1, as described above, the region L1 is in a state in which the data is written but is not sufficiently written. Is shown. Therefore, it is necessary to rewrite the selected memory cell to make it sufficiently written (area higher than VL).

When the threshold voltage of the memory cell MC15 after the first programming is in the region L2, the region L2
Indicates a state in which data is sufficiently written, as described above. Therefore, the memory cell in this state
I don't want to write much. That is, I want to slow down the writing speed.

When the threshold voltage of the memory cell MC15 after the first programming is 3 in the region L, the region L3
Indicates the state of writing "1" data as described above. Therefore, it is not desired to write any more data in the memory cell in this state.

As described above, the writing speed must be controlled according to the states (L1, L2, L3) of the memory cells after the first programming. In the present invention, the voltage switching circuit 160 according to the potentials of the nodes N1 and N2.
The bit line potential is controlled to control the writing speed.

The method of controlling the writing speed will be described below. Here, the memory cell MC1 after the first programming
An example will be described in which the threshold voltage of 5 is in the region L1. In this case, as shown in FIG. 5, the potentials of the nodes N1 and N2 after the first program and threshold read operations are set to L and L, respectively. At this time, node b
Since N1 and bN2 are H, the transistors Q4 and Q5 in the voltage switching circuit 160 are ON, and the transistors Q6 and Q are
8 is turned off. Therefore, the potential of the node N3 is GND
Becomes After that, the transistor Q3 is turned on by the signal φ3.
Setting to N drives the bit line. Then, 20V (20V-0V) is applied to the selected memory cell and writing is performed again.

When the threshold voltage of the memory cell MC15 after the first programming is in the region L2, as shown in FIG. 5, the nodes N1 and N2 of the nodes N1 and N2 after the first programming and the threshold value read operation are operated. The potentials are set to L and H, respectively. At this time, since the nodes bN1 and bN2 are H and L, respectively, the transistors Q6 and Q7 in the voltage switching circuit 160 are ON and the transistors Q5 and Q8 are OFF.
Becomes Therefore, the potential of the node N3 becomes Vref (for example, 1V). After that, the bit line is charged by turning on the transistor Q3 by the signal φ3. Then, 19V (20V-1V) is applied to the selected memory cell, and writing is performed again. However, at this time, 1
Since the voltage is as low as 9V, the writing speed becomes slow.

Further, when the threshold voltage of the memory cell MC15 after the first programming is in the region L3, as shown in FIG. 5, the nodes N1 and N2 after the first programming and the threshold read operation are performed. The electric potentials are set to H and *, respectively (however, * means either H or L). At this time, since the node bN1 is L, the transistor Q8 in the voltage switching circuit 160 is turned on. Therefore, the potential of the node N3 becomes the same as that of the node N1. That is, the potential of the node N3 becomes VM1. Signal φ3
By turning on the transistor Q3, the bit line is charged to VM1 (write inhibit voltage).

FIG. 5 shows the relationship between the potential of the charged bit line and the nodes N1 and N2. As shown in FIG.
The threshold voltage of the memory cell in which the data is written is L1,
In the area of L2 and L3, the potential of the bit line is set to G
Set to ND, Vref, VM1. Here, GND is 0V, Vref (reference voltage) is 1V, and VM1 (write inhibit voltage) is 10V.

As described above, the bit line is charged according to the result of the threshold read, and the selected memory cell MC15 receives 2 bits.
The second writing is performed. In the second write operation, the potential of the bit line is optimized according to the threshold state of the selected memory cell MC15, so that the write speed of the selected memory cell MC15 can be adjusted.

Next, the verify operation will be described.
The signal RST is set to H, the transistor Q10 is turned on, and the bit line BLi is reset. That's it, GND
Set to potential. Next, the signal bPRE is set to L, the transistor Q9 is turned on, and the bit line is set to Vcc (for example, 5
Precharge to V) and then turn off the transistor Q9.
Set to F, and the potential of the bit line is set to a floating state.

Further, Vcc (for example, 5 V) is applied to the unselected word lines WL0 to WL14 to turn them on. Further, the verify voltage Vv is applied to the selected word line WL15.
Apply fy. In addition, the selection transistors SGS, SG
Turn D on. The verify voltage Vvfy is assumed to be higher than the threshold judgment voltage VL.

The potential Vvfy of the selected word line WL15 is
When it is higher than the threshold voltage of the selected memory cell MC15,
The bit line is discharged from H to L, and the selected memory cell MC15
If below the threshold voltage, the bit line remains high.

After waiting a time required for discharging the bit line, the clocked inverter 140 is deactivated by bLAT1 = L, the signal φ1 is set to H, and the transistor Q1 is turned on.
N Then, the bit line BLi and the node N1 are connected.

Then, the clocked inverter 140 is activated by bLAT1 = H, and the sense / latch circuit 110 is activated.
The verification result is latched in the node N1 of the node. However, unlike the threshold read operation, in the verify operation, when writing “1” data to the selected memory cell MC15, the node N1 of the sense / latch circuit 110 must be held at H, so that the node N1 = H. The transistor Q11 is turned on, and when the signal CON = H, the transistor Q
Turn on 12. Therefore, the potential of the bit line is pulled up to hold the potential of the node N1 at H.

If the latched result is normal, the series of program sequences is completed. If the result is abnormal, writing and verify operation are repeated until the result is normal. This completes the series of program sequences shown in FIG.

FIG. 6 shows changes in the threshold voltage of the selected memory cell MC15 in the program sequence shown in FIG. The vertical axis shows the threshold voltage and the horizontal axis shows time.

As shown in FIG. 6, it is assumed that the distribution range of the threshold voltage of the selected memory cell after the first programming is R1 (time t1). As described above, the subsequent threshold read operation causes the threshold to change to the threshold judgment voltage V
The regions L2 and L1 are classified according to whether they are higher or lower than L. Based on this classification, the writing speed to the selected memory cell is controlled to perform the second writing. The time after the end of the second write operation is t2. At this time, the area L
The threshold voltage of the memory cell at 1 increases almost linearly. However, since the threshold voltage of the memory cell in the region L2 in the sufficiently written state is written at a slower writing speed, the slope becomes dull.

Due to this difference in inclination, the threshold distribution width R2 after the second write operation can be made narrower than the threshold distribution width R1 after the first write operation.
A memory cell having a threshold voltage in the region L1;
The reference voltage Vref described above is optimized so that the distribution range of the threshold voltage after the second writing of the memory cells having the threshold voltage in the region L2 matches at R2 (the optimum setting method will be described later). To).

When the second writing is completed, as shown in FIG. 3, verify is performed until the threshold voltage value is normal, that is, the threshold voltage exceeds the verify voltage Vvfy.
Repeat the write operation. In FIG. 6, time tn,
It corresponds to the range Rn.

Next, a method of setting VL and Vref will be described. After the first programming, the threshold value is read to obtain the distribution center VL and the distribution width R1. And 2
Applying VPP in the second program, VL-1 / 2 × R
Write from 1 to VTH2 which is the lower end of the range R2.

Next, in the second program, VPP-Vr
ef is applied to obtain Vref that prevents writing from VL to VTH2. The above is performed for chips having different writing speeds, and a correspondence table of VL and Vref is prepared.

In the test, after the first programming, the threshold value read is performed, VL is set at the center of the distribution, and Vr is set.
ef is obtained from the above correspondence table. Also, VLVref
Fuse Blow so that the voltage becomes a predetermined voltage.

Further, a timing chart of the program sequence shown in FIG. 3 is shown in FIG. FIG. 8 shows a timing chart of the address / data input operation, the first program operation, the threshold read operation, the second program operation, the verify operation, the third program, and the verify operation. In this case, the result of the first verify is abnormal, the result of the second verify is normal, and the series of program sequences is completed.

In this embodiment, the bit line is charged on the basis of the data latched by the two sense / latch circuits, and the write speed in the subsequent write operation is controlled, so that the write time is significantly increased. The distribution width of the threshold voltage can be narrowed without incident. As a result, malfunction of the nonvolatile semiconductor memory device can be suppressed.

Further, the transistors Q4, Q5, Q6 and Q7 connected between the reference voltage Vref and GND are simultaneously turned on.
Since N does not occur and a through current does not flow, power consumption does not increase. Next, a second embodiment according to the present invention will be described in detail with reference to the drawings. A schematic view of the nonvolatile semiconductor memory device is shown in FIG. 14, an enlarged view of a memory cell portion is shown in FIG.
The type memory cell is as already shown in FIG.

FIG. 9 is a schematic diagram of a nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 9, the nonvolatile semiconductor memory device according to the present invention includes a memory cell, a first sense / latch circuit, a second sense / latch circuit, and a voltage switching circuit. However, the first and second sense / latch circuits are of the forced inversion type. Further, in order to simplify the explanation, regarding the same parts as those in the first embodiment,
Use the same symbols.

The bit line BLi connected to the memory cell is connected to the first sense / latch circuit. This first sense / latch circuit is for writing data to the memory cell,
Also, it is for latching the data read from the memory cell, and also acts as a sense amplifier when reading the data from the memory cell.

The second sense / latch circuit connected to the bit line BLi is for latching the data read from the memory cell during the read operation, and also operates as a sense amplifier. Further, unlike the first sense latch circuit, the second sense latch circuit is not used during the write operation.

The voltage switching circuit, which is also connected to the bit line BLi, switches the potential of the bit line BLi according to the information latched by the first and second sense / latch circuits.

Next, FIG. 10 shows a detailed circuit diagram of the nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 10, in the memory cell array 100, the current paths of the non-volatile memory cells are connected in series, the selection transistors SGD and SGS are connected to both sides of the current path, and the memory cell array 100 is selected. It is connected to the bit line BLi via the transistor SGD.

The first sense / latch circuit 110 is connected to the bit line BLi via the selection transistor Q1 and is connected in inverse parallel to the inverters 130, 2 respectively.
And 30.

Further, the current paths of the transistors Q21 and Q22 are connected in series between the node bN1 and GND,
The control signal LAT1 is applied to the gate terminal of the transistor Q21.
Is supplied, and the gate terminal of Q22 is connected to the bit line. The second sense / latch circuit has the same structure.

The voltage switching circuit 160 is composed of a transistor Q8 and four transistors Q4, Q5, Q6 and Q7 connected in series between the reference voltage Vref and GND. The gate terminal of the transistor Q4 is a node bN1.
(Meaning the inverted potential of N1), the gate terminal of the transistor Q7 is connected to the node N1.

The gate terminal of the transistor Q8 is connected to the node bN1, the drain terminal is connected to the node N3, and the source terminal is connected to the node N1. The node N3 is connected to the bit line BLi via the selection transistor Q3.

In addition, the memory cell array 1 shown in FIG.
As shown in FIG. 00, this embodiment takes a NAND type memory cell array as an example. Next, FIG. 11 shows a program sequence used in this embodiment.

In the address / data input operation of the program sequence shown in FIG. 11, a predetermined potential for writing data is latched in the latch sense circuit 110 via the column gate.

Next, in the first program operation (Program in FIG. 11), data is written in the selected memory cell based on the potential latched by the latch / sense circuit 110.

Next, in the verify operation, it is judged whether or not the threshold voltage of the selected memory cell is normal, and if normal, a series of sequence is ended. If the threshold voltage of the selected memory cell is abnormal, the counter N is incremented.

Then, in the threshold read operation, the potential of the bit line changes according to the state of the threshold voltage of the memory cell written in the program operation described above. The potential of the bit line is sensed and latched by the latch sense circuit 120. At this time, the latch / sense circuit 110,
Based on the data latched in 120, the threshold voltage states of the selected memory cell are set to three states (“1” data write state, write state but not sufficiently written, and sufficiently written). State).

Next, in the second program operation,
The voltage switching circuit 160 charges the bit line to a predetermined potential depending on which of the above-mentioned three states the selected memory cell is in. Data is rewritten to the selected memory cell according to the potential of the bit line. In this writing, the writing speed is adjusted according to the three states of the selected memory cell, and the width of the threshold voltage of the selected memory cell can be shortened.

Next, the series of program sequences shown in FIG. 11 will be described in more detail with reference to FIG. In addition, in a non-volatile semiconductor memory device,
The state in which the threshold voltage of the memory cell is low is the erased state (“1”
Data) and a state where the threshold voltage is high is called a write state (“0” data). Here, it is assumed that all the memory cells MC0 to MC15 are in the erased state, that is, in "1" data. Further, in the following description, a case of writing data in the memory cell MC15 will be described as an example.

First, the address / data input operation will be described. A word line is selected according to the address data input to the nonvolatile semiconductor memory device shown in FIG. Here, it is assumed that the word line WL15 is selected. In addition, a predetermined potential is latched in the latch sense circuit 110 via the column gate. In this case, the low level potential (L) is held at the node N1.

Next, the first write operation will be described. Signal RST is a high level voltage (hereinafter referred to as H)
To turn on the transistor Q10 to turn on the bit line BL.
i is reset. That is, it is set to the GND potential. Next, set the signal bPRE to L and turn on the transistor Q9.
The bit line to the write inhibit voltage VM1 (for example,
10V) and then turn off the transistor Q9.

Further, a high level voltage VM2 (for example, 12V) is applied to the unselected word lines WL0 to WL14,
Turn them on. Further, the selection transistor SGS is turned off and the selection transistor SGD is turned on. Further, a write voltage (for example, 20V) is applied to the selected word line WL15.

Then, the signal φ1 is set to H to turn on the transistor Q1. Then, the node N1 changes to the bit line BL.
connected to i. At this time, since the potential of the node N1 is L, the potential of the bit line BLi is discharged from H to L.

When the bit line BLi is discharged to L, a potential difference of 20 V is generated between the channel portion of the selected memory cell MC15 and the gate terminal (terminal connected to the selected word line WL15). Therefore, electrons are injected into the floating gate of the selected memory cell MC15 and data is written. In other words, the threshold voltage of the selected memory cell MC15 rises and becomes "0" data.

Further, unselected memory cells MC0 to MC14
Channel portion and gate terminal (non-selected word lines WL0 to WL0
A potential difference of 12V is not generated between the terminals connected to WL14). Therefore, unselected memory cells MC0 to MC
No electrons are injected into the floating gate of 14 and no data is written. In other words, the threshold voltage of the selected memory cells MC0 to MC14 remains unchanged and "1" data is retained. This completes the first program in FIG.

Next, the verify operation will be described.
The signal RST is set to H, the transistor Q10 is turned on, and the bit line BLi is reset. That's it, GND
Set to potential. Next, the signal bPRE is set to L, the transistor Q9 is turned on, and the bit line is set to Vcc (for example, 5
Precharge to V) and then turn off the transistor Q9.
Set to F, and the potential of the bit line is set to a floating state.

Further, Vcc (for example, 5V) is applied to the unselected word lines WL0 to WL14 to turn them on. Further, the verify voltage Vv is applied to the selected word line WL15.
Apply fy. In addition, the selection transistors SGS, SG
Turn D on. The verify voltage Vvfy is assumed to be higher than the threshold judgment voltage VL.

The potential Vvfy of the selected word line WL15 is
When it is higher than the threshold voltage of the selected memory cell MC15,
The bit line is discharged from H to L, and the selected memory cell MC15
If below the threshold voltage, the bit line remains high.

After waiting the time required for the bit line to discharge, the signal LAT1 is set to H and the transistor Q21 is turned on.
Then, the potential of the bit line is latched. Where the signal φ
1 remains L.

At this time, when the node N1 is H in the "1" data write state, the node N1 holds H regardless of H / L of the bit line BLi. This is CON = H in FIG.
This has the same effect as pulling up the bit line and holding the node N1 at H.

When the node N1 is L in the "0" data write state, the node N1 holds L when the bit line is L, and the node N1 is forcibly inverted to H when the bit line is H.

If the latched result is normal, the series of program sequences is completed. If the result is abnormal, the counter N is incremented by 1. Next, the threshold value read operation (threshold voltage determination operation) will be described.

The signals RST and φ2 are set to H, the transistors Q10 and Q2 are turned on, and the bit line BLi is reset. That is, it is set to the GND potential. Here, the potential of the node N2 also becomes GND.

Next, the signal bPRE is set to L, the transistor Q9 is turned on, and the bit line is set to Vcc (for example, 5
Precharge to V) and then turn off the transistor Q9.
Set to F, and the potential of the bit line is set to a floating state.

Further, Vcc (for example, 5 V) is applied to the non-selected word lines WL0 to WL14 to turn them on. Further, the threshold judgment voltage V is applied to the selected word line WL15.
Apply L. In addition, the selection transistors SGS and SGD
To ON state.

Here, of the "0" data, a region higher than the threshold judgment voltage VL is defined as a region L2 and a region lower than the threshold judgment voltage VL is defined as a region L1 (see FIG. 4). In the first programming operation, the selected memory cell MC1 in which the data is written
Consider a case where the threshold voltage of 5 is in the region L1.

Since the potential VL of the selected word line WL15 is higher than the threshold voltage, the selected memory cell MC15 is turned on.
Then, the bit line BLi is discharged from H to L. Also, after waiting for a time necessary for discharging the bit line BLi, the signal L
AT2 is set to H to turn on the transistor Q23 to latch the potential of the bit line. Here, the signal φ2 remains L.

Now, considering the case where the threshold voltage is in the region L1, the selected memory cell MC15 is turned on and the bit line is discharged. Therefore, the transistor Q24 is OF
F, and the node N2 remains L.

On the other hand, when the threshold voltage is in the region L2,
The selected memory cell MC15 is turned off, and the bit line remains charged to H. Therefore, the transistor Q24 becomes O
N, the node N2 is forcibly inverted to H. Through the above operation, the result of the threshold read is latched at the node N2. The threshold read operation is completed as described above (see FIG. 11).

Next, the above-mentioned first program operation,
A summary of the potential states of the nodes N1 and N2 after the threshold read operation has already been shown in FIG. As shown in FIG. 5, in the first program operation, the node N1
= L, write "0" data to the selected memory cell MC15. Further, in the subsequent threshold value read operation, when the threshold voltage of the selected memory cell in which “0” data is written is in the region of L1, the potential of the node N2 is L.
The above is as described above.

When the threshold voltage of the selected memory cell in which "0" data is written is in the region L2, the threshold judgment voltage VL is lower than the region L2, so the selected memory cell MC15 is not turned on. . Therefore, the bit line BLi
Is not discharged, the potential of the node N2 becomes H.

In the first program operation,
When data is not written in the selected memory cell MC15,
The potential of the node N1 is set to H. In the subsequent threshold read operation, the potential held at the node N2 is L
Either H or H.

As described above, the two nodes N1 and N2 are
The potential of the memory cell after the programming operation is "1" data written state (L3), which is a written state but is not sufficiently written (L
It can be classified into three, 1) and a sufficiently written state (L2).

Next, the second programming operation will be described. Now, when the threshold voltage of the memory cell MC15 in which the data has been written in the first programming is in the region L1, as described above, the region L1 is in a state in which the data is written but is not sufficiently written. Is shown. Therefore, it is necessary to rewrite the selected memory cell to make it sufficiently written (area higher than VL).

When the threshold voltage of the memory cell MC15 after the first programming is in the region L2, the region L2
Indicates a state in which data is sufficiently written, as described above. Therefore, the memory cell in this state
I don't want to write much. That is, I want to slow down the writing speed.

When the threshold voltage of the memory cell MC15 after the first programming is 3 in the region L, the region L3
Indicates the state of writing "1" data as described above. Therefore, we do not want to write to the memory cell in this state.

As described above, the writing speed must be controlled depending on the states (L1, L2, L3) of the memory cells after the first programming. In the present invention, the voltage switching circuit 160 according to the potentials of the nodes N1 and N2.
The bit line potential is controlled to control the writing speed.

The method of controlling the writing speed will be described below. Here, the memory cell MC1 after the first programming
An example will be described in which the threshold voltage of 5 is in the region L1. In this case, as shown in FIG. 5, the potentials of the nodes N1 and N2 after the first program and threshold read operations are set to L and L, respectively. At this time, node b
Since N1 and bN2 are H, the transistors Q4 and Q5 in the voltage switching circuit 160 are ON, and the transistors Q6 and Q are
8 is turned off. Therefore, the potential of the node N3 is GND
Becomes After that, the transistor Q3 is turned on by the signal φ3.
By setting it to N, the bit line is charged. Then, 20V (20V-0V) is applied to the selected memory cell and writing is performed again.

When the threshold voltage of memory cell MC15 after the first programming is in region L2, as shown in FIG. 5, nodes N1 and N2 after the first programming and threshold read operation are The potentials are set to L and H, respectively. At this time, since the nodes bN1 and bN2 are H and L, respectively, the transistors Q6 and Q7 in the voltage switching circuit 160 are ON and the transistors Q5 and Q8 are OFF.
Becomes Therefore, the potential of the node N3 becomes Vref (for example, 1V). After that, the bit line is charged by turning on the transistor Q3 by the signal φ3. Then, 19V (20V-1V) is applied to the selected memory cell, and writing is performed again. However, at this time, 1
Since the voltage is as low as 9V, the writing speed becomes slow.

When the threshold voltage of the memory cell MC15 after the first programming is in the region L3, as shown in FIG. 5, the nodes N1 and N2 after the first programming and threshold read operation are The electric potentials are set to H and *, respectively (however, * means either H or L). At this time, since the node bN1 is L, the transistor Q8 in the voltage switching circuit 160 is turned on. Therefore, the potential of the node N3 becomes the same as that of the node N1. That is, the potential of the node N3 becomes VM1. Signal φ3
By turning on the transistor Q3, the bit line is charged to VM1 (write inhibit voltage).

FIG. 5 shows the relationship between the potential of the charged bit line and the nodes N1 and N2. As shown in FIG.
The threshold voltage of the memory cell in which the data is written is L1,
In the area of L2 and L3, the potential of the bit line is set to G
Set to ND, Vref, VM1. Here, GND is 0V, Vref (reference voltage) is 1V, and VM1 (write inhibit voltage) is 10V.

As described above, the bit line is charged according to the result of the threshold read, and the selected memory cell MC15 receives 2 bits.
The second writing is performed. In the second write operation, the potential of the bit line is optimized according to the threshold state of the selected memory cell MC15, so that the write speed of the selected memory cell MC15 can be adjusted.

FIG. 12 shows changes in the threshold voltage of the selected memory cell MC15 in the program sequence shown in FIG. The vertical axis shows the threshold voltage and the horizontal axis shows time.

As shown in FIG. 12, the distribution range of the threshold voltage of the selected memory cell after the (N-1) th programming is R
It is assumed that it is n-1 (time tn-1). As mentioned above,
By the threshold read operation thereafter, the regions are divided into regions L2 and L1 depending on whether the threshold is higher or lower than the threshold judgment voltage VL. Based on this classification, the write speed to the selected memory cell is controlled to perform the Nth write. The time after the end of the Nth write operation is tn.
At this time, the threshold voltage of the memory cell in the region L1 increases almost linearly. However, since the threshold voltage of the memory cell in the region L2 in the sufficiently written state is written at a slower writing speed, the slope becomes dull.

Due to this difference in inclination, the threshold distribution width Rn after the Nth write operation may be made narrower than the threshold distribution width Rn-1 after the (N-1) th write operation. it can.

Further, the distribution range of the threshold voltage of the memory cell having the threshold voltage in the region L1 and the memory cell having the threshold voltage in the region L2 after the Nth writing is R
The above-mentioned reference voltage Vref is optimized so that n will match (the optimum setting method will be described later).

After the Nth write is completed, the threshold voltage is normal, that is, the threshold voltage is the verify voltage Vvfy.
, The series of sequence ends. Next, VL
And a method of setting Vref will be described.

Among the cells of group L2, the cell having the highest threshold value is written by VPP-Vref and ΔVT.
Since the threshold value is increased by H2, the final threshold value distribution width is ΔVTH2.

Further, among the cells of the group L1, the cell with the highest threshold VL is written with VPP and ΔVTH
Since the threshold value increases by 1, the threshold distribution width is
The following conditions are necessary to suppress to TH2.

ΔVTH1 <= ΔVTH2 + (Vvfy-VL) Here (“<=” means “or less”) As described above, Vref is the write amount ΔVTH2 per VPP-Vref, that is, the request. Determined from the threshold distribution width.

Further, since ΔVTH1 is naturally determined from the write characteristics of the chip and Vvfy is determined at the time of circuit design, VL can be obtained from the above equation. Further, a timing chart of the program sequence shown in FIG. 11 is shown in FIG. FIG. 13 shows the threshold read operation, N-
The timing charts of the first program operation, the verify operation, the threshold value read operation, the Nth program, and the verify operation are shown.

In the present embodiment, the threshold judgment voltage VL is determined so as to reduce the threshold width at the Nth time, but at other times (Kth time, 1 <K <N), the threshold judgment voltage V L is determined.
You may decide L.

The detailed circuit diagram shown in FIG. 2 has been described with the program sequence shown in FIG. 3, and the detailed circuit diagram shown in FIG. 10 has been described with the program sequence shown in FIG. 2 may be applied to the circuit shown in FIG. 2, and the program sequence shown in FIG. 3 may be applied to the circuit shown in FIG.

In this embodiment, the bit line is charged on the basis of the data latched by the two sense / latch circuits, and the write speed in the subsequent write operation is controlled, so that the write time is significantly increased. The distribution width of the threshold voltage can be narrowed without incident. As a result, malfunction of the nonvolatile semiconductor memory device can be suppressed. Also, the transistors Q4, Q5, Q6, Q7 connected between the reference voltage Vref and GND are turned on at the same time.
Since no through current flows, power consumption does not increase.

[0158]

In the nonvolatile semiconductor memory device according to the present invention, a latch sense circuit and a voltage switching circuit are newly provided. Further, the potential of the bit line can be controlled based on the result of the threshold read operation, and the writing speed to the selected memory cell can be controlled. Therefore, the threshold voltage distribution width can be narrowed without significantly increasing the writing time.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a program sequence according to the first embodiment.

FIG. 4 is a distribution diagram of threshold voltage numbers of nonvolatile memory cells.

FIG. 5 is a table showing the potentials of bit lines according to the potentials of nodes N1 and N2.

FIG. 6 is a time transition diagram of the threshold voltage of the selected memory cell according to the first embodiment.

FIG. 7 is a threshold voltage determination potential VL and a reference voltage Vref.
The figure which showed the determination method of.

FIG. 8 is a timing chart of the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 9 is a schematic circuit diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a detailed circuit diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a program sequence according to the second embodiment.

FIG. 12 is a time transition diagram of the threshold voltage of the selected memory cell according to the second embodiment.

FIG. 13 is a program sequence according to the second embodiment.

FIG. 14 is an overall schematic diagram of a nonvolatile semiconductor memory device.

FIG. 15 is a detailed view of a memory cell array portion of the nonvolatile semiconductor memory device.

FIG. 16 is a diagram showing a NAND type memory cell array.

FIG. 17 is a cross-sectional view of a NAND type memory cell array on a wafer.

FIG. 18 is a detailed circuit diagram showing a latch / sense circuit portion in a conventional nonvolatile semiconductor memory device.

FIG. 19 is a diagram explaining a writing principle to a nonvolatile memory cell.

FIG. 20 is a diagram showing a program sequence in a conventional nonvolatile semiconductor memory device.

FIG. 21 is a diagram for explaining a malfunction in the conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

100 NAND type memory cell array 110 and 120 sense and latch circuits 160 voltage switching circuit 170 Bypass circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (15)

(57) [Claims] 1. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. A potential holding circuit connected to the bit line for holding data to be written in the nonvolatile memory cell and read data, and a threshold value range of the nonvolatile memory cell is predetermined. In a non-volatile semiconductor memory device that stores data depending on whether it is a first range lower than a value or a high second range, the potential holding circuit is a bypass circuit connected to the bit line, Based on the plurality of latch sense circuits connected to the bit lines and the data held in the plurality of latch sense circuits, the potential of the bit lines is turned off. A verifying operation for detecting whether or not the data written in the non-volatile memory is normal, the plurality of pieces of information corresponding to the data written in the non-volatile memory cell are provided in the verify operation. Held in the latch sense circuit of the
It is possible to narrow the threshold distribution width of the nonvolatile memory cell by switching the potential of the bit line by the voltage switching circuit and rewriting according to the data held in the sense circuit. Nonvolatile semiconductor memory device. 2. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. A first latch that is connected to the bit line through a first transfer gate and that latches a potential according to the data to be written to the nonvolatile memory cell and the data read from the nonvolatile memory A sense circuit, which is connected to the bit line and forcibly sets the bit line to a high-level potential according to data to be written to the nonvolatile memory cell at the time of verification, and sets the first latch sense circuit to a high level. A bypass circuit for holding a level potential and a memory cell connected to the bit line via a second transfer gate. A second latch sense circuit for latching a potential according to the data read from the second latch sense circuit, the first and second latch sense circuits being connected to the bit line through a third transfer gate And a voltage switching circuit for changing the potential of the bit line based on the potential latched in the non-volatile semiconductor memory device. 3. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. A nonvolatile semiconductor memory device that stores data depending on whether the threshold value range of the nonvolatile memory cell is a first range lower than a predetermined value or a second range higher than a predetermined value. A first transfer gate having one end of a current path connected to the bit line, and another end of the current path of the first transfer gate connected to a first inverter and a first clocked inverter in antiparallel. A first latch sense circuit configured to be connected to, and two transistors connected in series between the bit line and the high-level power supply voltage terminal, A bypass circuit for forcibly setting the bit line to the high level potential according to the data to be written to the non-volatile memory cell at the time of refining so that the first latch sense circuit holds the high level potential; A second transfer gate having one end of a current path connected to the bit line, and another end of the current path of the second transfer gate connected to a second inverter and a second clocked inverter in antiparallel. A second latch / sense circuit connected to the first transfer gate, a third transfer gate having one end of a current path connected to the bit line, and a third transfer gate connected to the third transfer gate. And a voltage switching circuit that changes the potential of the bit line based on the potential latched by the second latch sense circuit. The nonvolatile semiconductor memory device according to. 4. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. A potential holding circuit connected to the bit line for holding data to be written to and read from the non-volatile memory cell, and a threshold value range of the non-volatile memory cell is predetermined. In a nonvolatile semiconductor memory device that stores data depending on whether it is in a first range lower than a value or in a high second range, the potential holding circuit stores data read from the nonvolatile memory cell. And a plurality of latch sense circuits that hold data to be written in the nonvolatile memory cell and have a forced inversion function, and a plurality of latch sense circuits. A voltage switching circuit for switching the potential of the bit line based on the data held in the path suppresses an increase in write time and narrows the threshold distribution width of the nonvolatile memory cell. A non-volatile semiconductor memory device that enables 5. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. Connected to the bit line through a first transfer gate, latches data to be written to the nonvolatile memory cell and data read from the nonvolatile memory cell, and has a forced inversion function. One latch / sense circuit, which is connected to the bit line through a second transfer gate, and latches data to be written to the nonvolatile memory cell and data read from the nonvolatile memory cell, and , A second latch sense circuit having a forced inversion function, and a connection to the bit line via a third transfer gate. Is, the first and second on the basis of the data latched in the latch sense circuit, it nonvolatile semiconductor memory device according to claim and a voltage switching circuit for changing the potential of the bit line. 6. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. In a nonvolatile semiconductor memory device for storing data depending on whether the threshold value range of the nonvolatile memory cell is a first range lower than a predetermined value or a high second range. A first transfer gate having one end of a current path connected to the bit line, and the other end of the current path of the first transfer gate, and a first and a second inverter connected in antiparallel. A first latch sense circuit, which is connected between a terminal to which the first transfer gate of the first latch sense circuit is not connected and a first power supply voltage terminal. To forcibly invert the data latched by the first latch sense circuit when the threshold value of the nonvolatile memory cell is in the second range and higher than a predetermined value. A first forced inversion circuit, a second transfer gate having one end of a current path connected to the bit line, and a second transfer gate connected to the other end of the current path of the second transfer gate, A second latch / sense circuit in which the inverters are connected in anti-parallel, between a terminal to which the second transfer gate of the second latch / sense circuit is not connected and the first power supply voltage terminal. When the threshold value of the nonvolatile memory cell is in the second range and is higher than a predetermined value, the second latch sense circuit latches the data and Second inversion circuit for electrically inverting, a third transfer gate having one end of a current path connected to the bit line, and the other end of the current path of the third transfer gate, and And a voltage switching circuit for changing the potential of the bit line based on the potentials latched by the first and second latch sense circuits. 7. The nonvolatile memory cell according to claim 1, wherein the memory cell array constitutes a NAND memory cell in which current paths of the plurality of nonvolatile memory cells are connected in series. Semiconductor memory device. 8. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile memory cell has a floating gate, and electrons are injected into the floating gate by utilizing an FN tunnel current. . 9. The nonvolatile memory according to claim 1, wherein the voltage switching circuit switches the potential of the bit line in three ways based on the data latched by the plurality of sense latch circuits. Semiconductor memory device. 10. The voltage switching circuit includes a reference power supply voltage terminal, a first PMOS transistor having a source terminal connected to the reference power supply voltage terminal, and a gate terminal connected to the second latch means. Also,
A second PMOS transistor having a source terminal connected to the drain terminal of the first PMOS transistor; and a gate terminal connected to the second latch means, and
A first NMOS transistor having a source terminal connected to the drain terminal of the second PMOS transistor; a second NMOS transistor having a drain terminal connected to the source terminal of the first NMOS transistor; A ground terminal connected to the source terminal of the second NMOS transistor, a source terminal at the gate terminal of the first PMOS transistor and the other end of the first transfer gate, and a drain terminal at the drain of the second PMOS transistor. A gate terminal is connected to the other end of the terminal and the third transfer gate, and the gate terminal is connected to the gate terminal of the fourth NMOS transistor and the terminal of the first latch sense circuit to which the first transfer gate is not connected. Is composed of a third PMOS transistor Things nonvolatile semiconductor memory device according to claim 2, 3, 5, 6, wherein. 11. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. And a threshold voltage range of the non-volatile memory cell is a first range or a second range higher than the range, in a verification method of a non-volatile semiconductor memory device for storing data. A first write operation for selecting one of the plurality of non-volatile memory cells and writing data to the selected non-volatile memory cell, and being connected to the selected non-volatile memory cell A judgment voltage is applied to the word line, the data written in the selected nonvolatile memory cell is read out, and the threshold voltage of the nonvolatile memory cell is In order to determine whether it is in a range, or in the second range, which is equal to or higher than the determination voltage, or in the second range, which is lower than the determination voltage. Threshold voltage determination operation, by changing the potential of the bit line based on the determination of the threshold voltage in the threshold voltage determination operation,
A second write operation in which the write speed is adjusted when writing data to the selected nonvolatile memory cell, and a verify voltage is applied to the word line connected to the selected nonvolatile memory cell, A verifying method for a nonvolatile semiconductor memory device, comprising: a read operation for determining whether or not a threshold voltage of a nonvolatile memory cell is normal. 12. The method for verifying a non-volatile semiconductor device according to claim 11, wherein after the read operation is completed, the threshold voltage of the selected non-volatile memory cell is equal to or higher than a predetermined potential. 12. The method for verifying a non-volatile semiconductor device according to claim 11, wherein the second write operation and the read operation are repeated. 13. A memory cell array including a plurality of nonvolatile memory cells, a bit line connected to one end of a current path of the memory cell array, and a word line connected to a control gate of the nonvolatile memory cell. And a threshold voltage range of the non-volatile memory cell is a first range or a second range higher than the range, in a verification method of a non-volatile semiconductor memory device for storing data. A first write operation for selecting one of the plurality of non-volatile memory cells and writing data to the selected non-volatile memory cell, and being connected to the selected non-volatile memory cell A read operation for applying a verify voltage to the word line to determine whether the threshold voltage of the non-volatile memory cell is normal or abnormal; and the read operation. Then, when it is determined that the threshold voltage of the non-volatile memory cell is abnormal, a determination voltage is applied to the word line connected to the selected non-volatile memory cell, and the selected non-volatile The data written in the memory cell is read, and the threshold voltage of the nonvolatile memory cell is in the first range, or in the second range, which is equal to or higher than the determination voltage, or , A threshold voltage determination operation for determining whether it is in a range lower than the determination voltage in the second range, and in the determination operation, based on the determination of the threshold voltage,
A second write operation in which a write speed when writing data to the selected nonvolatile memory cell is adjusted by changing the potential of the bit line. Method. 14. The method for verifying a non-volatile semiconductor device according to claim 13, wherein the threshold voltage of the selected non-volatile memory cell becomes equal to or higher than a predetermined voltage after the read operation is completed. The threshold voltage determination operation, the write operation, and the read operation are repeated.
A method for verifying a nonvolatile semiconductor device according to claim 1. 15. The method of verifying a non-volatile semiconductor device according to claim 11, wherein the determination voltage is lower than the verify voltage.