JP2008130182A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of completing writing by a smaller number of processing times without reducing writing accuracy in the writing of a memory cell capable of storing binary or more data. <P>SOLUTION: A writing means 10 for repeatedly executing write processing carried out by applying a write gate voltage to a word line connected to a writing target cell while gradually increasing the write gate voltage is provided with a classification means 11 for classifying each of writing target cells into a plurality of memory cell groups according to a threshold voltage after first execution of write processing, and a reference writing gate voltage resetting means 12 for adding, in write processing immediately after the classification, a memory cell group increase amount set based on a difference between the lower limit value of the threshold value voltage distribution of a memory cell in a selective storage state and the upper limit threshold voltage of the memory cell group, to the reference writing gate voltage to reset it as a reference writing gate voltage for each memory cell group. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention includes a first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charges, and a second electrode that can be controlled by the amount of charges stored in the memory function unit The present invention relates to a nonvolatile semiconductor memory device including a memory cell array in which memory cells having two or more storage states defined by a conduction state therebetween are arranged in a matrix in the row and column directions.

  Conventionally, it has one or a plurality of memory function units capable of storing charges, and has two or more storage states defined by the conduction state between the source and drain that can be controlled by the amount of charges stored in the memory function units A stack type in which a control gate is stacked on a floating gate (floating gate) as the most common flash memory as a nonvolatile semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix in rows and columns. There is memory. As the stack type memory, for example, there is an ETOX (EPROM Thin Oxide, registered trademark of Intel Corporation) type flash memory.

  The stacked flash memory will be briefly described with reference to FIGS. Here, FIG. 2 is a schematic circuit diagram showing a configuration example of the memory cell array of the flash memory, and FIG. 11 is a cross-sectional view schematically showing the transistor structure of the memory cell of the stack type flash memory.

  As shown in FIG. 2, the memory cell array includes (n + 1) × (m + 1) memory cells. These memory cells are arranged in a matrix in the row and column directions, and the memory cells in the same row are arranged. The control gate (corresponding to the first electrode) is connected to the respective common word lines WL0 to WLn, and the sources (corresponding to one of the second electrodes) are connected between the two memory cells adjacent in the row direction. The drains (corresponding to one of the second electrodes) of the memory cells in the column are connected to the common bit lines BL0 to BLm, and the sources of the memory cells in the same column are connected to the common virtual ground line SL. ing.

  As shown in FIG. 11, the memory cell M1 constituting the memory cell array is a binary memory cell configured to have two memory states, a write state and an erase state, and a channel between the source 14 and the drain 16 A floating gate 13 (corresponding to a memory function part) serving as a charge storage region is formed on the region 15 via the tunnel oxide film 11, and a control gate 12 is further formed on the floating gate 13 via the interlayer insulating film 10. Has been. Incidentally, the threshold voltage of the memory cell in each storage state is not constant but has a predetermined distribution due to variations in transistor characteristics and the like. FIG. 12 shows the threshold voltage distribution of the memory cell when the memory cell array shown in FIG. 2 is composed of binary memory cells. In FIG. 12, the horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells in the memory cell array having the threshold voltage indicated by the horizontal axis. Specifically, as shown in FIG. 12, two partial threshold voltage distributions are formed corresponding to the write state and the erase state, and the partial threshold voltage distribution having a lower limit value of 4.5 V is the write state (program state). ) And the partial threshold voltage distribution having an upper limit value of 3 V represents the threshold voltage distribution of the memory cell in the erased state (erase state).

  The operation principle of the stack type flash memory cell will be briefly described. Here, a writing process for setting a memory cell in an erased state to a writing state, an erasing process for setting a memory cell in a writing state to an erasing state, and a reading process for reading the storage state of a reading target cell will be briefly described.

  In the writing process, for example, the voltage Vpp (for example, 9 V) is applied to the control gate 12 of the cell to be written in the memory cells constituting the memory cell array, the reference voltage Vss (for example, 0 V) is applied to the source 14, and the voltage Vdp (for example, to the drain 16). For example, a write voltage application process for applying 5V) is performed. As a result, in the cell to be written, a large amount of current flows in the channel region 15 between the source 14 and the drain 16, hot electrons are generated in the region where the electric field near the drain 16 becomes high, and electrons are injected into the floating gate 13. The threshold voltage increases. In general, after the write voltage application process, whether or not the threshold voltage of the memory cell has changed within the range of the desired threshold voltage distribution, that is, whether or not the write process has been completed normally. The verification process to be verified is executed. Specifically, in the verify process, a voltage Vgv (for example, 5 V) is applied to the control gate 12 of the write target cell, and a voltage Vdv (for example, 1 V) is applied to the drain 16, and the threshold voltage of the write target cell at this time is stored in the memory. The comparison is made with the threshold voltage of a reference cell having the same structure as the cell.

  The erasing process is performed, for example, by applying a voltage Vnn (for example, −9 V) to the control gate 12 of the memory cell to be erased and a voltage Vpe (for example, 6 V) to the source 14. Thereby, in the memory cell to be erased, electrons are extracted from the floating gate 13 in the vicinity of the source 14, and the threshold voltage is lowered.

  In the reading process, for example, the voltage Vgr (for example, 5 V) is applied to the control gate 12 of the reading target cell in the memory cell constituting the memory cell array, and the voltage Vdr (for example, 1 V) is applied to the drain 16 to flow through the reading target cell. This is done by detecting the current. Here, for example, when a voltage is applied under the above voltage condition, a memory cell in which a current of a predetermined amount or more flows is determined to be an erased state (erase state) memory cell with a low threshold voltage, and almost no current flows. It is determined that no memory cell is a memory cell in a write state (program state) with a high threshold voltage. More specifically, the threshold voltage of each memory cell in a memory cell array composed of binary memory cells belongs to one of the two threshold voltage distributions shown in FIG. Therefore, the memory state can be determined according to which of the threshold voltage distributions shown in FIG. 12 the threshold voltage of the memory cell obtained from the voltage flowing through the memory cell when a voltage is applied under the above voltage condition. When the threshold voltage is a memory cell belonging to the threshold voltage distribution with a low Data “1” shown in FIG. 12, it is determined that the memory cell is in the erased state. On the other hand, in the case of a memory cell belonging to a threshold voltage distribution having a high threshold voltage Data “0” shown in FIG.

  Although the flash memory using binary memory cells has been described above, multilevel storage of three or more values can also be realized in the stack type flash memory.

  Here, FIG. 4 shows an example of a threshold voltage distribution of a memory cell in a memory cell array using quaternary memory cells. Specifically, as shown in FIG. 4, four partial threshold voltage distributions are formed corresponding to the four storage states, and a 2-bit value is assigned to each partial threshold voltage distribution corresponding to each storage state. It has been. Data “11” is in the partial threshold voltage distribution in the range of 3V or less, and Data “10” is in the range of 4.7V to 5.2V in the partial threshold voltage distribution in the range of 3.7V to 4.2V. Data “01” is assigned to the partial threshold voltage distribution in FIG. 5 and Data “00” is assigned to the partial threshold voltage distribution in the range of 5.7 V or higher. A memory cell having a higher threshold voltage is in a state where more electrons are injected into the floating gate.

  A write process for the quaternary memory cell shown in FIG. 4 will be described with reference to FIG. Here, FIG. 13 is a flowchart showing a processing procedure of a conventional write process for a quaternary memory cell. In a multi-value memory cell having three or more values, in general, from a storage state with a low threshold voltage, a write voltage application process and a verify process are sequentially performed so as to shift to a storage state with a next higher threshold voltage. The write process is performed as needed to repeatedly execute the write process. The initial storage state of the memory cell is the erased state, and the threshold voltage is in the range of the threshold voltage distribution of Data “11” shown in FIG. Here, a case where the storage state defined by the write data is Data “00”, that is, a case where a write target cell in the erase state of Data “11” is written to the storage state of Data “00” will be described. .

  As shown in FIG. 13, when writing a write target cell in the erase state of Data “11” to the storage state of Data “00”, first, the write target cell in the erase state of Data “11” is set to Data “10”. Is written into the storage state (steps # 501 and # 502). Specifically, first, the write gate voltage Vg10 is applied to the word line connected to the write target cell, and after the voltage of the word line is stabilized, the amplitude Vdp (for example, 5 V) is applied to the bit line connected to the write target cell. ), A write voltage application process for applying a voltage pulse (write drain voltage) having a pulse width Wp (for example, 1 μsec) is performed (step # 501). Subsequently, the verify gate voltage Vgv is applied to the word line connected to the write target cell, and the verify drain voltage Vdv is applied to the bit line connected to the write target cell, thereby stabilizing the voltage of the word line and the bit line. Thereafter, a verify process is performed to read out the storage state of each write target cell and determine whether or not the data is in the storage state of Data “10” (step # 502). As a result of the verify process, for the write target cell determined that the threshold voltage does not reach the range of the threshold voltage distribution corresponding to Data “10” (NG branch in step # 502), the write gate voltage Vg10 is set. The write gate voltage Vg10 is reset by increasing ΔVg10, and the write process of step # 501 is performed again. In step # 502, the write voltage application processing in step # 501 and # 502 are performed until it is determined that the threshold voltages of all the write target cells are within the range of the threshold voltage distribution corresponding to the storage state of Data “10”. Repeat the verify process. Here, FIG. 14 is a waveform diagram showing, in time series, the write voltage applied to the word line and bit line of the write target cell in the write process and verify process shown in FIG. FIG. 14B shows the waveform of the write drain voltage applied to the bit line of the write target cell, and FIG. 14B shows the waveform of the write gate voltage applied to the word line of the write target cell. As shown in FIG. 14, the write gate voltage is set to increase by ΔVg for each write process, and the write drain voltage is set to the same value in all the write processes.

  After the threshold voltages of all the write target cells reach the range of the threshold voltage distribution corresponding to Data “10” (OK branch at step # 502), the write target cells in the storage state of Data “10” are displayed as Data. Write to the storage state of “01” (steps # 503 and # 504). Specifically, first, a write gate voltage Vg01 is applied to the word line connected to the write target cell, and after the word line voltage is stabilized, the pulse width Wp and amplitude Vdp are applied to the bit line connected to the write target cell. A write voltage application process for applying the voltage pulse is performed (step # 503). Subsequently, the verify gate voltage Vgv is applied to the word line connected to the write target cell, and the verify drain voltage Vdv is applied to the bit line connected to the write target cell, thereby stabilizing the voltage of the word line and the bit line. Thereafter, a verify process is performed to read out the storage state of each write target cell and determine whether or not it is in the storage state of Data “01” (step # 504). As a result of the verify process, for the write target cell determined that the threshold voltage does not reach the range of the threshold voltage distribution corresponding to Data “01” (NG branch in step # 504), the write gate voltage Vg01 is set. ΔVg01 is increased and reset as the write gate voltage Vg01, and the write process of step # 503 is performed again. In step # 504, the write voltage application process in step # 503 and # 504 are performed until it is determined that the threshold voltages of all the write target cells are within the range of the threshold voltage distribution corresponding to the storage state of Data “01”. Repeat the verify process.

  Subsequently, after the threshold voltages of all the write target cells reach the threshold voltage distribution range corresponding to Data “01” (OK branch in step # 504), the write target cell in the storage state of Data “01” Is written in the storage state of Data “00” (steps # 505 and # 506). Specifically, first, the write gate voltage Vg00 is applied to the word line connected to the write target cell, and after the word line voltage is stabilized, the pulse width Wp and amplitude Vdp are applied to the bit line connected to the write target cell. A write voltage application process for applying the voltage pulse is performed (step # 505). Subsequently, the verify gate voltage Vgv is applied to the word line connected to the write target cell, and the verify drain voltage Vdv is applied to the bit line connected to the write target cell, thereby stabilizing the voltage of the word line and the bit line. Thereafter, a verify process is performed to read out the storage state of each write target cell and determine whether or not the data is in the storage state of Data “00” (step # 506). As a result of the verify process, for the write target cell determined that the threshold voltage does not reach the range of the threshold voltage distribution corresponding to Data “00” (NG branch in step # 506), the write gate voltage Vg00 is set. ΔVg00 is increased and reset as the write gate voltage Vg00, and the write process of step # 505 is performed again. The write voltage application process in step # 505 and the verify process in # 506 are repeatedly executed. In step # 506, the threshold voltages of all write target cells are within the threshold voltage distribution range corresponding to the storage state of Data “00”. If it is determined that the writing process is present, the writing process is completed.

  Note that the write gate voltage Vg10 for writing the cell to be written to the storage state of Data “10”, the write gate voltage Vg01 for writing to the storage state of Data “01”, and the storage state of Data “00” The relationship of the write gate voltage Vg00 for writing to is Vg10 <voltage Vg01 <voltage Vg00. This is because the threshold voltage of the memory cell increases in accordance with the difference between the voltage applied to the control gate in the current write process and the voltage applied to the control gate in the previous write process, that is, the write gate applied to the control gate. This is because the threshold voltage of the memory cell increases by the amount of voltage increase. Specifically, for example, when the voltage Vgp is applied to the control gate of the memory cell and the threshold voltage of the memory cell after writing is Vt, the voltage applied to the control gate is increased by ΔVg for writing. As a result, the threshold voltage of the memory cell rises from Vt by ΔVg.

  As described above, in the conventional occasional writing process for the four-value memory cell, when writing from Data “11” to Data “00”, the writing process from Data “11” to Data “10”, from Data “10” The writing process to Data “01” and the writing process from Data “01” to Data “00” are performed in stages. Similarly, when writing from Data “11” to Data “01”, the writing process from Data “11” to Data “10” and the writing process from Data “10” to Data “01” are stepwise. When writing from Data “11” to Data “10”, only write processing to Data “10” is performed. For this reason, in the occasional write process, the time required to complete the write process increases as the number of storage states that pass from the initial storage state of the write target cell to the selected storage state defined by the write data increases. become longer. Therefore, in particular, when a memory cell in an erased state is written to a storage state having the highest threshold voltage, there is a problem that it takes a considerable time to complete the writing process.

  As a technique for shortening the time required for the memory cell write process, the pulse width of the write gate voltage applied to the word line connected to the write target cell is set according to the storage state defined by the write data. There is a nonvolatile semiconductor memory device that performs a writing process (see, for example, Patent Document 1).

JP 2000-149578 A

  In the conventional writing process, after the reference writing gate voltage is applied to the word line connected to the writing target cell and the writing process is executed, the reference writing gate voltage is applied to the writing target cell that has not been written. The writing process is repeated by gradually increasing in steps. If the write process is performed with a high reference write gate voltage, the memory cell may be excessively stressed and the reliability of the memory cell may be impaired. Therefore, the reference write gate voltage in the first write process is It can be said that it is desirable to set a certain level low. Further, in order to suppress variation in threshold voltage of the write target cell after completion of the write process due to variations in program characteristics and to tighten the threshold voltage distribution of the write target cell after completion of the write process, the second and subsequent write processes are performed. Therefore, it is necessary to set the amount of increase of the reference write gate voltage with respect to the reference write gate voltage in the previous write process more finely. However, if the reference write gate voltage is set to be low to some extent in the first write process, the difference between the threshold voltage of the write target cell in the first write process and the lower limit value of the threshold voltage in the selected storage state increases. Furthermore, if the increase amount of the reference write gate voltage in the second and subsequent write processes is set to be small, the increase in the threshold voltage of the write target cell is reduced. The number of write processes executed until the write process to the selected storage state for all the write target cells is completed is the difference between the threshold voltage of the write target cell in the first write process and the lower limit value of the threshold voltage of the selected storage state. , Which is proportional to the increased value of the threshold voltage of the write target cell. Therefore, the difference between the threshold voltage of the write target cell in the first write process and the lower limit value of the threshold voltage of the selected storage state is increased, and the increase in the threshold voltage of the write target cell is reduced, so that There has been a problem that the number of write processes executed until the write process to the selected storage state is considerably increased, and the time required to complete the write process is increased.

  In particular, in the case of a memory cell array composed of multi-valued memory cells, the threshold voltage distribution range corresponding to each storage state in order to secure a read margin as the number of storage states that the memory cell can take increases. In order to control the change of the threshold voltage during the writing process with higher accuracy, the increase amount of the writing gate voltage is set more finely, or the pulse width of the writing gate voltage is more It is necessary to take measures such as setting it narrowly. However, as described above, due to these measures, the number of executions of the writing process increases, and there is a problem that the time required for the completion of the writing process becomes longer.

  The present invention has been made in view of the above problems, and its object is to perform a write process in a smaller number of processes without degrading the write accuracy in a write process of a memory cell capable of storing binary or higher data. The present invention provides a nonvolatile semiconductor memory device capable of completing the above.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has one first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charges, and the memory function Memory cells having two or more storage states defined by the conduction state between the second electrodes, which can be controlled by the amount of charge accumulated in the portion, are arranged in a matrix in the row and column directions and are in the same row The first electrodes of the memory cells are respectively connected to a common word line, and one of the second electrodes of the memory cells in the same column is connected to a common bit line, and at least in the same column or the same row Applying a write gate voltage to a memory cell array in which the other second electrode of the memory cell is connected to a common ground line, and to the word line connected to a write target cell in the memory cell; Write processing for writing from the initial storage state to the selective storage state defined by the write data by applying a write drain voltage to the bit line connected to the target cell and increasing the threshold voltage of the write target cell A non-volatile semiconductor memory device comprising: a write unit that repeatedly executes the write gate voltage while increasing the write gate voltage stepwise, wherein the write unit performs the first write process using a reference write gate voltage. A classifying unit that classifies each of the write target cells into a plurality of memory cell groups according to the threshold voltage by comparing a threshold voltage of each of the write target cells with a preset classification threshold voltage after execution; For the writing process for each of the first memory cell groups after the classification of the memory cells by the classifying means. For each of the memory cell groups excluding the memory cell group having the maximum threshold voltage, a lower limit value of a threshold voltage distribution of the memory cell in the selected storage state and a threshold value of the write target cell included in the memory cell group Based on the difference in the threshold voltage for classification that sets the upper limit of the voltage, an increase amount for each memory cell group of the write gate voltage is set, and the increase amount for each memory cell group is added to the reference write gate voltage Reference write gate voltage resetting means for resetting the voltage as the reference write gate voltage for each of the memory cell groups, and the memory cells after the second time after the classification of the memory cells by the classification means In the write process for each group, for each memory cell group, the reference write for each memory cell group in the previous write process A first feature is that the write gate voltage is increased stepwise for each of the memory cell groups by adding a predetermined increase amount set in advance to the gate voltage.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the classification unit classifies each of the write target cells into two memory cell groups, and the classification threshold voltage is determined by the reference write gate voltage. A second feature is that the threshold voltage is set to the center of the predicted threshold voltage distribution of the write target cell after the first execution of the write process.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the classification means includes classification reference cells having threshold voltages corresponding to the classification threshold voltages.

  In the nonvolatile semiconductor memory device according to the first or second feature of the present invention, the classification unit has the same structure as the memory cell for determining whether or not the memory cell is in the selected storage state. The verification gate voltage applied to the first electrode of the determination reference cell is adjusted to control the amount of current of the determination reference cell, and the write operation is performed using the determination reference cell with the verification gate voltage adjusted. A fourth feature is that each target cell is classified into the memory cell group.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the classification unit has an intermediate memory state between the memory state of the write target cell and the selected memory state before the memory cell performs the write process. In this case, the determination is performed by adjusting the verification gate voltage applied to the first electrode of the determination reference cell in the intermediate storage state for determining whether or not the memory cell is in the intermediate storage state. A fifth feature is that each of the write target cells is classified into the memory cell group by using the determination reference cell in the intermediate storage state in which the current amount of the reference cell for control is controlled and the gate voltage for verification is adjusted. And

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has one first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charges, and the memory function Memory cells having two or more storage states defined by the conduction state between the second electrodes, which can be controlled by the amount of charge accumulated in the portion, are arranged in a matrix in the row and column directions and are in the same row The first electrodes of the memory cells are respectively connected to a common word line, and one of the second electrodes of the memory cells in the same column is connected to a common bit line, and at least in the same column or the same row Applying a write gate voltage to a memory cell array in which the other second electrode of the memory cell is connected to a common ground line, and to the word line connected to a write target cell in the memory cell; Write processing for writing from the initial storage state to the selective storage state defined by the write data by applying a write drain voltage to the bit line connected to the target cell and increasing the threshold voltage of the write target cell A non-volatile semiconductor memory device comprising: a write unit that repeatedly executes the write gate voltage while increasing the write gate voltage stepwise, wherein the write unit performs the first write process using a reference write gate voltage. A classifying unit that classifies each of the write target cells into a plurality of memory cell groups according to the threshold voltage by comparing a threshold voltage of each of the write target cells with a preset classification threshold voltage after execution; For the writing process for each of the first memory cell groups after the classification of the memory cells by the classifying means. For each memory cell group, the write drain voltage for each memory cell group is set such that the value of the write drain voltage increases as the threshold voltage of the classified write target cell decreases. A drain voltage resetting means for writing to reset each of the memory cells, and in the writing process for each memory cell group for the second and subsequent times after the classification of the memory cells by the classifying means, in the previous writing process, The programming gate voltage is increased stepwise by adding a preset specified increase amount to the reference writing gate voltage, and the word line connected to the writing target cell is increased stepwise. A gate voltage is applied to the bit line connected to the write target cell, and the memory cell group A sixth feature is that a write process is performed by applying the write drain voltage reset by the write drain voltage resetting means.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has one first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charges, and the memory function Memory cells having two or more storage states defined by the conduction state between the second electrodes, which can be controlled by the amount of charge accumulated in the portion, are arranged in a matrix in the row and column directions and are in the same row The first electrodes of the memory cells are respectively connected to a common word line, and one of the second electrodes of the memory cells in the same column is connected to a common bit line, and at least in the same column or the same row Applying a write gate voltage to a memory cell array in which the other second electrode of the memory cell is connected to a common ground line, and to the word line connected to a write target cell in the memory cell; Write processing for writing from the initial storage state to the selective storage state defined by the write data by applying a write drain voltage to the bit line connected to the target cell and increasing the threshold voltage of the write target cell A non-volatile semiconductor memory device comprising: a write unit that repeatedly executes the write gate voltage while increasing the write gate voltage stepwise, wherein the write unit performs the first write process using a reference write gate voltage. A classifying unit that classifies each of the write target cells into a plurality of memory cell groups according to the threshold voltage by comparing a threshold voltage of each of the write target cells with a preset classification threshold voltage after execution; For the writing process for each of the first memory cell groups after the classification of the memory cells by the classifying means. For each of the memory cell groups, the lower the threshold voltage of the classified write target cell, the longer the application time of the write voltage defined by the write gate voltage and the write drain voltage. Voltage pulse resetting means for resetting the application time of the write voltage for each memory cell group, and the memory cells after the second time after the classification of the memory cells by the classifying means. In the write processing for each group, the write gate voltage is increased stepwise by adding a predetermined increase amount set in advance to the reference write gate voltage in the previous write processing. The application time reset by the voltage pulse resetting means is applied to each of the word line and the bit line to be connected. A seventh feature is that a write process is performed by applying a voltage defining the write voltage.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the classification unit includes a characteristic storage unit that stores information on the classified memory cell group for each of the write target cells. It is characterized by.

  According to the nonvolatile semiconductor memory device of the first feature, after the first write process using the reference write gate voltage, the threshold voltage of each write target cell is compared with a preset threshold voltage for classification, Classification means for classifying each write target cell into a plurality of memory cell groups according to the threshold voltage, and writing processing is performed by setting a reference write gate voltage for each memory cell group, so according to the program characteristics of the write target cell Thus, the reference write gate voltage can be set. In particular, in the first write process after classification, the reference write gate voltage is set so that the memory cell group having a relatively slow write characteristic, which is considered to have a relatively large number of write operations, has a larger threshold voltage increase by memory cell group. By resetting the memory cell group, the memory cell group having slower write characteristics can reduce the number of times the write process is executed until the write process to the selected storage state is completed, and can reduce the time required to complete the write process. As a result, even if the specified increase amount of the gate voltage for writing is finely set for the writing accuracy, it is possible to suppress the increase in the number of executions of the writing process until the writing process to the selected storage state is completed as a whole. become.

  Similarly, in the nonvolatile semiconductor memory device having the sixth feature, the memory cell group having a relatively slow write characteristic, which is considered to have a relatively large number of writes, increases the threshold voltage increase amount by memory cell group. By resetting the write drain voltage in this manner, the number of executions of the write process until the write process to the selected storage state is completed can be reduced, and the time taken to complete the write process can be reduced. Similarly, in the nonvolatile semiconductor memory device having the seventh feature, the memory cell group having a relatively slow write characteristic, which is considered to have a relatively large number of writes, increases the increase in the threshold voltage for each memory cell group. By resetting the write voltage, it is possible to reduce the number of times the write process is executed until the write process to the selected storage state is completed, and to reduce the time required to complete the write process.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
1st Embodiment of this invention apparatus is described based on FIGS.

  First, the configuration of the device of the present invention will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a schematic block diagram showing a schematic configuration of the device of the present invention.

  As shown in FIG. 1, the device 1 of the present invention includes a memory cell array 20, a bit line voltage supply circuit 30 for supplying a drain voltage to the bit lines of the memory cell array 20, and a word line for supplying a gate voltage to the word lines of the memory cell array 20. The voltage supply circuit 40 compares the read voltage read from the selected bit line of the memory cell array 20 with the reference voltage read from the bit line of the reference cell, and selects a plurality of selected memory cells in the memory cell array 20 Sense amplifier circuit 50 composed of a plurality of sense amplifiers for verifying the storage state of the memory, generating a write voltage for generating a write gate voltage applied to a word line and a write drain voltage applied to a bit line during a write process In the circuit 60, during the verify process, the verify gate voltage and the bias voltage applied to the word line are A read voltage generation circuit 70 for generating a verify drain voltage to be applied to the first line, a bit line voltage supply circuit 30, a word line voltage supply circuit 40, a sense amplifier circuit 50, a write voltage generation circuit 60, and a read voltage generation circuit. 70 is configured to include a control circuit 10 that performs a write process, a read process, an erase process, and the like. In FIG. 1, input circuits such as a plurality of address input signals (ADD in the figure), a plurality of data input signals (DI in the figure), a plurality of control signals (CTRL in the figure), and a plurality of data output signals (in the figure). Details of peripheral circuits such as an output circuit such as DO) and a decoder circuit for an address input signal are the same as those of a known non-volatile semiconductor memory device such as a flash memory, and the description thereof is omitted.

  Here, FIG. 2 shows a schematic configuration of the memory cell array 20. As shown in FIG. 2, the memory cell array 20 has one or a plurality of floating gates (memory function units) capable of storing charges, and can be controlled between the source and the drain which can be controlled by the amount of charges stored in the floating gates. (N + 1) × (m + 1) memory cells having two or more storage states defined by the conductive state are provided. Furthermore, the memory cell array 20 arranges these memory cells in a matrix in the row and column directions, and connects the control gates (corresponding to the first electrode) of the memory cells in the same row to the common word lines WL0 to WLn. The source (corresponding to one of the second electrodes) is connected between two memory cells adjacent in the row direction, and the drain (corresponding to one of the second electrodes) of the memory cells in the same column is shared. The bit lines BL0 to BLm are connected, and the sources of all the memory cells in the memory cell array 20 are connected to a common ground line SL. Further, although not shown, the memory cell array 20 includes a reference cell having the same structure as the memory cell used for determining the storage state of the memory cell. The configuration of the memory cell array 20 and the memory cells constituting the memory cell array 20 are the same as the configuration of the memory cell array provided in the conventional nonvolatile semiconductor memory device.

  The control circuit 10 receives a write signal from the outside (a write instruction by a control signal input or a command input by a data input signal), and applies a write gate voltage to a word line connected to a write target cell among the memory cells. Write processing to write from the initial storage state to the selective storage state defined by the write data by applying a drain voltage for writing to the bit line connected to the write target cell and increasing the threshold voltage of the write target cell Is functioned as a writing means for repeatedly executing the writing gate voltage stepwise. Further, as shown in FIG. 1, the control circuit 10 of the present embodiment compares the threshold voltage of each write target cell with a preset classification threshold voltage after performing the first write process using the reference write gate voltage. Thus, in the classification unit 11 that classifies each write target cell into a plurality of memory cell groups according to the threshold voltage, and in the writing process for each of the first memory cell groups after the classification of the memory cells by the classification unit 11, the threshold voltage For each memory cell group excluding the memory cell group with the largest value, the threshold voltage for classification that sets the lower limit value of the threshold voltage distribution of the memory cell in the selected storage state and the upper limit value of the threshold voltage of the write target cell included in the memory cell group Based on the difference, the amount of increase in the write gate voltage for each memory cell group is set, and the amount of increase in the memory cell group is added to the reference write gate voltage. A reference write gate voltage resetting means 12 for resetting the voltage as a reference write gate voltage for each memory cell group, and for each memory cell group after the second time after the classification of the memory cells by the classification means 11 For each memory cell group, the write gate voltage is set stepwise for each memory cell group by adding a predetermined increase in advance to the reference write gate voltage for each memory cell group in the previous write process. The control to increase is performed.

  The classification means 11 of the present embodiment is configured to include classification reference cells having threshold voltages corresponding to the classification threshold voltages. Further, the classification unit 11 of the present embodiment includes a characteristic storage unit 11a that stores information of the classified memory cell group for each write target cell.

  Hereinafter, the writing process by the control circuit 10 of the device 1 of the present invention will be described with reference to FIG. Here, FIG. 3 is a flowchart showing the processing procedure of the writing process of the device 1 of the present invention in the present embodiment.

  In the present embodiment, description will be made on the assumption that a write process is performed on a quaternary memory cell. Here, FIG. 4 is a graph showing an example of the threshold voltage distribution of a quaternary (2-bit) memory cell. As shown in FIG. 4, the memory cells are stored in order from the lowest threshold voltage range. Data “11” (for example, a threshold voltage range of 3.0 V or less), Data “10” (for example, a threshold voltage range of 3.7 V or more and 4.2 V or less), Data “01” (for example, 4.7 V or more and 5.2 V) The following threshold voltage range) is associated with Data “00” (for example, a threshold voltage range of 5.7 V or higher). In the present embodiment, the initial state of the memory cell is the erase state of Data “11” shown in FIG. 4, and the selected storage state defined by the write data is Data “00”, that is, the write target The case where the cell is written from the erase state of Data “11” to the program state of Data “00” will be described. Furthermore, in the present embodiment, when there is an intermediate storage state between the selected storage state defined by the write data and the initial storage state, writing is performed step by step from a storage state having a low threshold voltage to a storage state having a high threshold voltage. Write processing is performed as needed. Specifically, first, a write process is performed to set Data “10” to the write target cell in the erase state of Data “11” as the selective storage state. Then, after writing to Data “10” is completed, a write process is performed to set Data “10” as an initial state and Data “01” as a selective storage state for a write target cell in the program state of Data “10”. After the writing to “01” is completed, a writing process is performed to set Data “01” as an initial state and Data “00” as a selective storage state with respect to a write target cell in the program state of Data “01”.

  First, the control circuit 10 performs a write process for setting Data “10” to the write target cell in the erase state of Data “11” to be in a selective storage state (steps # 101 to # 105).

  Specifically, the control circuit 10 applies the reference write gate voltage to the word line connected to the write target cell, applies the write drain voltage to the bit line connected to the write target cell, and sets the write target cell to Data. A voltage application process for writing from “11” to Data “10” is performed (step # 101).

  Subsequently, the control circuit 10 compares the threshold voltage of each of the write target cells with the classification threshold voltage of the classification reference cell by the classification unit 11 after performing the first writing process with the reference writing gate voltage in Step # 101. Then, each cell to be written is classified into a plurality of memory cell groups according to the threshold voltage (step # 102). In the present embodiment, the classifying unit 11 classifies each write target cell into two memory cell groups. In this embodiment, the classification threshold voltage of the classification reference cell is set to the central threshold voltage of the predicted threshold voltage distribution of the write target cell after the first execution of the write process using the reference write gate voltage. . Here, FIG. 5 shows the predicted threshold voltage distribution D1 of the write target cell after the first execution of the write process using the reference write gate voltage, and the threshold voltage distribution of the write target cell after the completion of the write process to Data “10”. D2 is shown respectively. The classifying unit 11 classifies each write target cell with a write target cell having a threshold voltage lower than the classification threshold voltage of the classification reference cell Rc into the memory cell group Ms with slow write characteristics. A write target cell having a threshold voltage higher than the threshold voltage is classified into a memory cell group Mf having a fast write characteristic. Here, for the memory cell group Mf, among the write target cells classified into the memory cell group Mf, the write target cell written in Data “10” is excluded. Further, the classification unit 11 of the present embodiment stores the information of the classified memory cell group in the characteristic storage unit 11a for each write target cell.

  Subsequently, the control circuit 10 uses the reference write gate voltage resetting means 12 to perform the memory processing except for the memory cell group having the maximum threshold voltage in the writing process for each of the first memory cell groups after the classification by the classification means 11. For each cell group, based on the difference between the lower limit value of the threshold voltage distribution of the memory cell in the selected memory state and the threshold voltage for classification that sets the upper limit of the threshold voltage of the write target cell included in the memory cell group, the write gate A voltage increase amount for each memory cell group is set, and a voltage obtained by adding the increase amount for each memory cell group to the reference write gate voltage is reset as a reference write gate voltage for each memory cell group (step # 103). Here, the increase amount by memory cell group is calculated for the memory cell group Ms with slow write characteristics except for the memory cell group Mf with fast write characteristics. Here, the increase amount for each memory cell group with respect to the memory cell group Ms is determined by performing the writing process for setting Data “10” in the selected storage state in FIGS. 4 and 5, so that the reference cell Ra for determination of Data “10” is determined. The threshold voltage ΔVthslow is defined as the difference between the threshold voltage and the classification threshold voltage of the classification reference cell Rc.

  Subsequently, as shown in FIG. 3, the control circuit 10 performs a write process on the memory cell group Ms using the voltage reset by the reference write gate voltage resetting means 12 (step # 104). Here, FIG. 6 is a waveform diagram showing a schematic waveform of the write voltage applied to the write target cell, and FIG. 6A shows the waveform of the write gate voltage applied to the word line of the write target cell. FIG. 6B shows the waveform of the write drain voltage applied to the bit line of the write target cell. Incidentally, the corresponding step numbers in FIG. 3 are described below each voltage waveform. In the first write process after the memory cell classification by the classifying unit 11, in this embodiment, the word line connected to the write target cell classified into the memory cell group Ms is increased to the reference write gate voltage Vg1 for each memory cell group. The reference write gate voltage Vgs1 to which the amount ΔVthslow is added is applied, and the write drain voltage Vd is applied to the bit lines connected to the write target cells classified into the memory cell group Ms. Further, the control circuit 10 compares the threshold voltage of each write target cell with the threshold voltage of the determination reference cell Ra shown in FIG. 5 to determine whether or not the write target cell is in the storage state of Data “10”. A verify process is performed (step # 105). The control circuit 10 excludes the write target cell determined to have a threshold voltage higher than the threshold voltage of the determination reference cell Ra in the verify process from the write target in the write process to Data “10”. The control circuit 10 performs a write process to Data “10” again on the write target cell determined to have a threshold voltage lower than the threshold voltage of the determination reference cell Ra (NG branch at step # 105).

  The control circuit 10 performs, in the previous write process (step # 104), for each memory cell group for the write target cell that has been determined that the write to Data “10” has not been completed in the verify process in step # 105. By adding a predetermined increase amount set in advance to the reference write gate voltage for each memory cell group, the write gate voltage is increased step by step for each memory cell group (step # 103). Then, the control circuit 10 performs a voltage application process for each memory cell group using the write gate voltage increased stepwise (step # 104). Specifically, as shown in FIG. 6, the previous memory cell group Ms is connected to the word line connected to the write target cell classified into the memory cell group Ms based on the information stored in the characteristic storage unit 11a. A write gate voltage Vgs2 obtained by adding a specified increase amount ΔVg to the reference write gate voltage Vgs1 used in the write process is applied, and a write drain voltage Vd is applied to the bit line. Further, based on the information stored in the characteristic storage unit 11a, the reference write gate used in the previous write process for the memory cell group Mf is connected to the word line connected to the write target cell classified into the memory cell group Mf. A write gate voltage Vg2 obtained by adding a specified increase amount ΔVg to the voltage Vg1 is applied, and a write drain voltage Vd is applied to the bit line. Subsequently, the control circuit 10 compares the threshold voltage of each write target cell with the threshold voltage of the determination reference cell Ra shown in FIG. 5, and determines whether or not the write target cell is in the storage state of Data “10”. A verify process is performed (step # 105).

  The control circuit 10 performs the write gate voltage for each memory cell group every time the write process is executed until it is determined in the verify process of step # 105 that all write target cells are in the data “10” storage state. Steps # 103 to # 105 are repeatedly executed while increasing the value by increments ΔVg.

  If it is determined in the verify process in step # 105 that all the write target cells are in the data “10” storage state (OK branch in step # 105), the control circuit 10 is the same as steps # 103 to # 105. In this procedure, write processing is executed for all write target cells in the storage state of Data “10”, with Data “10” being the initial state and Data “01” being the selective storage state (steps # 106 to ##). 108). In this embodiment, the setting of the gate voltage for writing in the writing process in which Data “01” is selected and stored is based on the classification of the memory cell group by the classification unit 11 stored in the characteristic storage unit 11a in step # 102. To do.

  Further, when it is determined in the verify process in step # 108 that all the write target cells are in the data “01” storage state (OK branch in step # 108), the control circuit 10 performs steps # 106 to # 108. In the same manner as described above, a write process is executed for all write target cells in the storage state of Data “01”, with Data “01” being the initial state and Data “00” being the selective storage state (step # 109). ~ # 111).

  As described above, the inventive device 1 of the present embodiment sets the write gate voltage using the memory cell group increase amount ΔVthslow for the write target cells classified into the memory cell group Ms and having the slow write characteristics. In the write processing for each first memory cell group after the memory cell classification by the classifying unit 11, the amount of increase in the threshold voltage of the write target cell in the memory cell group with slow write characteristics can be increased. As a result, the number of executions of the write process until the completion of the write process can be reduced for the write target cells with slow write characteristics classified into the memory cell group Ms considered to have a large number of write processes executed until the completion of the write process. This makes it possible to reduce the processing time of the entire writing process.

  More specifically, in the device 1 of the present invention, the pulse width of the reference write gate voltage is P [μs], the time required for one verify process is V [μs], and the voltage pulse of the reference write gate voltage is applied. When the number of times is N [times], the time required for the write voltage application process and the verify process is (P + V) × N [μs] in the prior art, but in the case of the device 1 of the present invention, (nP + V) × N / n (n is the number of memory cell groups to be classified). Therefore, for example, the pulse width of the reference write gate voltage is 2 [μs], the time required for one verify process is 1 [μs], the number of application times of the voltage pulse of the reference write gate voltage is 30 [times], and the memory When the number of cell groups is 2, the time required for the write voltage application process and the verify process is 90 [μs] in the conventional technique, but 75 [μs] in the device 1 of the present invention, and the write time is reduced by 84%. it can.

Second Embodiment
A second embodiment of the device of the present invention will be described with reference to FIGS. In the present embodiment, the case where the configuration of the classification means of the device of the present invention is different from that of the first embodiment will be described. In the first embodiment, the dedicated reference cell for classification is provided in order to classify the write target cell into the memory cell group. However, in the present embodiment, the memory cell array 20 corresponds to the selective storage state provided in advance. The cell to be written is classified using the reference cell for determination.

  The classification means 11 of the present embodiment adjusts the verification gate voltage applied to the control gate of the determination reference cell having the same structure as the memory cell for determining whether or not the memory cell is in the selected storage state. Each of the write target cells is classified into a memory cell group using a determination reference cell to which the adjusted reference gate voltage is applied by controlling the current amount of the reference cell for use. Specifically, for example, in FIG. 4, when performing a write process in which the data “10” is in the selective storage state for the write target cell in the data “11” erase state, the threshold value of the storage state of Data “10” A classification gate voltage higher than the verification gate voltage is applied to the control gate of the determination reference cell that defines the lower limit of the voltage distribution. For example, in FIG. 5, the value of the classification gate voltage is set in advance so that the current amount of the determination reference cell Ra when the classification gate voltage is applied to the control gate becomes a current amount corresponding to the threshold voltage for classification. Set to an experimentally determined value.

<Third Embodiment>
3rd Embodiment of this invention apparatus is described based on FIG.1 and FIG.4. In the present embodiment, a case where the configuration of the classification means of the apparatus of the present invention is different from those in the first and second embodiments will be described. In the first embodiment, a dedicated classification reference cell is provided to classify the write target cell into the memory cell group. In the second embodiment, the control gate of the determination reference cell corresponding to the selected storage state is provided. Although the verifying gate voltage to be applied is adjusted and used as the reference cell for classification, in the present embodiment, other determination cells different from the reference cell for determination corresponding to the selected storage state provided in advance in the memory cell array 20 are used. The reference cell is used to classify the write target cell.

  The classification unit 11 of the present embodiment determines whether or not the memory cell is in the intermediate storage state when the memory cell has an intermediate storage state between the storage state and the selective storage state of the write target cell before the execution of the write process. The intermediate storage state in which the gate voltage for verification applied to the control gate of the reference cell for determining the intermediate storage state is determined to control the current amount of the reference cell for determination, and the adjusted gate voltage for verification is applied Each of the write target cells is classified into a memory cell group using the determination reference cells. Specifically, for example, in FIG. 4, when performing a write process in which the data “01” is selected and stored in the erase target cell of Data “11”, the erase state of Data “11” and the Data Between the selected storage state of “01”, there is an intermediate storage state of Data “10”. Here, the reference cell A for determination of Data “10” in which the classification gate voltage obtained by adjusting the verification gate voltage is applied to the control gate is used as the classification reference cell. Then, the value of the classification gate voltage is experimentally obtained in advance so that the current amount of the reference cell A for determination when the classification gate voltage is applied to the control gate becomes the current amount corresponding to the threshold voltage for classification. Set the value to The classification gate voltage may be the same value as the verification gate voltage.

<Fourth embodiment>
A fourth embodiment of the device of the present invention will be described with reference to FIGS. 3, 7, and 8. FIG. In the present embodiment, the waveform of the write voltage defined by the write gate voltage and the write drain voltage generated by the write means (control circuit 10) of the device of the present invention is different from the first to third embodiments. A case where the values are different will be described. Specifically, in the first to third embodiments, the write processing is performed by adjusting the voltage value of the write gate voltage for each memory cell group. However, in this embodiment, the write drain voltage for each memory cell group is adjusted. Write processing is performed by adjusting the voltage value.

  The configuration of the device of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 7 is a schematic block diagram showing a schematic configuration of the device of the present invention in the present embodiment. The configuration of the memory cell array 20, the bit line voltage supply circuit 30, the word line voltage supply circuit 40, the sense amplifier circuit 50, the write voltage generation circuit 60, and the read voltage generation circuit 70 of the device 1 of the present invention is the first to the above. This is the same as each configuration of the inventive device 1 in the third embodiment.

  As shown in FIG. 7, the control circuit 10 of the device 1 of the present invention includes a classification unit 11 having the same configuration as the classification unit of any of the first to third embodiments, and a memory cell after the classification by the classification unit 11 In the first writing process for each memory cell group, for each memory cell group, the writing for each memory cell group is performed so that the value of the drain voltage for writing becomes larger as the threshold voltage of the classified writing target cell becomes lower. A drain voltage resetting means 13 for resetting the drain voltage for resetting, and in the writing process for each memory cell group after the memory cell classification by the classifying means 11, the reference in the previous writing process By adding a predetermined increase amount set in advance to the write gate voltage, the write gate voltage is increased stepwise to connect to the write target cell. The write gate voltage increased stepwise is applied to the word line to be written, and the write drain voltage reset by the write drain voltage resetting means 13 for each memory cell group is applied to the bit line connected to the write target cell. A writing process is performed by applying a voltage.

  Hereinafter, the writing process by the control circuit 10 of the device 1 of the present embodiment of the present embodiment will be described with reference to FIGS.

  As shown in FIG. 3, the control circuit 10 according to the present embodiment first executes a write process (step # 101) using the reference write gate voltage, and then continues to any one of the first to third embodiments. The classifying unit 11 classifies the write target cell into two memory cell groups (step # 102).

  Subsequently, the control circuit 10 according to the present embodiment uses the write drain voltage resetting means 13 to write the memory cell group in the first write process (step # 103) for each memory cell group after the classification by the classification means 11. Each time, the write drain voltage for each memory cell group is reset so that the value of the write drain voltage increases as the threshold voltage of the classified write target cell becomes lower. Subsequently, as shown in FIG. 3, the control circuit 10 of the present embodiment performs a write process for each memory cell group using the voltage reset by the write drain voltage resetting means 13 (step # 104). .

  Here, FIG. 8 is a waveform diagram showing a schematic waveform of the write voltage applied to the write target cell, and FIG. 8A shows the waveform of the write gate voltage applied to the word line of the write target cell. FIG. 8B shows the waveform of the write drain voltage applied to the bit line of the write target cell. Incidentally, the corresponding step numbers in FIG. 3 are described below each voltage waveform. More specifically, for the memory cell group Ms with slow write characteristics shown in FIG. 5, the threshold voltage of the write target cell in the write process for each of the first memory cell group after the memory cell classification by the classifying unit 11 is set. The write drain voltage Vds higher than the normal write drain voltage is set as the write drain voltage for each memory cell group so that the increase amount increases. In this embodiment, the value of the write drain voltage Vds is equal to the difference between the threshold voltage of the memory cell group Ms and the lower limit value of the threshold voltage distribution of the selected memory state, as the amount of increase in the threshold voltage of the memory cell group Ms. As such, it is set to a value obtained experimentally in advance. For the memory cell group Mf with fast write characteristics shown in FIG. 5, in order to maintain the writing accuracy, the write drain voltage of the same value as the normal write drain voltage is used as the write drain voltage for each memory cell group. Set Vdf.

  Furthermore, the control circuit 10 of the present embodiment uses the reference write gate voltage in the previous write process in the write process for each memory cell group after the memory cell classification by the classifying unit 11 (step # 103). By adding a predetermined increase amount ΔVg set in advance, the write gate voltage is increased stepwise from Vg0 to Vgn. Then, the control circuit 10 of the present embodiment applies the write gate voltage Vg which is increased stepwise to the word line connected to the write target cell, and based on the information stored in the characteristic storage unit 11a. The write drain voltage Vdf is applied to the bit line connected to the write target cell classified into the memory cell group Mf, and the write drain voltage Vds is applied to the bit line connected to the write target cell classified into the memory cell group Ms. Write process.

  Subsequently, the control circuit 10 compares the threshold voltage of each write target cell with the threshold voltage of the determination reference cell Ra shown in FIG. 5, and determines whether or not the write target cell is in the storage state of Data “10”. A verify process is performed (step # 105). Further, the control circuit 10 performs writing for each memory cell group every time the write process is executed until it is determined in the verify process in step # 105 that all write target cells are in the data “10” storage state. Steps # 103 to # 105 are repeatedly executed while increasing the gate voltage by the specified increase amount ΔVg. Further, the control circuit 10 executes a write process for setting Data “01” as the selective storage state for all write target cells in the storage state of Data “10” in the same procedure as steps # 103 to # 105. (Steps # 106 to # 108). In the verify process in step # 108, if it is determined that all write target cells are in the data “01” storage state (OK branch in step # 108), the same procedure as steps # 106 to # 108 is performed. Write processing for selecting Data “00” as the selective storage state is executed for all write target cells in the storage state of “01” (steps # 109 to # 111).

  As described above, the inventive device 1 of the present embodiment increases the threshold voltage of the write target cell in the memory cell group having a slower write characteristic in the write process for each of the first memory cell group after the memory cell is classified by the classifying unit 11. Since the value of the drain voltage for writing for each memory cell group is set so as to increase, the memory cell having a slower writing characteristic can reduce the number of times the writing process is executed until the writing process is completed. Thus, the processing time for the entire writing process can be shortened.

<Fifth Embodiment>
A fifth embodiment of the device of the present invention will be described with reference to FIGS. 3, 9, and 10. FIG. In the present embodiment, the waveform of the write voltage defined by the write gate voltage and the write drain voltage generated by the write means (control circuit 10) of the device of the present invention is different from the first to fourth embodiments. A case where the values are different will be described. Specifically, in the first to third embodiments, the writing process is performed by adjusting the voltage value of the writing gate voltage, and in the fourth embodiment, the writing process is performed by adjusting the voltage value of the writing drain voltage. In this embodiment, the writing process is performed by adjusting the application time of the writing voltage.

  The configuration of the device of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 9 is a schematic block diagram showing a schematic configuration of the device of the present invention in the present embodiment. The configuration of the memory cell array 20, the bit line voltage supply circuit 30, the word line voltage supply circuit 40, the sense amplifier circuit 50, the write voltage generation circuit 60, and the read voltage generation circuit 70 of the device 1 of the present invention is the first to the above. This is the same as each configuration of the device 1 of the present invention in the fourth embodiment.

  As shown in FIG. 9, the control circuit 10 of the device 1 of the present invention includes a classification unit 11 having the same configuration as that of any of the classification units of the first to third embodiments, and a memory cell after the classification by the classification unit 11. In the first writing process for each memory cell group, for each memory cell group, the lower the threshold voltage of the classified target cell, the lower the threshold voltage of the writing voltage specified by the writing gate voltage and the writing drain voltage. Voltage pulse resetting means 14 for resetting the application time of the write voltage for each memory cell group so that the application time becomes longer, and the second and subsequent memories after the classification of the memory cells by the classification means 11 In the write process for each cell group, a predetermined increase amount set in advance is added to the reference write gate voltage in the previous write process. The voltage is increased stepwise, and a write process is performed by applying a voltage defining a write voltage to the word line and the bit line connected to the write target cell with the application time reset by the voltage pulse resetting means 14. Configured to do. Here, the write voltage indicates a state in which the write gate voltage and the write drain voltage are simultaneously applied to the write target cell, and the application time of the write voltage is the same as the write gate voltage to the write target cell. It is defined by the time during which the write drain voltage is applied simultaneously.

  Hereinafter, the writing process by the control circuit 10 of the device 1 of the present embodiment of the present embodiment will be described with reference to FIGS.

  As shown in FIG. 3, the control circuit 10 according to the present embodiment first executes a write process (step # 101) using the reference write gate voltage, and then continues to any one of the first to third embodiments. The classifying unit 11 classifies the write target cell into two memory cell groups (step # 102).

  Subsequently, the control circuit 10 of the present embodiment uses the voltage pulse resetting unit 14 for each memory cell group in the writing process (step # 103) for each first memory cell group after the memory cell classification by the classifying unit 11. Then, the application time of the write voltage for each memory cell group is reset so that the application time of the write voltage becomes longer in the memory cell group in which the threshold voltage of the classified write target cell is lower. Subsequently, the control circuit 10 of the present embodiment performs a write process for each memory cell group using the write voltage reset by the voltage pulse resetting means 14 (step # 104).

  Here, FIG. 10 is a waveform diagram showing a schematic waveform of the write voltage applied to the write target cell, and FIG. 10A shows the waveform of the write gate voltage applied to the word line of the write target cell. FIG. 10B shows the waveform of the write drain voltage applied to the bit line of the write target cell. Incidentally, the corresponding step numbers in FIG. 3 are described below each voltage waveform. More specifically, for the memory cell group Ms with slow write characteristics shown in FIG. 5, the threshold voltage of the write target cell in the write process for each of the first memory cell group after the memory cell classification by the classifying unit 11 is set. The write drain voltage Vds having a long pulse width is set as the write drain voltage for each memory cell group so that the increase amount increases. The memory cell group Mf having fast write characteristics shown in FIG. 5 has a pulse width shorter than the pulse width of the write drain voltage Vds as the write drain voltage for each memory cell group in order to maintain the write accuracy. A write drain voltage Vdf is set. In this embodiment, the pulse widths of the write drain voltage Vds and the write drain voltage Vdf are determined by the increase in the threshold voltage of the memory cell group Ms by the memory cell group, the threshold voltage for classification, and the threshold voltage in the selected storage state. A value obtained experimentally in advance is set so as to be the difference between the lower limit values of the distribution.

  Furthermore, the control circuit 10 of the present embodiment uses the reference write gate voltage in the previous write process in the write process for each memory cell group after the memory cell classification by the classifying unit 11 (step # 103). By adding a predetermined increase amount ΔVg set in advance, the write gate voltage is increased stepwise from Vg0 to Vgn. Then, the control circuit 10 of the present embodiment applies the write gate voltage Vg which is increased stepwise to the word line connected to the write target cell, and based on the information stored in the characteristic storage unit 11a. The write drain voltage Vdf is applied to the bit line connected to the write target cell classified into the memory cell group Mf, and the write drain voltage Vds is applied to the bit line connected to the write target cell classified into the memory cell group Ms. Write process.

  In this embodiment, the application time of the write voltage is adjusted by adjusting the pulse width of the write drain voltage for each memory cell group. However, the present invention is not limited to this, and the write gate voltage is set for each memory cell group. The write voltage application time may be adjusted by adjusting the pulse width of the write gate, or the write gate voltage and the write drain voltage may be applied simultaneously by controlling the application timing of the write gate voltage and the write drain voltage. The application time of the voltage for writing may be adjusted by adjusting the time to be written.

  As described above, the inventive device 1 of the present embodiment increases the threshold voltage of the write target cell in the memory cell group having a slower write characteristic in the write process for each of the first memory cell group after the memory cell is classified by the classifying unit 11. Since the application time of the write voltage for each memory cell group is set to be long so that the amount increases, it is possible to reduce the number of times the write process is executed until the write process is completed as the memory cell has a slower write characteristic. Thus, the processing time for the entire writing process can be shortened.

<Another embodiment>
<1> In each of the above embodiments, the write target cell is classified into two memory cell groups. However, the present invention is not limited to this, and variations in the characteristics of the write target cell and the threshold voltage after the first write processing of the write target cell It may be classified into three or more memory cell groups in consideration of the threshold voltage range of the selected storage state defined by the distribution and write data.

  <2> In each of the above embodiments, the memory cell array 20 shown in FIG. 2 connects one second electrode (drain) of memory cells in the same column to a common bit line, and the other of all memory cells. Although the case where two electrodes (sources) are connected to a common ground line has been described, the structure of the memory cell array provided in the device 1 of the present invention is not limited to this. For example, the other second electrode (source) of the memory cell may be connected to a different ground line for each column or row. Further, the memory cell array 20 shown in FIG. 2 is configured so that one second electrode (drain) of memory cells adjacent in the row direction is connected to each other, but is connected to a different bit line for each row. You may do it. In each of the above embodiments, the case where a memory cell array using quaternary memory cells is provided has been described. However, the present invention is not limited to this, and other multi-valued memories such as binary memory cells are used. The present invention apparatus 1 can also be applied to a case where a memory cell array using cells is provided.

1 is a schematic block diagram showing a main configuration in a first embodiment of a nonvolatile semiconductor memory device according to the present invention. Schematic circuit diagram showing a configuration example of a memory cell array of a nonvolatile semiconductor memory device 7 is a flowchart showing a processing procedure of write processing in the first embodiment of the nonvolatile semiconductor memory device according to the present invention. The graph which shows the example of the threshold voltage distribution of a quaternary memory cell A graph showing the predicted threshold voltage distribution of the write target cell after the first write process by the reference write gate voltage and the threshold voltage distribution of the write target cell after the write process is completed FIG. 4 is a waveform diagram showing a schematic waveform of a write voltage applied to a write target cell in the first embodiment of the nonvolatile semiconductor memory device according to the present invention. The schematic block diagram which shows the main structures in 4th Embodiment of the non-volatile semiconductor memory device which concerns on this invention A waveform diagram showing a schematic waveform of a write voltage applied to a write target cell in the fourth embodiment of the nonvolatile semiconductor memory device according to the present invention. Schematic block diagram showing a main configuration in a fifth embodiment of a nonvolatile semiconductor memory device according to the present invention. Waveform diagram showing a schematic waveform of a write voltage applied to a write target cell in the fifth embodiment of the nonvolatile semiconductor memory device according to the present invention; Schematic diagram showing a schematic configuration example of a memory cell Graph showing an example of threshold voltage distribution of a binary memory cell A flowchart showing a processing procedure of a writing process of a nonvolatile semiconductor memory device according to the prior art Waveform diagram showing voltage pulses applied to word lines and bit lines in time series in a writing process of a nonvolatile semiconductor memory device according to the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 10 Control circuit 11 Classification means 12 Reference write gate voltage resetting means 13 Write drain voltage resetting means 14 Voltage pulse resetting means 20 Memory cell array 30 Bit line voltage supply circuit 40 Word Line voltage supply circuit 50 Sense amplifier circuit 60 Write voltage generation circuit 70 Read voltage generation circuits D1, D2 Threshold voltage distribution

Claims (8)

One first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charge, and between the second electrodes that can be controlled by the amount of charge stored in the memory function unit Memory cells having two or more storage states defined by a conduction state are arranged in a matrix in the row and column directions, and the first electrodes of the memory cells in the same row are connected to a common word line, One of the memory cells in the same column is connected to a common bit line, and at least the other second electrode of the memory cells in the same column or row is connected to a common ground line. A memory cell array,
A threshold voltage of the write target cell is determined by applying a write gate voltage to the word line connected to the write target cell in the memory cell and applying a write drain voltage to the bit line connected to the write target cell. Non-volatile comprising: a writing means for repeatedly performing a writing process to increase the voltage from the initial storage state to the selective storage state defined by the write data while gradually increasing the write gate voltage A semiconductor memory device,
The writing means includes
After the first writing process using the reference write gate voltage, the threshold voltage of each of the write target cells is compared with a preset threshold voltage for classification, so that a plurality of write target cells can be selected according to the threshold voltage. Classification means for classifying the memory cell group,
In the write processing for each of the first memory cell groups after the classification of the memory cells by the classification means, the memory cells in the selected storage state for each of the memory cell groups excluding the memory cell group having the maximum threshold voltage Based on the difference between the lower limit value of the cell threshold voltage distribution and the upper threshold voltage of the write target cell included in the memory cell group, the write gate voltage is increased by memory cell group. A reference write gate voltage resetting means for setting an amount and resetting a voltage obtained by adding the increment for each memory cell group to the reference write gate voltage as the reference write gate voltage for each memory cell group; With
In the writing process for each of the memory cell groups after the classification of the memory cells by the classifying means, the reference write gate for each memory cell group in the previous writing process for each memory cell group. A nonvolatile semiconductor memory device, wherein the write gate voltage is increased stepwise for each of the memory cell groups by adding a predetermined increase amount set in advance to the voltage.   The classification unit classifies each of the write target cells into two memory cell groups, and the classification threshold voltage is the prediction of the write target cell after the first execution of the write process by the reference write gate voltage. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is set to a threshold voltage at a center of the threshold voltage distribution.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the classification unit includes a classification reference cell having a threshold voltage corresponding to each of the classification threshold voltages. 4.   The classification means adjusts a verify gate voltage applied to the first electrode of the determination reference cell having the same structure as the memory cell for determining whether or not the memory cell is in the selected storage state. 2. The write target cell is classified into the memory cell group by using the determination reference cell in which the current amount of the determination reference cell is controlled and the verification gate voltage is adjusted. 3. The nonvolatile semiconductor memory device according to 2.   The classification means determines whether the memory cell is in the intermediate storage state when the memory cell has an intermediate storage state between the storage state of the write target cell and the selected storage state before the execution of the write process. Adjusting the verification gate voltage applied to the first electrode of the determination reference cell in the intermediate storage state for determining whether or not, and controlling the amount of current of the determination reference cell, the verification gate 5. The nonvolatile semiconductor memory device according to claim 4, wherein each of the write target cells is classified into the memory cell group by using the determination reference cell in the intermediate storage state in which the voltage is adjusted. One first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charge, and between the second electrodes that can be controlled by the amount of charge stored in the memory function unit Memory cells having two or more storage states defined by a conduction state are arranged in a matrix in the row and column directions, and the first electrodes of the memory cells in the same row are connected to a common word line, One of the memory cells in the same column is connected to a common bit line, and at least the other second electrode of the memory cells in the same column or row is connected to a common ground line. A memory cell array,
A threshold voltage of the write target cell is determined by applying a write gate voltage to the word line connected to the write target cell in the memory cell and applying a write drain voltage to the bit line connected to the write target cell. Non-volatile comprising: a writing means for repeatedly performing a writing process to increase the voltage from the initial storage state to the selective storage state defined by the write data while gradually increasing the write gate voltage A semiconductor memory device,
The writing means includes
After the first writing process using the reference write gate voltage, the threshold voltage of each of the write target cells is compared with a preset threshold voltage for classification, so that a plurality of write target cells can be selected according to the threshold voltage. Classification means for classifying the memory cell group,
In the write processing for each of the first memory cell groups after the classification of the memory cells by the classification means, the memory cell group having a lower threshold voltage of the classified write target cell for each memory cell group Write drain voltage resetting means for resetting the write drain voltage for each of the memory cell groups so that the value of the drain voltage for use increases.
In the write processing for each of the memory cell groups after the second time after the classification of the memory cells by the classification means, by adding a predetermined increase amount set in advance to the reference write gate voltage in the previous write processing The bit line connected to the write target cell by increasing the write gate voltage and applying the write gate voltage increased stepwise to the word line connected to the write target cell. In addition, a writing process is performed by applying the writing drain voltage reset by the writing drain voltage resetting means for each memory cell group. One first electrode, a pair of second electrodes, and one or a plurality of memory function units capable of storing charge, and between the second electrodes that can be controlled by the amount of charge stored in the memory function unit Memory cells having two or more storage states defined by a conduction state are arranged in a matrix in the row and column directions, and the first electrodes of the memory cells in the same row are connected to a common word line, One of the memory cells in the same column is connected to a common bit line, and at least the other second electrode of the memory cells in the same column or row is connected to a common ground line. A memory cell array,
A threshold voltage of the write target cell is determined by applying a write gate voltage to the word line connected to the write target cell in the memory cell and applying a write drain voltage to the bit line connected to the write target cell. Non-volatile comprising: a writing means for repeatedly performing a writing process to increase the voltage from the initial storage state to the selective storage state defined by the write data while gradually increasing the write gate voltage A semiconductor memory device,
The writing means includes
After the first writing process using the reference write gate voltage, the threshold voltage of each of the write target cells is compared with a preset threshold voltage for classification, so that a plurality of write target cells can be selected according to the threshold voltage. Classification means for classifying the memory cell group,
In the write processing for each of the first memory cell groups after the classification of the memory cells by the classification means, the memory cell group having a lower threshold voltage of the classified write target cell for each memory cell group, Voltage pulse resetting means for resetting the application time of the write voltage for each memory cell group so that the application time of the write voltage specified by the write gate voltage and the write drain voltage is lengthened; With
In the write processing for each of the memory cell groups after the second time after the classification of the memory cells by the classification means, by adding a predetermined increase amount set in advance to the reference write gate voltage in the previous write processing The write gate voltage is increased stepwise, and the write voltage is defined for each of the word line and the bit line connected to the write target cell with the application time reset by the voltage pulse resetting means. A nonvolatile semiconductor memory device, wherein a writing process is performed by applying a voltage to be applied.   The classification means includes a characteristic storage means for storing information of the classified memory cell groups for each of the write target cells.

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