KR102153017B1 - Semiconductor memory device and operation method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a method of operating the same, and the semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells, a peripheral circuit for performing an erase operation and a soft program operation, and the software. And a control circuit for controlling the peripheral circuit to sequentially apply a read voltage and a soft program voltage to a selected word line among word lines of the memory cell array during a program operation.

Description

TECHNICAL FIELD [0001] A semiconductor memory device and operation method thereof

The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device that performs a soft program operation after an erase operation, and a method of operating the same.

A semiconductor memory device is a memory device that can store data and read it when necessary. Semiconductor memory devices are largely divided into RAM (Random Access Memory: RAM) and ROM (Read Only Memory: ROM). Data stored in RAM is destroyed when the power supply is interrupted. This type of memory is called volatile memory. On the other hand, the data stored in the ROM is not destroyed even if the power supply is interrupted. This type of memory is called nonvolatile memory.

During a program operation of a semiconductor memory device, memory cells are programmed using the F-N tunneling method. When a high voltage is applied to the control gate of the memory cell during the program operation, electrons are accumulated in the floating gate. During a read operation of the semiconductor memory device, a threshold voltage of a memory cell that varies depending on the amount of electrons accumulated in the floating gate is detected, and read data is determined according to the level of the detected threshold voltage.

The erase operation of the semiconductor memory device may be performed in units of selected blocks. For example, the erase operation is performed by applying a ground voltage (e.g., 0V) to all wordlines included in the selected block and applying an erase voltage (e.g., 20V) to a well of the block. I can.

Meanwhile, since the threshold voltage distribution of memory cells on which the erase operation has been completed is generally widely distributed, a time required for a program operation to be performed later may be lengthened. For example, if a memory cell having the lowest threshold voltage level and a memory cell having the highest threshold voltage among erased memory cells are simultaneously programmed, a difference in program operation speed occurs between the two memory cells.

To improve this, a soft program operation is performed after the erase operation.

1 is a circuit diagram illustrating one string of a memory cell array of a semiconductor memory device.

2 is a graph for explaining a change in a threshold voltage distribution according to a soft program operation according to the prior art.

1 and 2, in a state in which a ground voltage is applied to the bit line BL and a power voltage is connected to the source line SL during the soft program operation, a power voltage is applied to the drain selection line DSL, and the source A ground voltage is applied to the selection line SSL. At this time, a memory cell having a threshold voltage higher than the soft program verification voltage (SEV) by simultaneously applying a soft program voltage to a plurality of word lines (WL<0:n>) to soft program all of the memory cells (MC0 to MCn) at the same time. Program to be at least one or more. That is, the soft program operation is performed using a program operation similar to a general program operation method. However, when all the memory cells are programmed, the effect of reducing the width of the threshold voltage distribution is insufficient because the threshold voltages of all the memory cells increase. That is, the threshold voltage distribution B of the memory cells on which the soft program operation has been completed increases but the distribution width does not decrease compared to the threshold voltage A of the memory cells before the soft program operation.

An embodiment of the present invention is to provide a semiconductor memory device capable of improving a threshold voltage distribution of memory cells after an erase operation of a semiconductor memory device, and a method of operating the same.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, peripheral circuits for performing an erase operation and a soft program operation, and word lines of the memory cell array during the soft program operation. And a control circuit for controlling the peripheral circuit to sequentially apply a read voltage and a soft program voltage to the selected word line.

In the method of operating a semiconductor memory device according to an embodiment of the present invention, the steps of erasing a plurality of memory cells and a soft program operation are performed to increase threshold voltage values of the plurality of memory cells in an erased state. In the program operation, programming by controlling the degree of programming according to the threshold voltage values of the plurality of memory cells, and performing a soft program verification operation to verify whether the threshold voltage values of the plurality of memory cells are greater than a target threshold voltage value. And when it is determined that the threshold voltage values of the plurality of memory cells are smaller than the target threshold voltage as a result of the soft program verification operation, re-executing the soft program operation from the beginning.

In another embodiment of the present invention, a method of operating a semiconductor memory device includes applying an erase voltage to a semiconductor substrate on which a memory cell array including a plurality of memory cells is disposed to erase the plurality of memory cells; and Performing an erase verification operation on the memory cells, and when it is determined that the threshold voltages of the plurality of memory cells are lower than the target threshold voltage according to the result of the erase verification operation, the erased state is performed by performing a soft program operation. Increasing the threshold voltage values of the plurality of memory cells, the soft program operation includes controlling and programming a degree of programming according to the threshold voltage values of the plurality of memory cells.

According to the present invention, it is possible to improve a threshold voltage distribution of memory cells after an erase operation of a semiconductor memory device.

1 is a circuit diagram illustrating one string of a memory cell array of a semiconductor memory device.
2 is a graph for explaining a change in a threshold voltage distribution according to a soft program operation according to the prior art.
3 is a block diagram of a semiconductor memory device according to the present invention.
4 is a detailed circuit diagram of the memory cell array shown in FIG. 3.
5 is a flowchart illustrating a method of operating a semiconductor memory device according to the present invention.
6 is a flow chart for explaining the soft program operation illustrated in FIG. 5.
7 is a waveform diagram for explaining a potential of a bit line and a potential of a word line during a soft program operation.
8 is a graph for explaining a change in a threshold voltage distribution according to a soft program operation according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms, only the present embodiment makes the disclosure of the present invention complete and the scope of the invention to those of ordinary skill in the art It is provided to inform you.

3 is a block diagram of a semiconductor memory device according to the present invention.

Referring to FIG. 3, the semiconductor memory device 100 includes a memory cell array 110, a page buffer 120, an X decoder 130, a voltage supply unit 140, and a control circuit 150.

The memory cell array 110 includes a plurality of memory cells. The detailed configuration of the memory cell array 110 will be described later.

The page buffer 120 is connected to a plurality of bit lines BL of the memory cell array 110. The page buffer 120 senses the potentials of the bit lines BL during an erase verification operation and a soft program verification operation in response to page buffer control signals PB_signals output from the control circuit 150 to erase the memory cells. To verify.

The X decoder 130 is a voltage supply unit to a plurality of word lines WL, drain and source selection lines (DSL, SSL) of the memory cell array 110 according to the row address RADD output from the control circuit 150 The operating voltages generated at 140 are applied.

The voltage supply unit 140 responds to the voltage supply unit control signals VC_signals output from the control circuit 150 when an erasing operation is performed, the erasing voltage Verase applied to the P well of the semiconductor substrate in which the memory cell array 110 is formed. ), and generates a verification voltage (Vverify) during the erase verification operation and the soft program verification operation. In addition, the voltage providing unit 140 includes a read voltage Vread for sensing threshold voltages of memory cells of the memory cell array 110 and a soft program voltage for programming memory cells of the memory cell array 110 during a soft program operation. Operating voltages including (Vpgm) and pass voltage (Vpass) are generated.

The control circuit 150 outputs control signals VC_signals so that the voltage providing unit 140 generates the erase voltage Verase during the erase operation, and the voltage providing unit 140 outputs the read voltage Vread during the soft program operation. , So that the control signals VC_signals are output to generate the soft program voltage Vpgm and the pass voltage Vpass, and the voltage providing unit 140 generates the verification voltage Vverify during the erase verification operation and the soft program verification operation. Control signals (VC_signals) are output.

In addition, the control circuit 150 precharges the potentials of the bit lines BL to a set level during the soft program operation, and discharges the potentials of the precharged bit lines BL according to the threshold voltage of the selected memory cell. The page buffer 120, the X decoder 130, and the voltage providing unit 140 are controlled to be controlled by the amount of potential. That is, the control circuit 150 adjusts the amount of discharge potential of the bit line connected to the memory cells according to the threshold voltage values of the erased memory cells during the soft program operation, and adjusts the program degree of the memory cell according to the potential of the bit line. The page buffer 120, the X decoder 130, and the voltage providing unit 140 are controlled as possible.

In addition, the control circuit 150 detects the pass/fail result of the erase verification operation and the soft program verification operation by sensing the potential of the bit lines BL during the erase verification operation and the soft program verification operation. Outputs buffer control signals PB_signals.

4 is a detailed circuit diagram of the memory cell array shown in FIG. 3.

Referring to FIG. 4, the memory cell array 110 includes a plurality of strings ST0 to STk. Since the plurality of strings ST0 to STk have a similar structure, a single string ST0 will be described in detail.

The string ST0 includes a source selection transistor SST connected between the source line SL and the bit line BL0, a first dummy cell DMC0, a plurality of memory cells MC0 to MCn, and a dummy cell DMC1. ) And a drain select transistor DST. First and second dummy transistors may be formed instead of the first and second dummy cells DMC0 and DMC1, and two first and second dummy cells DMC0 and DMC1 may be disposed, respectively.

A source selection line SSL and a drain selection line DSL are connected to the gates of the source selection transistor SST and the drain selection transistor DST, respectively, and the gates of the first and second dummy cells DMC0 and DMC1 are connected to each other. The first and second dummy word lines DWL<0> and DWL<1> are connected, and a plurality of word lines WL<n:0> are connected to the plurality of memory cells MC0 to MCn.

A plurality of memory cells of the memory cell array 110 may define memory cells connected to the same word line as one page. That is, the memory cell array 110 may be composed of a plurality of pages.

5 is a flowchart illustrating a method of operating a semiconductor memory device according to the present invention.

A method of operating a semiconductor memory device according to the present invention will be described with reference to FIGS. 3 to 5.

1) Erase operation (S510)

The voltage providing unit 140 generates an erase voltage Verase in response to the voltage providing unit control signals output from the control circuit 150. The generated erase voltage Verase is applied to the P well of the semiconductor substrate in which the memory cell array 110 is formed. At this time, 0V may be applied to the word lines of the memory cell array 110.

As a result, charges stored in the floating gates of the plurality of programmed memory cells of the memory cell array 110 are tunneled to the semiconductor substrate through the tunnel insulating layer and exit, thereby decreasing the threshold voltage of the memory cells.

2) Erasure verification (S520)

After the erase operation (S510), the memory cells of the memory cell array 110 are lower than the target threshold voltage HEV using the page buffer 120 connected to the bit lines BL of the memory cell array 110 Verify that it has a voltage value. In this case, the erase verification operation is preferably performed by sensing threshold voltage values of memory cells using a virtual negative read (VNR) method. In more detail, when the threshold voltage sensing operation of memory cells is performed, voltages applied to the bit line voltage and the P-well are applied by increasing the core voltage (for example, 1V). Accordingly, even if the threshold voltage value of the memory cells is a negative voltage value (for example, -1V), it can be sensed as a value raised by the core voltage Vcore.

3) Erasing verification operation determination (S530)

As a result of the above-described erase verification operation (S520), when the threshold voltage values of all memory cells have a threshold voltage value lower than the target threshold voltage HEV, it is determined as a pass, and the threshold voltage value of at least one memory cell is the target threshold. If it is higher than the voltage (HEV), it is judged as a failure.

4) Increase the erase voltage (S540)

When the above-described erase verification operation determination (S530) is determined to be a failure, a voltage obtained by raising the erase voltage Verase used in the previous erase operation (S510) by a step voltage is set as a new erase voltage (Verase), and the above-described The erase operation is performed again from S510. The voltage supply unit 140 increases the erasing voltage Verase used in the previous erasing operation S510 by a step voltage in response to the voltage supply unit control signals output from the control circuit 150. Create

5) Soft program operation (S550)

If it is determined as a pass as a result of the above-described erase verification operation determination (S530), a soft program operation is performed.

Detailed operation description of the soft program operation will be described later.

6) Soft program verification operation (S560)

After completing the soft program operation (S550), a soft program verification operation is performed. The soft program verification operation senses threshold voltage values of memory cells programmed using a page buffer, and detects the presence or absence of memory cells having a threshold voltage value higher than the Mokpo threshold voltage value SEV among the programmed memory cells.

In the above-described soft program verification operation, it is preferable to perform verification by sensing threshold voltage values of memory cells using a virtual negative read (VNR) method.

7) Soft program verification operation determination (S570)

As a result of the above-described soft program verification operation (S560), if at least one memory cell having a threshold voltage value higher than the Mokpo threshold voltage value (SEV) among the programmed memory cells is determined as a path, the page address is changed and described above. The soft program operation (S550) and the soft program verification operation (S560) are performed again. In addition, when the soft program operation (S550) and the soft program verify operation (S560) are completed for all pages, the operation of the semiconductor memory device is terminated.

If the threshold voltage values of all the memory cells are lower than the Mokpo threshold voltage value SEV, it is determined that the soft program operation of the corresponding page has failed, and the above-described soft program operation (S550) is repeated.

At this time, when the number of cycles in which the soft program operation (S550) and the soft program verification operation (S560) are repeatedly performed for one page is counted and the number of times counted is greater than the set number, the operation for the memory cell array 110 is failed. It can be judged as a bad block.

6 is a flow chart for explaining the soft program operation illustrated in FIG. 5.

7 is a waveform diagram for explaining a potential of a bit line and a potential of a word line during a soft program operation.

8 is a graph for explaining a change in a threshold voltage distribution according to a soft program operation according to the present invention.

The soft program operation according to the present invention will be described in detail with reference to FIGS. 3, 4, 6, 7, and 8 as follows.

1) Bit lines precharge (S551)

The page buffer 120 sets the bit lines BL0 to BLk of the memory cell array 110 to a power supply voltage level (Vcc) or a set voltage in response to page buffer control signals PB_signals output from the control circuit 150. Precharge to the level.

2) Erasing cell threshold voltage sensing (S552)

The voltage providing unit 140 generates a read voltage Vread and a pass voltage Vpass in response to the voltage providing unit control signals VC_signals output from the control circuit 150. The read voltage Vread is preferably set to a voltage lower than the target threshold voltage HEV of the erase operation, and the pass voltage Vpass is preferably set to a voltage higher than 0V.

The X decoder 130 is a voltage supply unit to a plurality of word lines WL, drain and source selection lines (DSL, SSL) of the memory cell array 110 according to the row address RADD output from the control circuit 150 The operating voltages generated at 140 are applied. In an embodiment of the present invention, a word line (WL<0>) is selected from among a plurality of word lines (WL<0;n>) and the remaining word lines (WL<n;1>) are not selected to perform a soft program operation. Explain what to do. The X decoder 130 applies the read voltage Vread to the selected word line WL<0> according to the row address RADD and the pass voltage Vpass to the remaining unselected word lines WL<n; 1>. Is applied. At this time, an operating voltage (for example, Vcc) is applied to the drain and source selection lines (DSL, SSL) and the first and second dummy word lines (DWL<0> and DWL<1>). , SST) and the first and second dummy cells DMC0 and DMC1 are turned on.

Accordingly, the precharged bit lines BL0 to BLk of the memory cell array 110 are discharged according to the threshold voltage values of the memory cells MC0 connected to the selected word line WL<0>. In more detail, the amount of discharge current of the bit line is adjusted according to the threshold voltage values of the memory cells MC0. Accordingly, each bit line is discharged to have a potential corresponding to the threshold voltage value of the connected memory cell. For example, when the threshold voltage value of the connected memory cell is relatively high, the bit line maintains a potential level close to the precharge level, and when the threshold voltage value of the connected memory cell is relatively low, it is discharged to a potential level close to 0V. .

3) Applying a pass voltage to the unselected word line (S553)

The voltage providing unit 140 generates a pass voltage Vpass in response to the voltage providing unit control signals VC_signals output from the control circuit 150.

The X decoder 130 is a voltage supply unit to a plurality of word lines WL, drain and source selection lines (DSL, SSL) of the memory cell array 110 according to the row address RADD output from the control circuit 150 The operating voltages generated at 140 are applied. That is, the X decoder 130 applies a pass voltage to the unselected word lines WL<n;1> according to the row address RADD, and the drain and source selection lines DSL and SSL 2 Drain and source selection transistors DST and SST and first and second dummy cells DMC0 and DMC1 by applying an operating voltage (for example, Vcc) to dummy word lines DWL<0> and DWL<1> Turn them on.

4) Applying the soft program voltage to the selected word line (S554)

The voltage providing unit 140 generates a soft program voltage Vpgm in response to the voltage providing unit control signals VC_signals output from the control circuit 150.

The X decoder 130 applies the soft program voltage Vpgm to the selected word line WL<0> of the memory cell array 110 according to the row address RADD output from the control circuit 150.

Each of the selected memory cells MC0 is controlled in a program operation according to the potential of the connected bit lines BL0 to BLk.

When the potential of the bit line is relatively close to the precharge level, more specifically, when the potential difference (Vgs) between the potential of the bit line and the drain selection line (DSL) is less than the threshold voltage (Vt) of the drain selection transistor The selection transistor is turned off, and the potential of the channel in which the memory cell MC0 is formed is boosted by the soft program voltage Vpgm applied to the selected word line WL<0>, so that the memory cell MC0 is not programmed. At this time, the level of boosting of the channel changes according to the degree that the potential difference Vgs is smaller than the threshold voltage Vt of the drain select transistor, so that the threshold voltage of the memory cell may increase. That is, even if the potential difference Vgs is smaller than the threshold voltage Vt of the drain select transistor, the threshold voltage of the memory cell may increase in proportion to the level of the potential difference Vgs.

On the other hand, when the potential of the bit line is relatively far from the precharge level and close to 0V, in more detail, the difference (Vgs) between the potential of the bit line and the drain selection line (DSL) is the threshold voltage (Vt) of the drain selection transistor. If it is greater than ), the drain select transistor is turned on, and the memory cell MC0 is programmed by the soft program voltage Vpgm applied to the selected word line WL<0>.

Accordingly, the memory cells having a low threshold voltage and the memory cells having a relatively high threshold voltage can be soft programmed with different programming degrees, thereby narrowing the width of the threshold voltage distribution of the memory cells. That is, the degree to which the channel is boosted is adjusted according to the potential difference (Vgs) between the potential of the bit line and the potential of the drain selection line (DSL). It can be programmed to have.

All of the memory cells MC0 to MCn of the memory cell array 110 subjected to the above-described soft program operation have a threshold voltage value of 0V or less, that is, a threshold voltage value in an erase state. That is, the soft program operation is not an operation for storing data, and is performed to increase the threshold voltage values of the plurality of memory cells close to 0V and to decrease the threshold voltage distribution width.

After completing the soft program operation, the semiconductor memory device may perform a program operation for storing data.

100: semiconductor memory device
110: memory cell array
120: page buffer
130: X decoder
140: voltage supply unit
150: control circuit

Claims (20)

A memory block including a plurality of memory cells;
A peripheral circuit for performing a soft program operation and a soft program verification operation after performing an erase operation on the memory block; And
A semiconductor memory device including a control circuit for controlling an operation of the peripheral circuit, wherein the control circuit performs the soft program operation and performs a soft program verification operation for verifying completion of the soft program operation. Control,
The soft program operation,
Precharging a plurality of bit lines respectively connected to the plurality of memory cells,
Applying a read voltage to a selected word line commonly connected to the plurality of memory cells,
A semiconductor memory for applying a soft program voltage to the selected word line in a state in which voltages of the plurality of bit lines are discharged with voltages respectively corresponding to threshold voltages of the plurality of memory cells according to the application of the read voltage Device.
delete ◈ Claim 3 was abandoned upon payment of the set registration fee. The method of claim 1,
A page buffer for precharging the bit lines;
The peripheral circuit may include a voltage supply unit configured to generate the read voltage and the soft program voltage in response to voltage supply unit control signals output from the control circuit; And
The potential of the precharged bit line by sequentially applying the read voltage and the soft program voltage to the selected word line in response to a row address signal output from the control circuit is discharged according to the threshold voltage values of the memory cells. A semiconductor memory device including an X decoder for controlling to be programmed after being programmed.
◈ Claim 4 was abandoned upon payment of the set registration fee. The method of claim 1,
The control circuit controls the peripheral circuit to program the memory block in a page unit during the soft program operation.
delete ◈ Claim 6 was abandoned upon payment of the set registration fee. The method of claim 1,
When the potential level of the discharged bit lines and the potential difference between the drain selection line among the plurality of word lines is less than the threshold voltage of the drain selection transistor, the memory cells connected to the bit lines are programmed during the soft program operation. A semiconductor memory device that is controlled and programmed.
◈ Claim 7 was abandoned upon payment of the set registration fee. The method of claim 6,
When a potential difference between a potential level of the discharged bit lines and a potential of the drain select line is greater than a threshold voltage of the drain select transistor, a memory cell connected to the bit line is programmed during the soft program operation.
◈ Claim 8 was abandoned upon payment of the set registration fee. The method of claim 1,
The semiconductor memory device wherein the read voltage is lower than a target threshold voltage value during an erase operation.
◈ Claim 9 was abandoned upon payment of the set registration fee. The method of claim 3,
The page buffer senses potentials of the bit lines to perform an erase verification operation and a soft program verification operation.
◈ Claim 10 was abandoned upon payment of the set registration fee. The method of claim 1,
The soft program operation is performed after an erase operation is completed, and all memory cells in which the soft program operation is performed have a threshold voltage distribution in an erase state.
Erasing a plurality of memory cells included in the memory block;
Precharging a plurality of bit lines respectively connected to the plurality of memory cells;
Applying a read voltage to a selected word line commonly connected to the plurality of memory cells;
Applying a soft program voltage to the selected word line in a state in which voltages of the plurality of bit lines are discharged with voltages corresponding to threshold voltages of the plurality of memory cells according to the application of the read voltage;
Performing a soft program verification operation to verify whether a threshold voltage value of the plurality of memory cells is greater than a target threshold voltage value; And
Reapplying the soft program voltage according to a result of the soft program verification operation.
delete delete ◈ Claim 14 was abandoned upon payment of the set registration fee. The method of claim 11, wherein applying a soft program voltage to the selected word line comprises:
When the voltage difference between the discharged bit lines and the drain select line among the plurality of word lines is less than the threshold voltage of the drain select transistor, the degree to which the memory cells connected to the bit lines are programmed is controlled How the device works.
◈ Claim 15 was abandoned upon payment of the set registration fee. The method of claim 14,
A method of operating a semiconductor memory device in which a boosting level of a channel is changed according to the potential difference when a difference between the discharged potential levels of the bit lines and the drain selection line is less than the threshold voltage of the drain selection transistor.
delete ◈ Claim 17 was abandoned upon payment of the set registration fee. The method of claim 11,
The method of operating a semiconductor memory device in which the target threshold voltage value is lower than 0V.
Erasing the plurality of memory cells by applying an erase voltage to a semiconductor substrate on which a memory cell array including a plurality of memory cells is disposed;
Performing an erase verification operation on the plurality of memory cells;
Precharging a plurality of bit lines connected to the plurality of memory cells when threshold voltages of the plurality of memory cells are lower than a target threshold voltage according to a result of the erase verification operation;
Applying a read voltage to a selected word line commonly connected to the plurality of memory cells; And
In a state in which voltages of the plurality of bit lines are discharged with voltages respectively corresponding to threshold voltages of the plurality of memory cells according to the application of the read voltage, a soft program operation is performed on the memory cells connected to the selected word line. Step to; and
And performing a soft program verification operation for verifying whether the soft program operation is completed.
◈ Claim 19 was abandoned upon payment of the set registration fee. The method of claim 18,
When there is at least one memory cell in which the threshold voltages of the plurality of memory cells are higher than the target threshold voltage according to the result of the erase verification operation, from the step of increasing the erase voltage by a step voltage and then erasing the plurality of memory cells. A method of operating a semiconductor memory device comprising the step of re-performing.
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