KR102064514B1 - Method for operating semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of operating a semiconductor memory device, wherein an operating voltage is applied to a drain select line connected to a drain select transistor of a memory cell block, the operating voltage being a precharged bit line potential and a threshold voltage value of the drain select transistor. Controlling the power supply to be higher than the sum of the power source and increasing the potential level of the word line adjacent to the drain select line by an operating voltage applied to the drain select line; And after the potential level of the adjacent word line rises, applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block, and applying a pass voltage to an unselected word line.

Description

Method for operating semiconductor memory device

The present invention relates to a method of operating a semiconductor memory device, and more particularly, to a method of operating a semiconductor memory device for suppressing a program disturb phenomenon during a program operation.

A semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices are roughly divided into random access memory (RAM) and read only memory (ROM). Data stored in RAM is destroyed when power supply is interrupted. This type of memory is called volatile memory. On the other hand, data stored in the ROM is not destroyed even when the power supply is interrupted. This type of memory is called nonvolatile memory.

NAND flash memory devices of the nonvolatile memories described above are designed to have a high degree of integration for high capacity, and thus, the spacing between word lines constituting the cell block is reduced. As a result, noise is generated by the coupling capacitor between each word line. In particular, in the erase operation, edge memory cells are less erased than memory cells due to coupling noise between the selection transistor and the edge memory cell adjacent to the selection transistor.

 Due to this characteristic, edge memory cells having a higher threshold voltage than other memory cells after the erase operation is completed may reduce a channel boosting phenomenon of a cell string in a program inhibit mode during a program operation.

An embodiment of the present invention provides a program method of a semiconductor memory device that can reduce a program disturb phenomenon during a program operation of the semiconductor memory device and an erase method that can improve the threshold voltage distribution of the memo cell during the erase operation.

A method of operating a semiconductor memory device according to an exemplary embodiment of the present invention applies an operating voltage to a drain select line connected to a drain select transistor of a memory cell block, wherein the operating voltage is a precharged bit line potential and a threshold of the drain select transistor. Controlling the voltage value to be higher than a sum of voltage values and increasing a potential level of a word line adjacent to the drain select line by an operating voltage applied to the drain select line; And after the potential level of the adjacent word line rises, applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block, and applying a pass voltage to an unselected word line.

A method of operating a semiconductor memory device according to another exemplary embodiment of the present invention applies an operating voltage to a drain select line connected to a drain select transistor of a memory cell block for a predetermined time, wherein the operating voltage is a precharged bit line potential and the drain select. Controlling the transistor to be higher than a sum of threshold voltage values of the transistor, increasing a potential level of a word line adjacent to the drain select line by an operating voltage applied to the drain select line, and bringing the operating voltage to a low level. Applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block, and applying a pass voltage to an unselected word line when the transition and the rising to the high level again.

In another aspect of the present invention, there is provided a method of operating a semiconductor memory device, the method including applying an operating voltage to a drain select line connected to a drain select transistor of a memory cell block, and when the operating voltage is applied to the drain select line, Applying a pre-pass voltage to a word line adjacent to the drain select line, and applying a pre-pass voltage to the adjacent word line, and then applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block. And applying a pass voltage to the unselected word lines.

In another aspect of the present invention, there is provided a method of operating a semiconductor memory device, the method including applying an operating voltage to a drain select line connected to a drain select transistor of a memory cell block, and when the operating voltage is applied to the drain select line, Applying a pre-pass voltage to a plurality of word lines adjacent to the drain select line, and applying a pre-pass voltage to the plurality of adjacent word lines, and then applying the pre-pass voltage to the selected word line among the plurality of word lines connected to the memory cell block. Applying a program voltage and applying a pass voltage to the unselected word lines.

A method of operating a semiconductor memory device according to another embodiment of the present invention may include applying an erase voltage to a P well of a semiconductor substrate on which a memory cell block is disposed, and negatively affecting memory cells adjacent to a selection transistor of the memory cell block. And erasing by applying a voltage.

According to the present invention, a program disturb phenomenon can be reduced during a program operation of a semiconductor memory device, and a threshold voltage distribution of a memo cell can be improved during an erase operation.

1 is a configuration diagram illustrating a configuration of a semiconductor memory device.
FIG. 2 is a detailed circuit diagram of the memory cell block of FIG. 1.
3A and 3B are graphs illustrating a program method of a semiconductor memory device according to an embodiment of the present invention.
4A to 4C are graphs for describing a program method of a semiconductor memory device according to another exemplary embodiment.
5 is a graph illustrating an erase method of a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a semiconductor memory device according to the present invention.

Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell block 110, a page buffer 120, an X decoder 130, a voltage providing unit 140, and a control circuit 150.

The memory cell block 110 includes a plurality of memory cells. The detailed configuration of the memory cell block 110 will be described later.

The page buffer 120 is connected to the plurality of bit lines BL of the memory cell block 110. In response to the page buffer control signals PB_signals output from the control circuit 150, the page buffer 120 discharges the bit line to a low level according to the program data value and sets the bit line to the program mode, or sets the bit line to the program mode. Set to program inhibit mode by keeping high level.

The X decoder 130 may include a plurality of word lines WL <n: 0>, drains, and source select lines DSL and SSL of the memory cell block 110 according to a row address RADD output from the control circuit 150. ) To the operating voltages generated by the voltage providing unit 140.

The voltage provider 140 applies an erase voltage Verase applied to a P well of a semiconductor substrate on which the memory cell block 110 is formed during an erase operation in response to voltage provider control signals VC_signals output from the control circuit 150. And a negative voltage for applying to the edge word line WL <n> of the memory cell block 110 and a program voltage Vpgm for applying to selected memory cells of the memory cell block 110 during a program operation. And a pass voltage Vpass for applying to unselected memory cells, a pre-pass voltage pre_Vpass for applying to an edged memory cell, and an operating voltage for applying to a drain select transistor. The operating voltage for applying to the drain select transistor is higher than the power supply voltage Vcc, and more preferably has a value higher than the sum of the potential Vbl of the precharged bit line and the threshold voltage Vt of the drain select transistor. It is preferable.

The control circuit 150 outputs control signals VC_signals such that the voltage providing unit 140 generates an erase voltage Verase during an erase operation, and outputs a program voltage Vpgm, a pass voltage Vpass, and a free signal during a program operation. The control signals VC_signals are output to generate an operating voltage for applying the pass voltage pre_Vpass and the drain select transistor.

In addition, the control circuit 150 precharges the potentials of the bit lines BL to a set level during a program operation, and maintains or discharges the potential of the precharged bit lines BL according to a program data value. The page buffer control signals PB_signals for controlling the page buffer 120 are output.

In addition, the control circuit 150 may include a program voltage Vpgm, a pass voltage Vpass, a pre-pass voltage pre_Vpass, and an operating voltage for applying a drain selection transistor to a memory cell. A row address RADD for controlling the X decoder 130 to be applied to the block 110 is output, and a negative voltage generated by the voltage provider 140 during an erase operation is generated in the plurality of memory cell blocks 110. A row address RADD is output for controlling to be applied to edge memory cells among the memory cells.

FIG. 2 is a detailed circuit diagram of the memory cell block shown in FIG. 1.

Referring to FIG. 2, the memory cell block 110 includes a plurality of strings ST0 to STk. Since the plurality of strings ST0 to STk have a similar structure, one string ST0 will be described in detail as an example.

The string ST0 includes a source select transistor SST, a plurality of memory cells MC0 to MCn, and a drain select transistor DST connected between the source line SL and the bit line BL0.

The gates of the source select transistor SST and the drain select transistor DST are connected to the source select line SSL and the drain select line DSL, respectively, and the plurality of word lines WL are provided in the plurality of memory cells MC0 to MCn. <n: 0>) is concatenated.

The plurality of memory cells of the memory cell block 110 may define memory cells connected to the same word line as one page. That is, the memory cell block 110 may be composed of a plurality of pages.

3A and 3B are graphs illustrating a program method of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIGS. 1, 2, and 3A, a program method of a semiconductor memory device according to an embodiment of the present invention will be described as follows.

The page buffer 120 precharges all the bit lines BL0 to BLk to a high level in response to the page buffer control signals PB_signals output from the control circuit 150, and then stores the program data stored in the page buffer 120. In some cases, the potential of the corresponding bit line is maintained at the precharge level or discharged at the low level.

Thereafter, the voltage providing unit 140 applies an operating voltage for applying to the drain selection transistor DST of the memory cell block 110 in response to the voltage providing control signals VC_signals output from the control circuit 150. Create The operating voltage at this time is preferably higher than the power supply voltage (Vcc). More specifically, the operating voltage preferably has a value higher than the sum of the voltage Vbl of the precharged bit line and the threshold voltage Vt of the drain select transistor DST.

The X decoder 130 may drain the operating voltage (value higher than Vbl + Vt) generated by the voltage providing unit 140 according to the row address RADD output from the control circuit 150. It is applied to the drain select line DSL connected to the DST.

As a result, the potential of the word line WL <n> adjacent to the drain select transistor DSL increases by a predetermined level at 0V due to the coupling phenomenon.

After that, the voltage providing unit 140 may be connected to an unselected word line among the word lines of the memory cell block 110 in response to the voltage providing control signals VC_signals output from the control circuit 150. A pass voltage Vpass for applying and a program voltage Vpgm for applying to the selected word line sel WL are generated. The X decoder 130 may apply the pass voltage Vpass and the program voltage Vpgm generated by the voltage providing unit 140 according to the row address RADD output from the control circuit 150. Selectively applies to: 0>). At this time, the pass voltage Vpass is applied when the word line WL <n> is included in the unselected word line unsel WL, and the program voltage Vpgm is applied when the word line WL <n> is included in the selected word line sel WL.

When the pass voltage Vpass and the program voltage Vpgm are selectively applied to the plurality of word lines WL <n: 0>, the potential of the drain select line DSL drops below the power supply voltage level as shown in the figure. .

The memory cells connected to the word line sel WL selected by the above operation are programmed according to the potential of the corresponding bit line.

In this case, in the case of the program inhibiting string in which the potential of the bit line is maintained at the precharge level, the selected memory cell may be boosted by the pass voltage Vpass, even if the program voltage Vpgm is applied to the selected word line sel WL. Must not be programmed. In the present invention, before the pass voltage Vpass is applied to unselected word lines unsel WL, the potential of the precharged bit line is applied by applying an operating voltage higher than the power supply voltage Vcc to the drain select line DSL. The word line WL <n> adjacent to the drain select transistor DSL by a potential of the drain select line DSL is transferred to a channel without drop and is brought to a predetermined level before the pass voltage Vpass is applied. As a result, the channel potential of the string in the program prohibition mode may be increased by a predetermined level before the channel boosting operation. As a result, the boosting level is increased during the channel boosting operation.

Accordingly, the threshold voltage of the memory cell connected to the selected word line sel WL among the memory cells included in the string of the program inhibit mode may not be increased.

3B illustrates a program operation similar to that of FIG. 3A. Referring to FIG. 3B, an operating voltage applied to the drain select line DSL is applied at a high level for a predetermined time and then transitions to a 0V level. As a result, the potential of the word line WL <n> adjacent to the drain select line DSL also rises to a constant potential level for a predetermined time when the operating voltage applied to the drain select line DSL is applied at a high level.

Subsequent operations are similar to that of FIG. 3A, and thus a detailed description thereof will be omitted.

4A to 4C are graphs for describing a program method of a semiconductor memory device according to another exemplary embodiment.

Referring to FIGS. 1, 2, and 4A, a program method of a semiconductor memory device according to an embodiment of the present invention will be described as follows.

The page buffer 120 precharges all the bit lines BL0 to BLk to a high level in response to the page buffer control signals PB_signals output from the control circuit 150, and then stores the program data stored in the page buffer 120. In some cases, the potential of the corresponding bit line is maintained at the precharge level or discharged at the low level.

Thereafter, the voltage providing unit 140 applies an operating voltage for applying to the drain select transistor DST of the memory cell block 110 in response to the voltage providing control signals VC_signals output from the control circuit 150. The pre-pass voltage Pre_Vpass is generated to be applied to the memory cell MCn adjacent to the drain select transistor DST.

The X decoder 130 may connect the operating voltage generated by the voltage providing unit 140 to the drain select transistor DST of the cell block 110 according to the row address RADD output from the control circuit 150. The pre-pass voltage Pre_Vpass is applied to the word line WL <n> connected to the memory cell MCn.

After that, the voltage providing unit 140 may be connected to an unselected word line among the word lines of the memory cell block 110 in response to the voltage providing control signals VC_signals output from the control circuit 150. A pass voltage Vpass for applying and a program voltage Vpgm for applying to the selected word line sel WL are generated. The X decoder 130 may apply the pass voltage Vpass and the program voltage Vpgm generated by the voltage providing unit 140 according to the row address RADD output from the control circuit 150. Selectively applies to: 0>). At this time, the pass voltage Vpass is applied when the word line WL <n> is included in the unselected word line unsel WL, and the program voltage Vpgm is applied when the word line WL <n> is included in the selected word line sel WL.

The memory cells connected to the word line sel WL selected by the above operation are programmed according to the potential of the corresponding bit line.

At this time, in the case of the program inhibiting string in which the potential of the bit line is maintained at the precharge level, the selected memory cell may be boosted by the pass voltage Vpass, even if the program voltage Vpgm is applied to the selected word line sel WL. Must not be programmed. In the present invention, the pre-pass voltage Pre_Vpass is applied to the word line WL <n> adjacent to the drain select line DSL before the pass voltage Vpass is applied to the unselected word lines unsel WL. Before the boosting operation, the channel potential of the string in the program prohibition mode may be increased by a predetermined level before the channel boosting operation. As a result, the boosting level is increased during the channel boosting operation.

Accordingly, the threshold voltage of the memory cell connected to the selected word line sel WL among the memory cells included in the string of the program inhibit mode may not be increased.

FIG. 4B is a diagram illustrating a program operation similar to that of FIG. 4A. Referring to FIG. 4B, after applying the pre-pass voltage Pre_Vpass applied to the word line WL <n> to a high level for a predetermined time, the 0V level is illustrated. Transition to.

Subsequent operations are similar to that of FIG. 3A, and thus a detailed description thereof will be omitted.

FIG. 4C is a diagram illustrating a program operation similar to that of FIG. 4A. Referring to FIG. 4B, when the pre-pass voltage Pre_Vpass is applied to the word line WL <n>, it is adjacent to the word line WL <n>. The pre-pass voltage Pre_Vpass is also applied to the word line WL <n-1>. As a result, the potential of the word line WL <n> rises more than the pre-pass voltage Pre_Vpass due to the coupling phenomenon, thereby increasing the potential of the channel.

Since the operation method is similar to FIG. 4A, detailed description thereof will be omitted.

5 is a graph illustrating an erase method of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 5, the voltage provider 140 applies the P well of the semiconductor substrate on which the memory cell block 110 is disposed in response to the voltage provider control signals VC_signals output from the control circuit 150. A negative voltage is applied to the erase voltage Verase and the word select line WLn adjacent to the drain select line DSL.

While the erase voltage Verase generated by the voltage providing unit 140 is applied to the P well of the semiconductor substrate, the X decoder 130 may apply the voltage providing unit according to the row address RADD output from the control circuit 150. The negative voltage generated at 140 is applied to the word line WLn adjacent to the drain select line DSL. At this time, the remaining word lines WL <n-1: 1> are preferably floated for a predetermined time and then maintained at 0V.

As a result, the potential difference between the gate and the semiconductor substrate is greater than the erase voltage Verase, so that the memory cells MCn connected to the word line WLn are erased so that the threshold voltage is lower during the erase operation. As a result, in the erase operation, edge memory cells adjacent to the drain select transistor may be less erased than other memory cells.

According to an exemplary embodiment of the present invention, a negative voltage is applied only to the word line WLn adjacent to the drain select line DSL, but the word line WL0 adjacent to the source select line SSL is also erased. A negative voltage can be applied.

100: semiconductor memory device
110: memory cell block
120: page buffer
130: X decoder
140: voltage providing unit
150: control circuit

Claims (5)

Applying an operating voltage to a drain select line connected to a drain select transistor of a memory cell block, wherein the operating voltage is controlled to be higher than a sum of a precharged bit line potential and a threshold voltage value of the drain select transistor;
Increasing the potential level of the word line adjacent to the drain select line by an operating voltage applied to the drain select line; And
Applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block after the potential level of the adjacent word line rises, and applying a pass voltage to an unselected word line; Method of operation.
Applying an operating voltage to a drain select line connected to a drain select transistor of a memory cell block for a predetermined time, wherein the operating voltage is controlled to be higher than a sum of a precharged bit line potential and a threshold voltage value of the drain select transistor;
Increasing the potential level of the word line adjacent to the drain select line by an operating voltage applied to the drain select line; And
Applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block and applying a pass voltage to an unselected word line when the operating voltage transitions to a low level and rises again to a high level again; Method of operating a semiconductor memory device comprising a.
Applying an operating voltage to a drain select line connected to the drain select transistor of the memory cell block;
Applying a pre-pass voltage to a word line adjacent to the drain select line when the operating voltage is applied to the drain select line; And
After applying a pre-pass voltage to the adjacent word line, applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block, and applying a pass voltage to an unselected word line. How the memory device works.
Applying an operating voltage to a drain select line connected to the drain select transistor of the memory cell block;
When the operating voltage is applied to the drain select line, applying a pre-pass voltage to a plurality of word lines adjacent to the drain select line; And
After applying a pre-pass voltage to the plurality of adjacent word lines, applying a program voltage to a selected word line among a plurality of word lines connected to the memory cell block, and applying a pass voltage to an unselected word line. A method of operating a semiconductor memory device.
Applying an erase voltage to a P well of a semiconductor substrate on which a memory cell block is disposed; And
Applying a negative voltage to memory cells adjacent to the selection transistor of the memory cell block to erase the memory cell;
The erasing may include floating memory cells not adjacent to the selection transistor for a predetermined time.

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