KR100624301B1 - Method for programming nand-type flash memory device - Google Patents

Abstract

The present invention applies a channel boosting prevention voltage lower than a program prohibition voltage applied to other word lines to edge word lines connected to memory cells closest to the select transistors to select the memory cells connected to the edge word lines. The present invention relates to a nonvolatile memory device which prevents program disturb caused by hot electrons by reducing electric fields between transistors, that is, by reducing energy of hot electrons.

Hot Electron, Edge Wordline, Program Disturbance

Description

Program method of NAND flash memory device {Method for programming NAND-type flash memory device}

1 illustrates a general NAND flash memory device.

FIG. 2 is a graph illustrating a threshold voltage (program speed) according to each word line in FIG. 1.

3 is a flowchart illustrating a sequential program method of a NAND flash memory device according to a preferred embodiment of the present invention.

4 is a timing diagram illustrating a program voltage according to an incremental step pulse program (ISPP).

<Description of Symbols for Main Parts of Drawings>

MC: memory cell DSL: drain select line

SSL: source selection line CSL: common source line

The present invention relates to a method of programming a NAND flash memory device, and more particularly, to a sequential program method of a NAND flash memory device for improving a program threshold voltage distribution.

 Flash memory is a non-volatile memory that can store data when power is cut off. It can be programmed and erased electrically. It requires refresh function to rewrite data at regular intervals. Refers to a device that is not present. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of erasing data from a memory. Such flash memory devices are largely divided into NOR and NAND flash according to the cell structure and operating conditions. Noah-type flash memory is a source of each memory cell transistor is connected to the ground terminal (VSS) can be programmed and erased to any address, it is mainly used in applications requiring high-speed operation. In contrast, as shown in FIG. 1, a NAND flash memory has a structure in which a plurality of memory cell transistors MC0 to MC31 are connected in series to form one string, and one string is connected to a source and a drain. It is mainly used in highly integrated data archiving applications.

Referring to FIG. 1, the number of memory cells MC0 to MC31 connected in series between the drain select transistor DST and the source select transistor SST is 16 in consideration of device and density. 32 or 64. In FIG. 1, N strings 1-1 and 1-n exist with 32 memory cells as one string. Memory cells (eg MC0) are controlled by one word line WL0 and form one page. In FIG. 1, there are 32 pages.

FIG. 2 is a flowchart showing a program method of the NAND flash memory device shown in FIG. 1 using a sequential method.

In the method of programming a NAND flash memory device, first, a program bias, that is, a program voltage is applied to the first word line WL0 to program data in the memory cell MC0 (S11). Next, it is verified whether or not data is programmed in the memory cell MC0 (S12). At this time, if the threshold voltage Vt of the programmed memory cell MC0 is smaller than the target threshold voltage Vt (S13), since data is not normally programmed in the memory cell MC0, the program voltage is added to the word line WL0 again with the program bias + 0.5V. It is applied to the word line WLO (S14) to program the memory cell MCO again. On the other hand, when the threshold voltage Vt of the programmed memory cell MC0 is greater than the target threshold voltage Vt (S13), since data is normally programmed in the memory cell MC0, the program for the memory cell MC0 is terminated, and the program is performed in the next word line WL1. Program MC1 by applying voltage. The program is sequentially performed to the memory cell MC31 connected to the last word line WL31 in the same manner as the program method of MC0 described above.

However, in the sequential method of the conventional NAND flash memory device, the program speed of the memory cell MC31 connected to the last word line WL31 is slower than that of other memory cells MC0 to MC30. This is because the last word line WL31 is adjacent to the drain select line DSL and is subject to interference by the power supply voltage VCC applied to these drain select line DSL. In more detail, the program inhibit voltage Vpass corresponding to approximately 8V to 10V is applied to the unselected word line during the program operation, while the power supply voltage VCC is applied to the drain select line DSL. In this case, the memory cells MC31 are subjected to an interference effect by the potential of the drain select transistor DST, so that the program speed of the memory cell MC31 is lower than the program speeds of the other memory cells MC0 to MC30.

3 is a graph illustrating threshold voltages according to word lines, and a low threshold voltage indicates a slow program speed. In the drawings, letters A and B represent different chips.

As shown in FIG. 3, it can be seen that the threshold voltage Vt of the memory cell MC31 connected to the last word line WL31 closest to the drain select line DSL is the lowest.

As described above, the threshold voltage Vt of the specific memory cell (eg, MC31 adjacent to the DST) is lower than the threshold voltage Vt of the other memory cells MC0 to MC30, thereby widening the threshold voltage distribution in the chip of the NAND flash memory device. As a result, the performance of the NAND flash memory device is reduced.

An object of the present invention is to provide a NAND flash memory device that compensates for program threshold voltages of memory cells connected to a last word line closest to a drain select line.

According to a preferred embodiment of the present invention for achieving the above object, a program method of a NAND flash memory device including a plurality of memory cells connected to each of the N (N is a natural number) word line, (a) the N Programming data into a first group of memory cells connected to the word line to which the program voltage is applied by applying a program voltage to one of the word lines; (b) verifying that data is normally programmed in the first group of memory cells; (c) if data is normally programmed in the first group of memory cells, determining whether a word line to which the program voltage is applied is an N-th word line corresponding to a last word line; (d) If the word line to which the program voltage is applied is the Nth word line, the first voltage of the first group connected to the Nth word line by adding the first positive voltage to the Nth word line is added to the program voltage. Reprogramming data into memory cells; And (e) after the program step (d), terminating all programs without returning to the program verifying step (b).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you. Like reference numerals in the drawings denote like members performing the same functions.

4 is a flowchart illustrating a program method of a NAND flash memory device according to a preferred embodiment of the present invention, and FIG. 5 is a diagram for describing an ISPP program method. In FIG. 5, Tpw represents a pulse width, Tury represents a verify time, and Tpgm represents a total program time.

Hereinafter, a program method of narrowing the program threshold voltage distribution of the general NAND flash memory cell shown in FIG. 1 to make the program speed uniform will be described with reference to FIGS. 4 and 5.

First, for example, 15.5 V is applied to the first word line WL0 as a program bias to program data in the memory cells MC0 in the selected string (S21).

Next, it is verified whether data is normally programmed into the memory cells MC0 (S22). At this time, if the threshold voltage Vt of the programmed memory cells MC0 is smaller than the target threshold voltage Vt (S23), since 0.5V is added to the aforementioned program bias 15.5V since data is not normally programmed in the memory cells MC0 (S24). A program bias of 16V is applied to the word line WL0 to program data back into the memory cells MC0.

On the other hand, if the threshold voltage Vt of the programmed memory cell MC0 is greater than the target threshold voltage Vt (S23), since data is normally programmed in the memory cells MC0, the process proceeds to step S25 to determine whether the word line WL0 corresponds to the last word line WL31. . At this time, since the word line WL0 is not the last word line WL31, the address is increased by +1 (S26), and a program bias is applied to the next word line WL1 to program data in the memory cells MC1 in the selected string. In the same manner as described above, the program operation is performed up to the memory cell MC30.

Finally, for example, 15.5 V is applied to the word line WL31 as a program bias to program data in the memory cells MC31 in the selected string.

Next, it is verified whether data is normally programmed in the memory cells MC31 (S22). At this time, if the threshold voltage Vt of the programmed memory cell MC31 is smaller than the target threshold voltage Vt (S23), since data is not normally programmed in the memory cells MC31, 0.5V is added to the aforementioned program bias 15.5V (S24). The program bias of 16V is applied to the word line WL31 to program data into the memory cell MC31 again.

On the other hand, if the threshold voltage Vt of the programmed memory cells MC31 is greater than the target threshold voltage Vt (S23), since data is normally programmed in the memory cells MC31, the process proceeds to step S25 to determine whether the word line WL31 corresponds to the last word line WL31. . At this time, since the word line WL31 is the last word line WL31, the process proceeds to step S27 to apply the program bias, for example, 16.5V, which is equal to 0.5V to 16V to the word line WL31, and re-programs the memory cell MC31. Here, after the program operation on the memory cells MC31 connected to the last word line WL31, the program operation is terminated without program verification.

As shown in FIG. 4, the reason for programming the memory cells MC31 unconditionally by adding 0.5V to the program voltage without program verification is to increase the program speed by increasing the threshold voltage Vt of the memory cells MC31 connected to the last word line WL31. .

When the memory cell MC31 is programmed by adding + 0.5V to the program bias without the program verifying operation to the word line WL31 closest to the drain select line DSL, the threshold voltage Vt of the memory cell MC31 is increased, resulting in an overall threshold voltage distribution. Narrows. In this case, the program rates of these memory cells MC31 are similar to those of other memory cells MC0 to MC30.

The present invention is more effective when the number of memory cells in the cell string is increased.

In addition, although the present invention has been described only for flash memory devices of single-level cells, the present invention is further described in flash memory devices of multi-level cells that use faster program speeds and narrower program threshold voltage distributions. effective.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the threshold voltage distribution of the memory cells connected to the last word line adjacent to the drain select line may be higher than in the related art, thereby narrowing the program threshold voltage distribution. As a result, the performance of the NAND flash memory device can be improved.

Claims (4)

A program method of a NAND flash memory device including a plurality of memory cells connected to each of N word lines, wherein N is a natural number. (a) programming data into a first group of memory cells connected to the word line to which the program voltage is applied by applying a program voltage to one of the N word lines; (b) verifying that data is normally programmed in the first group of memory cells; (c) if data is normally programmed in the first group of memory cells, determining whether a word line to which the program voltage is applied is an N-th word line corresponding to a last word line; (d) If the word line to which the program voltage is applied is the Nth word line, the first voltage of the first group connected to the Nth word line by adding the first positive voltage to the Nth word line is added to the program voltage. Reprogramming data into memory cells; And (e) after the program step (d), ending all programs without returning to the program verifying step (b). The method of claim 1, If data is not normally programmed in the first group of memory cells, reprogramming the first group of memory cells by adding the first positive voltage to the program voltage and reapplying the word line. Program method of a NAND flash memory device, characterized in that. The method of claim 1, If the word line to which the program voltage is applied is not the N-th word line, steps (a) to (c) are repeatedly performed until the N-th word line is sequentially increased by one address. Program method of NAND flash memory device. The method according to claim 1 or 2, And the first positive voltage is 0.5V.

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