KR20100013950A - Flash memory device and method for programming thereof - Google Patents

Flash memory device and method for programming thereof Download PDF

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Publication number
KR20100013950A
KR20100013950A KR1020080075714A KR20080075714A KR20100013950A KR 20100013950 A KR20100013950 A KR 20100013950A KR 1020080075714 A KR1020080075714 A KR 1020080075714A KR 20080075714 A KR20080075714 A KR 20080075714A KR 20100013950 A KR20100013950 A KR 20100013950A
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KR
South Korea
Prior art keywords
voltage
bit line
applying
line
drain select
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KR1020080075714A
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Korean (ko)
Inventor
김기환
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080075714A priority Critical patent/KR20100013950A/en
Publication of KR20100013950A publication Critical patent/KR20100013950A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a program method thereof, wherein the drain select transistor, memory cells, and source select transistor connected between the bit line and the common source line are selected by respective drain select lines, word lines, and source select lines. And a second voltage higher than a first voltage applied when programming other memory cells during a program operation of the memory cell adjacent to the drain select transistor. A voltage generator for applying a drain selection line, a page buffer for applying a third voltage to the bit line or detecting a voltage change of the bit line, and programming other memory cells during a program operation of a memory cell adjacent to the drain select transistor. When program gold Due to a fifth voltage higher than the fourth voltage applied to the bit line voltage controller for applying to the bit line in order, it is possible to further implement a high performance flash memory device.

Description

Flash memory device and method for programming thereof

The present invention relates to a flash memory device and a program method thereof, and more particularly, to a NAND flash memory device and a program method thereof.

There is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that rewrites data at regular intervals. Here, the program refers to an operation of writing data to a memory cell. The NAND flash memory device of the nonvolatile memory device has a large capacity because a plurality of memory cells are connected in series to form a single cell string by sharing drains or sources between adjacent cells. There is an advantage that is suitable for storing information.

1 is a circuit diagram illustrating a cell string structure of a conventional NAND flash memory device 10.

Referring to FIG. 1, a power supply voltage VCC is applied to an unselected bit line BLe connected to a first cell string 11, and a ground voltage is applied to a selected bit line Blo connected to a second cell string 12. (0V) is applied. A power supply voltage VCC is applied to the drain select line DSL, and a ground voltage 0V is applied to the source select line SSL. The program voltage Vpgm (about 16-19V) is applied to the word line WL2, and the pass voltage Vpass (about 8V-10V) is applied to the remaining word lines WL0, WL1, and WL3-WL31. When the program voltage condition described above is reached, data is programmed in the memory cell MC2 '.

However, in the NAND type flash memory device 10 shown in FIG. 1, Vpgm disturb may occur during a program operation. The Vpgm disturb is a disturb that is received by the memory cell MC2 of the first cell string 11 whose gate is connected to the same word line WL2 as the cell MC2 'to be programmed. The Vpgm disturb refers to a phenomenon in which the memory cell MC2 is programmed when the difference between the voltage of the word line WL2 and the channel voltage of the memory cell MC2 is higher than the threshold voltage Vt of the memory cell MC2.

However, all of the channel voltages of the memory cells MC0-MC31 connected to the unselected bit lines BLe to which the power supply voltage VCC is applied are boosted to a voltage higher than the power supply voltage VCC, for example, 8V. Therefore, the phenomenon of being programmed in the memory cell MC2 can be prevented.

The reason why all the channel voltages of the memory cells MC0-MC31 connected to the unselected bit line BLe to which the power supply voltage VCC is applied is boosted is as follows. That is, when the power supply voltage VCC is applied to the unselected bit line BLe and the drain select transistor DST is turned on, VCC-Vt (Vt is the threshold voltage of DST) toward the channel of the memory cells MC0-MC31. Since voltage shift occurs, the channels of the memory cells MC0-MC31 are initially charged to VCC-Vt. When the program voltage Vpgm and the pass voltage Vpass are applied, the source voltage of the drain select transistor DST is increased due to channel boosting, and the drain select transistor DST is turned off without forming a channel. That is, tunnel oxide capacitance and ONO (Oxide Nitride Oxide) layer capacitance exist between the channel of the memory cells MC0-MC31 and the control gate CG, and depletion capacitance between the channel and the bulk substrate (Si-Sub). Is present. Thus, the channel voltages of the memory cells MC0-MC31 are boosted by the coupling of these three capacitances to rise to about 8V. For this reason, even when the program voltage Vpgm is applied to the gate, the program inhibiting cell MC2 connected to the unselected bit line BLe to which the power supply voltage Vcc is applied is not programmed.

However, since the degree of boosting the channel voltage of the memory cells MC0-MC31 connected to the unselected bit line BLe may vary according to various requirements, the actual boosted channel voltage is higher than the target boosting level of 8V. Or low. That is, when the actual boosted channel voltage is lower than the target boosting level due to charge sharing, the above-described Vpgm disturb may occur in a memory cell (for example, MC31) in which the channel voltage may be formed at the lowest. have.

In addition, when the actual boosted channel voltage is higher than the target boosting level, the memory cells adjacent to the drain select transistor DST or the source select transistor SST (for example, MC0 and MC31) may be caused by gate induced drain leakage (GIDL). Hot carrier injection (HCI) may cause hot carrier injection disturbances in which data is programmed to increase the threshold voltage. This is because the drain select transistor DST or the source select transistor SST is formed with a relatively low channel voltage or no channel voltage at all, so that a large channel voltage difference between adjacent drain cells is formed.

As such, the Vpgm disturb and hot carrier injection disturbances generated by the channel voltage formed higher or lower than the target boosting level have a high probability of being concentrated when the program voltage is applied to the memory cell MC31 adjacent to the drain select line DSL. high. Therefore, during the program operation, it is important to properly maintain the channel voltage of the memory cells of the unselected bit line BLe, particularly the memory cell MC31 adjacent to the drain select line DSL.

The present invention sets a target channel voltage at which the Vpgm disturb and the hot carrier injection disturb does not occur during a program operation, and then applies the target channel voltage to the drain of the memory cell adjacent to the drain select line among the memory cells of the unselected bit line during the program operation. By forcing, the channel voltage of the memory cell adjacent to the drain select line can be maintained at the target channel voltage.

A flash memory device according to an aspect of the present invention includes a drain select transistor, memory cells, and a source select transistor connected between a bit line and a common source line and selected by respective drain select lines, word lines, and source select lines. And applying a second operating voltage to the memory cell array and a second voltage higher than a first voltage applied when programming other memory cells during a program operation of a memory cell adjacent to the drain select transistor. When programming other memory cells in a program operation of a memory cell adjacent to the voltage generator and the page buffer for applying a third voltage to the bit line or detecting a voltage change of the bit line and the drain select transistor. 1st licensed for program ban And a bit line voltage controller configured to apply a fifth voltage higher than four voltages to the bit line.

The first voltage or the third voltage may be a power supply voltage. The second voltage and the fifth voltage may be the same voltage. The second voltage or the fifth voltage may be 8V. The voltage generator may generate voltages necessary for a program operation, a read operation, or an erase operation of the memory cells according to a program command signal, a read command signal, or an erase command signal. The voltage generator may output different voltages to a drain select line according to the word line selected by the address signal during a program operation. The voltage generator may apply one of a program voltage, a pass voltage, and a turn-off voltage lower than a pass voltage and higher than a ground voltage to the memory cell array. The third voltage may be a ground voltage or a power supply voltage. The bit line voltage controller may be connected between the page buffer and the bit line. The bit line voltage controller may apply different voltages to the bit lines when a program operation of a word line adjacent to the drain select line is performed according to an address signal.

According to another aspect of the present invention, a method of programming a flash memory device includes applying a ground voltage to a selected bit line, applying a first voltage to an unselected bit line, and applying a second voltage to a drain select line; Performing a first program operation by applying a program voltage to a selected word line and applying a pass voltage to remaining word lines after applying the second voltage, applying a ground voltage to the selected bit line, Applying a third voltage higher than the first voltage to the selected bit line, applying a fourth voltage higher than the second voltage to the drain selection line, and applying the fourth voltage to be adjacent to the drain selection line. A program voltage is applied to one word line, and a pass voltage is applied to the other word lines, thereby providing a second program movement. Characterized in that it comprises the step of conducting.

The first voltage and the second voltage may be the same voltage. The first voltage or the second voltage may be a power supply voltage. The third voltage and the fourth voltage may be the same voltage. The third voltage and the fourth voltage may be 8V. A turn-off voltage lower than the pass voltage and higher than the ground voltage may be applied to the word line adjacent to the word line applying the pass voltage. The second program operation may be performed after the first program operation.

According to the flash memory device of the present invention and a program method thereof, the channel voltage of the memory cell adjacent to the drain select line among the memory cells of the unselected bit line can be maintained at an appropriate target channel voltage. As a result, Vpgm disturb and hot carrier injection disturb can be prevented from occurring in the memory cell adjacent to the drain select line among the memory cells of the unselected bit line, which may degrade the characteristics of the flash memory device during the program operation. High performance flash memory devices can be implemented.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2 is a block diagram illustrating a NAND flash memory device including a bit line voltage controller according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a NAND flash memory device may include a memory cell block 110, a row decoder 120, a block select switch 122, a voltage generator 130, a bit line voltage controller 140, and a page buffer. And 150.

The memory cell block 110 includes a plurality of cell strings 111a and 111b. The cell strings 111a and 111b include memory cells MC0 to MCn-1 or MC0 'to MCn-1', a source select transistor SST or SST ', and a drain select transistor DST or DST', respectively. The memory cells MC0 to MCn-1 or MC0 'to MCn-1' are connected in series between the source select transistor SST or SST 'and the drain select transistor DST or DST'. In FIG. 2, two strings 111a and 111b are present in the memory cell block 110, but a plurality of strings are present.

Each bit line BLe and BLo is connected to a drain of the drain select transistor DST or DST 'included in each cell string. BLe represents an even bit line and BLo represents an odd bit line. In one embodiment of the present invention, BLe represents an unselected bit line during a program operation and BLo represents a selected bit line during a program operation. The common source line CSL is connected in common with the sources of the source select transistors SST or SST 'included in different cell strings.

Memory cells (eg, MC0 and MC0 ') having control gates connected to each other and sharing one word line (eg, WL0) are controlled by the corresponding word line (eg, WL0) and constitute one page. In FIG. 2, there are n pages. The number of memory cells MC0 to MCn-1 or MC0 'to MCn-1' connected in series between the drain select transistor DST or DST 'and the source select transistor SST or SST', that is, the word lines The number of WL0 to WLn-1) may exist as 16, 32, 64, etc. in consideration of the device and density.

The block select switch 122 transfers the operating voltages output from the voltage generator 130 to the memory cell block selected according to the block select signal BSELi output from the row decoder 102. That is, the block select switch 122 may select the global lines GDSL, GWL0 to GWLn-1, and GSSL according to the block select signal BSELi output from the row decoder 120 to select local lines of the memory cell block. DSL, WL0 to WLn-1, SSL).

The block select switch 122 is composed of a plurality of pass transistors T0 to Tn + 1 having gates connected to each other. The pass transistors T0 to Tn + 1 are composed of NMOS transistors. In response to the block select signal BSELi of the row decoder 120, the block select switch unit 122 assigns the respective word lines WL0 to WLn-1 to the corresponding global word lines GWL0 to GWLn. -1), a drain select line DSL to a global drain select line GDSL, and a source select line SSL to a global source select line GSSL.

The voltage generator 130 generates the voltages necessary for the program operation, the read operation, or the erase operation of the memory cells according to the program command signal PGM, the read command signal READ, or the erase command signal ERASE, and thus the global drain select line. And output to the GDSL, the global word lines GWL0 to GWLn-1, and the global source select line GSSL. In particular, the voltage generator 130 may apply a voltage output to the global drain select line GDSL such that different voltages are applied to the drain select line DSL according to a word line selected by the address signal ADD during a program operation. Adjust. For example, the voltage generator 130 may apply the global drain such that the power supply voltage VCC is applied to the drain select line DSL when the program operation of the word line WLn-1 adjacent to the drain select line DSL is performed. The operating voltage is output to the selection line GDSL.

The page buffer 150 outputs a voltage corresponding to data stored in the memory cells during a program operation and applies the voltage to the bit line BLe or BLo, and changes the bit line BLe or BLo according to the data stored in the memory cell during a read operation. To detect the voltage. The page buffer 150 may supply a power supply voltage VCC or a ground voltage to the bit line BLe or BLo when a program operation of the word lines WL0 to WLn-2 not adjacent to the drain select line DSL is performed. 0 V) is applied. The power supply voltage VCC corresponds to a program inhibit voltage for preventing a memory cell from being programmed during a program operation. When programming a memory cell, the ground voltage 0V is applied to the bit line BLe or BLo regardless of the selected word line.

The bit line voltage controller 140 is connected between the bit line BLe or BLo and the page buffer 150 and programs the word line WLn-1 adjacent to the drain select line DSL according to the address signal ADD. When the operation is performed, a voltage (for example, 8V) or a ground voltage (0V) higher than the power supply precursor VCC is applied to the bit line BLe or BLo. The voltage higher than the power supply voltage VCC corresponds to a program prohibition voltage for preventing a memory cell from being programmed during a program operation. When programming a memory cell, the ground voltage 0V is applied to the bit line BLe or BLo regardless of the selected word line.

Referring to the NAND flash memory device of the present invention described above, a program method of the NAND flash memory device according to an embodiment of the present invention will be described in detail as follows. The program method described below may be applied to a program method of an ISPP method or a program method implemented in an MLC element.

For example, when programming any one of the memory cells MC0 'to MCn-2' connected to a word line that is not adjacent to the drain select line DSL, the row decoder 120 may perform a program operation. The memory cell block 110 receives the address of the memory cell block 110 to output the high level block selection signal BSELi. The block select signal BSELi activates the block select switch 122 to turn on the plurality of pass transistors To to Tn + 1 included in the memory cell block 110. Accordingly, each of the word lines WL0 to WLn-1 included in the memory cell block 110 is connected to the global word lines GWL0 to GWLn-1 corresponding to the word lines WL0 to WLn-1 and the drain select line DSL. Is connected to the global drain select line GDSL, and the source select line SSL is connected to the global source select line GSSL.

The bit line voltage unit 140 and the page buffer 150 receive the address of the selected bit line BLo or the unselected bit line BLe, and apply the ground voltage Ob to the selected bit line BLo. The power supply voltage VCC is applied to the selected bit line BLe.

The voltage generator 130 applies a ground voltage 0V to the source select line SSL and a power supply voltage VCC to the common source line CSL. In addition, the voltage generator 150 receives an address of a word line to which a memory cell (one of MC0 'to MCn-2') to which a program operation is to be connected, applies a program voltage Vpgm to the word line. In addition, a pass voltage Vpass lower than the program voltage Vpgm is applied to word lines adjacent to the word line. In addition, a turn-off voltage Viso may be applied to word lines adjacent to the word line to which the pass voltage Vpass is applied to turn off the memory cells connected to the word line and the gate. Turn-off voltage (Viso) is a voltage range higher than the ground voltage (0V) and lower than the pass voltage (Vpass). In this case, the memory cells to which the program inhibit voltage Vpass is applied and the memory cells to which the program voltage Vpgm is applied are among the memory cells belonging to the first string 111a connected to the unselected bit line BLe. The channel voltage may increase because (Viso) is applied and turned off to be isolated and partially local channel boost due to a memory cell that does not form a channel voltage.

On the other hand, when programming the memory cell MCn-1 'connected to the word line WLn-1 adjacent to the drain select line DSL among the word lines, the voltage is applied to the drain select line DSL among the above-described voltages. The voltage and the voltage applied to the unselected bit line BLe are changed. In detail, first, when a higher target voltage (for example, 8V) is applied to the unselected bit line BLe in the bit line voltage controller 140 instead of the power supply voltage VCC and the drain select transistor DST is turned on. The channel of the memory cell MCn-1 is initially charged to 8V-Vt (Vt is a threshold voltage of the drain select transistor). When the program voltage Vpgm or the program pass voltage Vpass is applied to the memory cell MCn-1 ′ by the voltage generator 130, a channel boosting phenomenon occurs in the channel region of the memory cell MCn-1 ′. This occurs to increase the channel voltage of the memory cell MCn-1 '. The drain line transistor DST is turned off by the voltage difference between the gate and the source.

On the other hand, since the turn-off voltage Viso is applied and the channels are not formed, the memory cells are not affected by the channel voltage of the memory cell MCn-1 '.

8V-Vt, which is the channel voltage of the memory cell MCn-1, is a channel voltage that can prevent the occurrence of Vpgm disturb or hot carrier injection disturbance in the memory cell MCn-1 during a program operation. The voltage condition may vary depending on the operating voltages being used. That is, the present invention is forcibly forcing the channel voltage of the memory cell MCn-1 of the unselected bit line BLe, which is most vulnerable to Vpgm disturb or hot carrier injection disturb, so that the Vpgm disturb or hot carrier injection disturb can be suppressed. Ensure that the channel voltage does not occur.

The drain select transistors DST or DST 'included in the memory cell block 110 are applied with a target voltage higher than the power supply voltage VCC in addition to the ground voltage 0V or the power supply voltage VCC. Therefore, it is preferable that the drain select transistors DST or DST 'form a thicker thickness of the tunnel insulating film than the conventional drain select transistors so as to withstand high voltage.

3 is a graph illustrating a fail rate according to a pass voltage Vpass applied to a predetermined cell string.

In the case of the cell string shown in FIG. 3, when the pass voltage Vpass is lower than the first voltage V1, Vpgm disturb may occur. When the pass voltage Vpass is higher than the second voltage V2, the hot carrier injection disturb may occur. May occur. Accordingly, the pass voltage Vpass of the cell string may be selected as a value between the first voltage V1 and the second voltage V2. In addition, when a pass voltage Vpass value selected for the predetermined cell string is selected, the channel voltage of the memory cell in which disturbances may not occur in the cell string may also be selected.

1 is a circuit diagram illustrating a cell string structure of a conventional NAND flash memory device 10.

2 is a block diagram illustrating a NAND flash memory device including a bit line voltage controller according to an exemplary embodiment of the present invention.

3 is a graph illustrating a fail rate according to a pass voltage applied to a predetermined cell string.

<Description of the symbols for the main parts of the drawings>

110: memory cell block 120: row decoder

122: block selection switch unit 130: voltage generator

140: bit line voltage control unit 150: page buffer

Claims (17)

A memory cell array coupled between the bit line and the common source line and including a drain select transistor, memory cells and a source select transistor selected by respective drain select lines, word lines and source select lines; Generates a voltage that applies operating voltages to the memory cell array and applies a second voltage higher than a first voltage applied when programming other memory cells during a program operation of a memory cell adjacent to the drain select transistor to the drain select line. part; A page buffer applying a third voltage to the bit line or detecting a change in voltage of the bit line; And And a bit line voltage controller configured to apply a fifth voltage higher than a fourth voltage applied for prohibition of the program to the bit line when programming other memory cells during a program operation of a memory cell adjacent to the drain select transistor. . The method of claim 1, And the first voltage or the third voltage is a power supply voltage. The method of claim 1, And the second voltage and the fifth voltage are the same voltage. The method of claim 3, And the second voltage or the fifth voltage is 8V. The method of claim 1, And the voltage generator generates voltages necessary for a program operation, a read operation, or an erase operation of the memory cells according to a program command signal, a read command signal, or an erase command signal. The method of claim 1, And the voltage generator outputs different voltages to drain select lines according to the word lines selected by the address signal during a program operation. The method of claim 1, And the voltage generator applies one of a program voltage, a pass voltage, and a turn-off voltage lower than a pass voltage and higher than a ground voltage to the memory cell array. The method of claim 1, And the third voltage is a ground voltage or a power supply voltage. The method of claim 1, And the bit line voltage controller is connected between the page buffer and the bit line. The method of claim 1, And the bit line voltage controller applies different voltages to bit lines when a program operation of a word line adjacent to a drain select line is performed according to an address signal. Applying a ground voltage to the selected bit line, applying a first voltage to the unselected bit line, and applying a second voltage to the drain select line; Performing a first program operation by applying a program voltage to a selected word line and applying a pass voltage to remaining word lines after applying the second voltage; Applying a ground voltage to the selected bit line, applying a third voltage higher than the first voltage to the unselected bit line, and applying a fourth voltage higher than the second voltage to the drain select line; And And applying a program voltage to a word line adjacent to the drain select line and applying a pass voltage to the remaining word lines after applying the fourth voltage to perform a second program operation. The method of claim 11, And the first voltage and the second voltage are the same voltage. The method of claim 11, And the first voltage or the second voltage is a power supply voltage. The method of claim 11, And the third voltage and the fourth voltage are the same voltage. The method of claim 11, And the third voltage and the fourth voltage are 8V. The method of claim 11, And applying a turn-off voltage lower than the pass voltage and higher than a ground voltage to a word line adjacent to the word line applying the pass voltage. The method of claim 11, And executing the second program operation after the first program operation.
KR1020080075714A 2008-08-01 2008-08-01 Flash memory device and method for programming thereof KR20100013950A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10714184B2 (en) 2018-02-28 2020-07-14 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11152074B2 (en) 2018-02-28 2021-10-19 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11217311B2 (en) 2018-02-28 2022-01-04 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11600322B2 (en) 2020-10-12 2023-03-07 SK Hynix Inc. Semiconductor memory device and method of operating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10714184B2 (en) 2018-02-28 2020-07-14 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11152074B2 (en) 2018-02-28 2021-10-19 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11217311B2 (en) 2018-02-28 2022-01-04 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11600331B2 (en) 2018-02-28 2023-03-07 Samsung Electronics Co., Ltd. Memory device with improved program performance and method of operating the same
US11600322B2 (en) 2020-10-12 2023-03-07 SK Hynix Inc. Semiconductor memory device and method of operating the same

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