KR20130006299A

KR20130006299A - Operating method of semiconductor device

Info

Publication number: KR20130006299A
Application number: KR1020120068537A
Authority: KR
Inventors: 세이이치 아리토메
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2011-07-06
Filing date: 2012-06-26
Publication date: 2013-01-16

Abstract

PURPOSE: A method for operating a semiconductor device is provided to prevent a leakage in an unselected memory cell by constantly maintaining a gradually rising program voltage after the program voltage reaches approaches a specific level. CONSTITUTION: Selected memory cells are programmed by applying a gradually rising first program voltage(Vpgm1) to a selected word line and a first pass voltage(Vpass1) to unselected word lines. The selected memory cells are programmed by applying a second program voltage(Vpgm2) to the selected word line and a gradually rising second pass voltage(Vpass2) to first unselected word lines near the selected word line if a voltage difference between the first program voltage and the first pass voltage reaches a critical dimension. [Reference numerals] (AA) Voltage; (BB) Critical dimension; (CC) Rest of WL; (DD) Number of program pulse application

Description

Operating method of semiconductor device

The present invention relates to a method of operating a semiconductor device, and more particularly to a program method.

The semiconductor device includes a memory cell array in which data is stored. The memory cell array consists of a plurality of cell blocks, each cell block consisting of a plurality of cell strings. The cell strings have the same structure, and one cell string will be described in detail as follows.

1 is a cross-sectional view of a cell string for explaining a problem according to the prior art.

Referring to FIG. 1, a cell string includes a plurality of memory cells and switch transistors formed on the semiconductor substrate 10. For example, a plurality of memory cells are formed between a drain select transistor and a source select transistor, and a junction region 11 is formed in the semiconductor substrate 10 between the transistors and the memory cells. The switch drain and source select transistors include a gate insulating film 12 and a gate electrode 14 sequentially stacked on the semiconductor substrate 10. Each memory cell includes a gate insulating film 12, a floating gate 16, a dielectric film 17, and a control gate 18 sequentially stacked on the semiconductor substrate 10. The gate insulating film 12 is formed of an insulating material such as an oxide film, and the dielectric film 17 is formed of a stacked structure of an oxide film, a nitride film, and an oxide film or is formed of a high dielectric material. The floating gate 16, the control gate 18, and the gate electrode 14 are formed of a conductive material such as polysilicon. Drain select transistors formed in different cell strings are connected to a drain select line DSL, source select transistors are connected to a source select line SSL, and memory cells are word lines WLn-k to WLn + k. Is connected to.

A method of programming a semiconductor memory device using the cell string described above is as follows.

1 and 2, in a state where a program allowance voltage (eg, a ground voltage) is applied to a channel of a selected cell string, a program voltage Vpgm is applied to a selected word line WLn connected to the selected memory cell. Is applied, and a pass voltage Vpass is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. When the program voltage Vpgm is applied to the selected word line WLn, the potential of the floating gate 16 is increased due to the coupling between the control gate 18 and the floating gate 16. As a result, electrons of the semiconductor substrate 10 flow into the floating gate 16 through the gate insulating layer 12 by a tunneling phenomenon. An operation of introducing electrons into the floating gate 16 is called a program operation, and an operation of pulling electrons introduced into the floating gate 16 into the semiconductor substrate 10 is called an erase operation.

Recently, multi-level cells (MLCs), which can program one memory cell at various levels, are mainly used. Since one memory cell must be programmed at various levels, the threshold voltage distribution should be narrow. do. To this end, an ISPP (incremental step pulse program) type program operation is performed.

In the ISPP program operation, the program voltage Vpgm is applied to the selected word line WLn, and the pass voltage is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. Vpass) is applied. In general, the pass voltage Vpass has a level lower than the program voltage Vpgm. In detail, the program voltage Vpgm having a low level is applied at the beginning of the program, and as the number of times the program voltage Vpgm is applied increases, the program voltage Vpgm is increased by the step voltage. After the program voltage Vpgm and the pass voltage Vpass are applied, a verification operation for determining whether the threshold voltage of the selected memory cell reaches the target voltage is performed. As a result of the verification operation, if the threshold voltage of the selected memory cell does not reach the target voltage, the program voltage Vpgm and the path are gradually increased while increasing the program voltage Vpgm by the step voltage until the target voltage is reached. The program operation and the verify operation of applying the voltage Vpass are repeated. When the threshold voltage reaches the target voltage, the program operation ends.

While performing the program operation, the program voltage Vpgm gradually increases, while the unselected word lines WLn-1 through WLn-k and WLn + 1 through WLn + k have a constant level of pass voltage Vpass ( 1)), the level difference between the program voltage Vpgm and the pass voltage Vpass (1) gradually increases. Alternatively, the pass voltage Vpass (2) may be applied to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k while the program is being executed. At this time, the pass voltage Vpass (2) increases to a level lower than the level at which the program voltage Vpgm increases. That is, the step up level of the pass voltage Vpass (2) is lower than the step up level of the program voltage Vpgm.

In the case of non-selected memory cells adjacent to the selected memory cell, when the program voltage Vpgm applied to the selected word line WLn becomes higher than a specific level, it may be programmed under the influence of the increased program voltage Vpgm. That is, when the program voltage Vpgm gradually rises and reaches the critical voltage difference CD between the program voltage Vpgm and the pass voltage Vpass, the unselected memory cells 12 and the selected memory cell ( 11) Liver breakdown (BD) may occur. In addition, electrons trapped in the floating gates of the unselected memory cells 12 may exit in the control gate direction of the selected memory cells 12, thereby lowering the threshold voltages of the unselected memory cells 12. As described above, when the program voltage Vpgm applied to the selected word line WLn gradually increases during the program operation and the voltage difference with the pass voltage Vpgm reaches the threshold CD, the selected memory cell and the adjacent memory cell are adjacent to the selected memory cell. Since the threshold voltages of the memory cells may vary, the reliability of the program operation may be reduced.

The problem to be solved by the present invention is to prevent the threshold voltages of the non-selected memory cells adjacent to the selected memory cell from being lowered by preventing the difference between the program voltage and the pass voltage from being higher than the threshold value during the program operation.

In addition, it is intended to prevent the leakage that may occur in an unselected memory cell by maintaining a program voltage that gradually rises after reaching a certain level.

According to an embodiment of the present disclosure, a method of operating a semiconductor device may include applying a first program voltage that gradually increases to a selected word line and applying a constant first pass voltage to remaining non-selected word lines, thereby selecting the selected memory cells. Programming; And when a voltage difference between the first program voltage and the first pass voltage reaches a threshold value, applies a constant second program voltage to the selected word line, and gradually applies the first unselected word lines adjacent to the selected word line. Programming the selected memory cells while applying a rising second pass voltage.

When the second pass voltage is applied to the first unselected word lines, the potential of the second unselected word lines adjacent to the first unselected word lines is lowered by the threshold value than the first pass voltage; The method may further include performing a program operation while applying a three pass voltage.

The third pass voltage gradually increases in proportion to the pass voltage.

When the second pass voltage is applied to the first non-selected word lines, applying a fourth pass voltage gradually lowered to second non-selected word lines adjacent to the first non-selected word lines; And applying a fifth pass voltage gradually increasing in proportion to the second pass voltage to second unselected word lines when the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold. It includes more.

When the fifth pass voltage is applied to the second non-selected word lines, applying a sixth pass voltage gradually lowered to third non-selected word lines adjacent to the second non-selected word lines, respectively. ; And applying a seventh pass voltage to the second non-selected word lines when the voltage difference between the sixth pass voltage and the first pass voltage reaches the threshold.

A fourth pass voltage gradually lowered to second and third unselected word lines sequentially adjacent to the first non-selected word lines when the second pass voltage is applied to the first unselected word lines; Applying a; And when the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, a fifth pass voltage gradually increasing in proportion to the second pass voltage is applied to the second unselected word lines, The third unselected word lines may further include applying the fourth pass voltage until the voltage difference with the first pass voltage reaches the threshold.

When the voltage difference between the fourth pass voltage applied to the third unselected word lines and the first pass voltage reaches the threshold, a constant eighth pass voltage is applied to the second unselected word lines.

According to another exemplary embodiment of the present disclosure, a method of operating a semiconductor device may include applying a first program voltage gradually increasing by a first step voltage to selected word lines, and lowering the first program voltage to remaining unselected word lines. Programming selected memory cells connected to the selected word line by applying a ninth pass voltage gradually rising to a level; And while programming the selected memory cells, if a voltage difference between the first program voltage and the ninth pass voltage reaches a threshold, a constant second program voltage is applied to the selected word line and is adjacent to the selected word line. Programming the selected memory cells while applying a second pass voltage that gradually increases by the first step voltage to first unselected word lines.

When the second pass voltage is applied to the first unselected word lines, the potential of the second unselected word lines adjacent to the first unselected word lines is lowered by the threshold value than the ninth pass voltage; The step of applying a three-pass voltage further.

The third pass voltage gradually increases in proportion to the second pass voltage.

When applying the second pass voltage to the first unselected word lines, applying a fourth pass voltage that is gradually lowered to the second unselected word lines adjacent to the first unselected word lines, respectively. ; And applying a fifth pass voltage gradually increasing in proportion to the second pass voltage to second unselected word lines when the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold. It includes more.

When the fifth pass voltage is applied to the second non-selected word lines, applying a sixth pass voltage gradually lowered to third non-selected word lines adjacent to the second non-selected word lines, respectively. ; And applying a tenth pass voltage gradually rising in proportion to the ninth pass voltage to the third unselected word lines when the voltage difference between the sixth pass voltage and the ninth pass voltage reaches the threshold. It further includes.

A fourth pass voltage gradually lowered to second and third unselected word lines sequentially adjacent to the first non-selected word lines when the second pass voltage is applied to the first unselected word lines; Applying a; And when the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, a fifth pass voltage gradually increasing in proportion to the second pass voltage is applied to the second unselected word lines, And further applying the fourth pass voltage to third non-selected word lines until the voltage difference with the ninth pass voltage reaches the threshold.

When the voltage difference between the fourth pass voltage and the ninth pass voltage applied to the third unselected word lines reaches the threshold, the third unselected word lines are gradually increased in proportion to the ninth pass voltage. A rising eleventh pass voltage is applied.

The present invention can prevent the threshold voltages of unselected memory cells adjacent to the selected memory cell from being lowered during the program operation, and can improve the reliability of the semiconductor device. In addition, by keeping the level of the gradually rising program voltage constant after reaching a certain level, it is possible to prevent leakage that may occur in the selected memory cell.

1 is a cross-sectional view of a cell string for explaining a problem according to the prior art.
2 is a graph illustrating a program method according to the prior art.
3 is a block diagram illustrating a semiconductor device.
4 is a graph illustrating a program method according to a first embodiment of the present invention.
5 is a graph illustrating a program method according to a second embodiment of the present invention.
6 is a graph illustrating a program method according to a third embodiment of the present invention.
7 is a graph illustrating a program method according to a fourth embodiment of the present invention.
8 is a graph illustrating a program method according to a fifth embodiment of the present invention.
9 is a graph illustrating a program method according to a sixth embodiment of the present invention.
10 is a graph illustrating a program method according to a seventh embodiment of the present invention.
11 is a graph illustrating a program method according to an eighth embodiment of the present invention.
12 is a graph illustrating a program method according to a ninth embodiment of the present invention.
13 is a graph for explaining a program method according to a tenth embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

3 is a block diagram illustrating a semiconductor device.

Referring to FIG. 3, a semiconductor device may include a memory cell array 110, a circuit group 130, 140, 150, and 160 configured to perform a program operation, a read operation, or an erase operation of memory cells included in the memory cell array 110. Control circuit 120 configured to control circuit groups 130, 140, 150, 160, 170, 180, and 200 to set threshold voltage levels of selected memory cells according to input data. It includes.

In the case of the NAND flash memory device, the circuit group includes the voltage generation circuit 130, the row decoder 140, the page buffer group 150, the column selection circuit 160, the input / output circuit 170, and the pass / fail determination circuit 180. ) And a comparison circuit 200.

The memory cell array 110 includes a plurality of memory cells connected to word lines and bit lines. The memory cell array 110 will be described in detail as follows. The memory cell array 110 includes a plurality of cell blocks, one of which is shown in FIG. 3. Each cell block includes a plurality of cell strings ST. Some of the cell strings ST are designated as normal strings and some are designated as flag strings. Each cell string ST is configured identically to each other, and has a source select transistor SST connected to a common source line CSL, a plurality of memory cells Fn-k to Fn + k, and a bit line BLe or And a drain select transistor DST connected to BLo. The cells included in the flag string are called flag cells, but the structure is the same as the memory cells. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells Fn-k through Fn + k are connected to the word lines WLn-k through WLn + k, respectively. The gate of the drain select transistor DST is connected to the drain select line DSL. The cell strings ST are connected to bit lines BLe and BLo respectively corresponding to the cell strings ST, and are commonly connected to the common source line CSL.

The voltage supply circuits 130 and 140 may select the voltages required for the program operation, the read operation, or the erase operation of the memory cells according to the signals PGM, ERASE, READ, and RADD of the control circuit 120. (DSL), word lines WLn-1 to WLn + n, source select line SSL, and well. This voltage supply circuit includes a voltage generation circuit 130 and a row decoder 140.

The voltage generation circuit 130 outputs operation pulses for programming, reading, or erasing memory cells as global lines in response to the operation signals PGM, READ, and ERASE, which are internal command signals of the control circuit 120, When programming memory cells, operation pulses (eg, Vpgm, Vpass, or Vread) for the program are output as global lines. Vpgm is the program voltage, Vpass is the pass voltage, and Vread is the read pulse.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 may generate operation pulses generated by the voltage generation circuit 130 to local lines DSL, SSL, and WL [nk] of the selected cell block. : n + k]).

The comparison circuit 200 compares the program voltage Vpgm generated by the voltage generation circuit 130 and the pass voltage Vpass during a program operation, and, as a result of the comparison, between the program voltage Vpgm and the pass voltage Vpass. When the voltage difference is greater than or equal to the threshold, the threshold signal CV is output.

The page buffer group 150 detects a program state or an erase state of memory cells. The page buffer group 150 may include page buffers PB connected to the bit lines BLe and BLo, respectively, and may include memory cells in response to the page buffer signals PB SIGNALS output from the control circuit 120. Voltages necessary for storing data in Fn-k to Fn + k) are applied to the bit lines BLe and BLo, respectively. In detail, the page buffer group 150 may precharge the bit lines BLe and BLo during the program operation, the erase operation, or the read operation of the memory cells Fn-k to Fn + k, or the bit lines BLe and The data corresponding to the threshold voltage levels of the detected memory cells Fn-k to Fn + k is latched according to the voltage change of BLo. That is, the page buffer group 150 applies a program allowable voltage (eg, a ground voltage) or a program inhibit voltage (eg, a power supply voltage) to the bit lines BLe or BLo according to data input to the latch during a program operation. In the read operation, data stored in the memory cells Fn-k to Fn + k is adjusted by adjusting voltages of the bit lines BLe to BLo according to data stored in the memory cells Fn-k to Fn + k. Detect. In addition, the page buffer group 150 applies an erase permission voltage (eg, a power supply voltage) to the bit lines BLe and BLo at an initial stage of the erase operation, and erases the program buffer according to the erase verification result during the erase operation. A program permission voltage (eg, a ground voltage) is applied to bit lines connected to the strings ST.

The column select circuit 160 selects the page buffers PB included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. The latched data of the page buffer selected by the column select circuit 160 is output. In addition, the data output from the page buffer group 150 may be received through the column line CL, and may be transferred to the pass / fail determination circuit 180.

The input / output circuit 170 may input data DATA from the outside during the program operation to the page buffers PB of the page buffer group 150, respectively, to control the data DATA under the control of the control circuit 120. Transfer to column selection circuit 160. When the column selection circuit 160 transfers the transferred data to the page buffers of the page buffer group 150 in order, the page buffers store the input data in an internal latch. In addition, during the read operation, the input / output circuit 170 outputs data DATA transferred through the column select circuit 160 from the page buffers of the page buffer group 150 to the outside.

The pass / fail determination circuit 180 checks whether error cells are generated in the verify operation performed after the program or erase operation and outputs the result as a check signal PFC. In addition, the pass / fail determination circuit 180 counts the number of error cells generated when an error cell occurs and outputs a counting result as a counting signal CS. The control circuit 120 adjusts the level of the program voltage applied to the selected word line during the program operation of the memory cells, and allows the voltage generation circuit 130 to selectively apply the verify voltages applied to the selected word line during the program verify operation. ). In this case, the control circuit 120 may control the voltage generation circuit 130 according to the check signal CS of the pass / fail determination circuit 180.

The control circuit 120 internally outputs the program operation signal PGM, the read operation signal READ or the erase operation signal ERASE in response to the command signal CMD, and according to the type of operation, the page buffer group 150. Output page buffer signals PB SIGNALS for controlling the page buffers PB included in the " In addition, the control circuit 120 checks whether the threshold voltages of the selected memory cells have risen or decreased to a target level according to the check signal CS output from the pass / fail determination circuit 180 during a program or erase verify operation. It is determined whether to re-execute, complete, or fail the program or erase operation according to the result of the check.

In particular, when the threshold signal CV is applied during the program operation, the control circuit 120 adjusts the rising or falling level of the pass voltage Vpass generated by the voltage generating circuit 130. That is, in the program operation, when the voltage difference between the program voltage Vpgm generated by the voltage generation circuit 130 and the pass voltage Vpass reaches the threshold, the comparison circuit 200 outputs the threshold signal CV and controls the voltage. The circuit 120 causes the voltage generation circuit CV to generate a variable pass voltage Vpass in response to the threshold signal CV.

The program method using the above-described semiconductor device will be described below.

4 is a graph illustrating a program method according to a first embodiment of the present invention.

4 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. Pass voltages are applied to WLn-k and WLn + 1 to WLn + k). In the ISPP program operation, the first program voltage Vpgm1 is increased by the step voltage. In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is smaller than the critical voltage CD, so that the selected word line WLn connected to the selected memory cells Fn is progressive. The rising program voltage Vpgm is applied, and the first pass voltage Vpass1 having a fixed level is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. do. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not programmed. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

If the first first program voltage Vpgm1 applied to the selected word line WLn is 12V and the first pass voltage Vpass1 is 9V, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is Since it is 3V, it is lower than the threshold (CD). In this case, since the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn are not affected by the first program voltage Vpgm1, all of the unselected word lines WLn-1. To WLn + k and WLn + 1 to WLn + k, the first pass voltage Vpass1 is applied. That is, until the threshold voltages of the selected memory cells Fn do not reach the target voltage and the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 reaches the threshold CD, the first program The first program voltage Vpgm1 is gradually increased by a step voltage in proportion to the number of times of applying the voltage Vpgm1, and the first pass voltage Vpass1 is maintained at a constant level.

While executing the program while gradually applying the first program voltage Vpgm1 rising to the selected word line WLn, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 reaches the threshold value CD. After that, a second program voltage Vpgm2 having a constant level is applied instead of the first program voltage Vpgm1 applied to the selected word line WLn thereafter. That is, the second program voltage that is maintained constant without increasing the first program voltage Vpgm1 when the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 reaches the threshold CD. Apply (Vpgm2). Therefore, the second program voltage Vpgm2 does not have a step voltage.

When a constant second program voltage Vpgm2 is applied to the selected word line WLn, the threshold value CD is maintained between the selected word line WLn and the first unselected word lines WLn-1 and WLn + 1. In order to do this, the second pass voltage Vpass2 is gradually applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. While applying, the step up voltage of the second pass voltage Vpass2 is set equal to the step voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

In this case, the first fixed level of the remaining non-selected word lines WLn-2 to WLn-k and WLn + 2 to WLn + k except for the first non-selected word lines WLn-1 and WLn + 1. The pass voltage Vpass1 is continuously applied.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, the program voltage can be prevented from rising excessively, and the excessive voltage rise can be prevented, thereby preventing leakage between selected memory cells and unselected memory cells. can do. In addition, while the program voltage is fixed at a predetermined level, the selected memory cells are gradually increased by increasing a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn. It is possible to prevent a decrease in program efficiency.

5 is a graph illustrating a program method according to a second embodiment of the present invention.

5 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. In a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. Pass voltages are applied to WLn-k and WLn + 1 to WLn + k). In the ISPP program operation, the first program voltage Vpgm1 is increased by the step voltage. In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is smaller than the critical voltage CD, so that the selected word line WLn connected to the selected memory cells Fn is progressive. The rising program voltage Vpgm is applied, and the first pass voltage Vpass1 having a fixed level is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. do. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not erased. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

When the second program voltage Vpgm2 is applied to the selected word line WLn, the second program voltage Vpgm2 gradually rises to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. The second pass voltage Vpass2 is applied. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. When applied, it is possible to prevent a decrease in efficiency of program operation according to a second constant program voltage Vpgm2 and to lower threshold voltages of memory cells connected to the first unselected word lines WLn-1 and WLn + 1. Can be prevented. For example, the step up voltage of the second pass voltage Vpass2 may be set equal to the step voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

In particular, while applying the second pass voltage Vpass2 gradually rising to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1. ) And second non-selected memory cells Fn-2 and Fn + 2 adjacent to the first non-selected memory cells Fn-1 and Fn + 1 and the first non-selected memory cells Fn-1 and Fn + 1. Threshold voltage can be lowered. To prevent this, the threshold value (rather than the first pass voltage Vpass1) is applied to the second unselected word lines WLn-2 and WLn + 2 adjacent to the first unselected word lines WLn-1 and WLn + 1. The third pass voltage Vpass3 as low as CD) is applied. In this case, the remaining non-selected word lines WLn-3 to WLn− except for the first non-selected word lines WLn-1 and WLn + 1 and the second non-selected word lines WLn-2 and WLn + 2. The first pass voltage Vpass1 is continuously applied to k and WLn + 3 to WLn + k. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are prevented from being lowered due to the gradually rising second pass voltage Vpass2. For example, the level of the first pass voltage Vpass1 applied to the second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2, respectively, may be adjusted. After lowering by the threshold value CD, a third pass voltage Vpass3 gradually rising is applied. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 and the third pass voltage Vpass3 are gradually increased by 0.5V.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, it is possible to prevent the program voltage from excessively increasing, and by preventing excessive increase of the program voltage, it is possible to prevent leakage of unselected memory cells. have. In addition, while performing a program operation using a program voltage having a constant level, a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn is gradually applied. The increase may prevent the program efficiency of the selected memory cells from decreasing. In this case, the first and second ratios are applied to the second unselected word lines WLn-2 and WLn + 2 by applying a third pass voltage Vpass3 lower than the second pass voltage Vapss2 by a threshold value CD. It is possible to prevent the threshold voltages of the selected memory cells Fn-1, F-2, Fn + 1, and Fn + 2 from lowering.

6 is a graph illustrating a program method according to a third embodiment of the present invention.

6 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. Pass voltages are applied to WLn-k and WLn + 1 to WLn + k). In the ISPP program operation, the first program voltage Vpgm1 is increased by the step voltage. In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is smaller than the critical voltage CD, so that the selected word line WLn connected to the selected memory cells Fn is progressive. The rising program voltage Vpgm is applied, and the first pass voltage Vpass1 having a fixed level is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. do. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not erased. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

If the first first program voltage Vpgm1 applied to the selected word line WLn is 12V and the first pass voltage Vpass1 is 9V, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is Since it is 3V, it is lower than the threshold (CD). In this case, since the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn are not affected by the first program voltage Vpgm1, all of the unselected word lines WLn-1. To WLn + k and WLn + 1 to WLn + k, the first pass voltage Vpass1 is applied. That is, until the threshold voltages of the selected memory cells Fn do not reach the target voltage and the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 reaches the threshold CD, the first program In proportion to the number of times the voltage Vpgm1 is applied, the first program voltage Vpgm1 is gradually increased by a step voltage, and the first pass voltage Vpass1 is maintained at a constant level.

When a constant second program voltage Vpgm2 is applied to the selected word line WLn, program efficiency of selected memory cells connected to the selected word line WLn may be reduced. To compensate for this, the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. When applied, the efficiency of the program operation according to the second program voltage Vpgm2 which is influenced by the second pass voltage Vpass2 may be prevented. Preferably, the step up voltage of the second pass voltage Vpass2 may be set equal to the step voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

When the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1 are applied. A fourth pass voltage Vpass4 that is gradually lowered is applied to the adjacent second unselected word lines WLn-2 and WLn + 2. In this case, except for the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn and the second unselected word lines WLn-2 and WLn + 2 adjacent to the selected word line WLn. The first pass voltage Vpass1 having a constant level is continuously applied to the unselected word lines WLn-3 to WLn-k and WLn + 3 to WLn + k.

The fourth pass voltage Vpass4 is a voltage applied to the second unselected memory cells Fn-2 and Fn + 2 adjacent to the first unselected memory cells Fn-1 and Fn + 1, respectively. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are compensated for by the influence of the gradually increasing second pass voltage Vpass2. In order to do so, the fourth pass voltage (step down voltage) may be gradually lowered to the second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2. Vpass4) is applied. The fourth pass voltage Vpass4 will be described in detail as follows. In the selected memory cell, the maximum step of the fourth pass voltage Vpass4 when the coupling ratio of the word line connected to the selected memory cell is 0.6 and the coupling ratio of the word line connected to the adjacent memory cell is 0.15. The step down voltage is 0.5V × (0.6 / 0.15) = 2V. Therefore, the step-down voltage of the fourth pass voltage Vpass4 is preferably set in a range higher than the ground voltage 0V and lower than 2V.

Since the second pass voltage Vpass2 gradually increases by the step-up voltage, and the fourth pass voltage Vpass4 gradually decreases by the step-down voltage, the second pass voltage Vpass2 and the second pass voltage Vpass2 and the first pass voltage before the program operation is completed. The voltage difference between the four pass voltages Vpass4 may reach the threshold CD. When the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 reaches the threshold CD, the second unselected word lines WLn-2 and WLn + to which the fourth pass voltage Vpass4 is applied. A fifth pass voltage Vpass5 that gradually rises is applied to 2). That is, when the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 becomes too large above the threshold CD, the corresponding memory cells Fn-1 and the second pass voltage Vpass2 gradually increase. Since the threshold voltage of Fn + 1 may be lowered, a fifth pass voltage Vpass5 that gradually rises by the step-up voltage is applied to the second unselected word lines WLn-2 and WLn + 2 to compensate for this. Is authorized. When the second or fifth pass voltage Vpass2 or Vpass5 is applied to the first and second unselected word lines WLn-1, WLn-2, WLn + 1, and WLn + 2, the remaining unselected word lines The first pass voltage Vpass1 is continuously applied to the fields WLn-3 to WLn-k and WLn + 3 to WLn + k.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, an excessive increase in the program voltage may be prevented, thereby preventing leakage currents of the non-selected memory cells. In addition, while performing a program operation using a program voltage having a constant level, a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn is gradually applied. The increase may prevent the program efficiency of the selected memory cells from decreasing. In addition, by controlling the pass voltages applied to the second and third non-selection word lines WLn-2, WLn-3, WLn + 2 and WLn + 3, the first non-selection word lines WLn-1 and It is possible to prevent the threshold voltage change of the first to third unselected memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 due to the second pass voltage Vpass2 applied to WLn + 1. have.

7 is a graph illustrating a program method according to a fourth embodiment of the present invention.

Referring to FIGS. 7 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing the program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. Pass voltages are applied to WLn-k and WLn + 1 to WLn + k). In the ISPP program operation, the first program voltage Vpgm1 is increased by the step voltage. In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is smaller than the critical voltage CD, so that the selected word line WLn connected to the selected memory cells Fn is progressive. The rising program voltage Vpgm is applied, and the first pass voltage Vpass1 having a fixed level is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. do. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not erased. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

When the second program voltage Vpgm2 is applied to the selected word line WLn, the second program voltage Vpgm2 gradually rises to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. The second pass voltage Vpass2 is applied. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. When applied, the potentials of the selected memory cells increase under the influence of the second pass voltage Vpass2, thereby preventing a decrease in efficiency of the program operation according to the second program voltage Vpgm2. Preferably, the step up voltage of the second pass voltage Vpass2 may be set equal to the step voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

The fourth pass voltage Vpass4 is a voltage applied to the second unselected word lines WLn-2 and WLn + 2 adjacent to the first unselected word lines WLn-1 and WLn + 1, respectively. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are compensated for by the influence of the gradually increasing second pass voltage Vpass2. In order to do so, the fourth pass voltage (step down voltage) may be gradually lowered to the second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2. Vpass4) is applied. The fourth pass voltage Vpass4 will be described in detail as follows. In the selected memory cell, the maximum step of the fourth pass voltage Vpass4 when the coupling ratio of the word line connected to the selected memory cell is 0.6 and the coupling ratio of the word line connected to the adjacent memory cell is 0.15. The step down voltage is 0.5V × (0.6 / 0.15) = 2V. Therefore, the step-down voltage of the fourth pass voltage Vpass4 is preferably set in a range higher than the ground voltage 0V and lower than 2V.

Since the second pass voltage Vpass2 gradually increases and the fourth pass voltage Vpass4 gradually decreases, the voltage between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 before the program operation is completed. The difference may reach the threshold CD. At this time, the fifth pass voltage Vpass5 gradually increases to the second unselected word lines WLn-2 and WLn + 2 to which the fourth pass voltage Vpass4 is applied, and the second non-selected word is applied. The sixth pass voltage Vpass6 that is gradually lowered is applied to the third unselected word lines WLn-3 and WLn + 3 adjacent to the lines WLn-2 and WLn + 2. That is, when the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 becomes too large above the threshold CD, the first non-selected memory cells Fn by the gradually increasing second pass voltage Vpass2. Since the threshold voltages of −1 and Fn + 1 may be lowered, a fifth pass voltage Vpass5 gradually applied to the second unselected word lines WLn-2 and WLn + 2 may be applied to prevent the threshold voltages of −1 and Fn + 1. will be. Second, fifth, or sixth pass voltages on the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 sequentially adjacent to the selected word line WLn. When applying Vpass2, Vpass5 or Vpass6, the fixed first pass voltage Vpass1 is continuously applied to the remaining unselected word lines WLn-4 to WLn-k and WLn + 4 to WLn + k.

When the sixth pass voltage Vpass6 gradually decreases to the third unselected word lines WLn-3 and WLn + 3, a voltage between the sixth pass voltage Vpass6 and the first pass voltage Vpass1 is applied. The difference may reach the threshold CD. At this time, in order to prevent the voltage difference between the third unselected word lines WLn-3 and WLn + 3 and the fourth word lines WLn-4 and WLn + 4 from increasing further, the sixth pass voltage ( The fixed seventh pass voltage Vpass7 is applied to the third unselected word lines WLn-3 and WLn + 3 having a lower potential.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, it is possible to prevent the program voltage from excessively increasing, and by preventing excessive increase of the program voltage, it is possible to prevent leakage of unselected memory cells. have. In addition, by adjusting the pass voltages applied to the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 adjacent to the selected word line WLn, the selected memory cell ( During the program operation of Fn, the threshold voltages of the first to third memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 adjacent to the selected memory cell Fn may be prevented from changing. .

8 is a graph illustrating a program method according to a fifth embodiment of the present invention.

8 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. In a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. Pass voltages are applied to WLn-k and WLn + 1 to WLn + k). In the ISPP program operation, the first program voltage Vpgm1 is increased by the step voltage. In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the first pass voltage Vpass1 is smaller than the critical voltage CD, so that the selected word line WLn connected to the selected memory cells Fn is progressive. The rising program voltage Vpgm is applied, and the first pass voltage Vpass1 having a fixed level is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. do. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not programmed. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

When a constant second program voltage Vpgm2 is applied to the selected word line WLn, program efficiency of selected memory cells connected to the selected word line WLn may be reduced. To compensate for this, the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. When applied, the potentials of the selected memory cells increase under the influence of the second pass voltage Vpass2, thereby preventing a decrease in efficiency of the program operation according to the second program voltage Vpgm2. Preferably, the step up voltage of the second pass voltage Vpass2 may be set equal to the step voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

When the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1 are applied. A fourth pass voltage Vpass4 that is gradually lowered is applied to the adjacent second and third unselected word lines WLn-2, WLn + 2, WLn-3, and WLn + 3. In this case, the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn and the second and third unselected word lines WLn-2 and WLn + 2, The first pass voltage Vpass1 having a constant level is continuously applied to the unselected word lines WLn-4 to WLn-k and WLn + 4 to WLn + k except for WLn-3 and WLn + 3.

The fourth pass voltage Vpass4 is applied to the first and second unselected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 due to the gradually increasing second pass voltage Vpass2. In order to compensate for the increase in the threshold voltage, the voltage gradually decreases by the step-down voltages to the second and third non-selection word lines WLn-2, WLn + 2, WLn-3, and WLn + 3. The fourth pass voltage Vpass4 will be described in detail as follows. In the selected memory cell, the maximum step of the fourth pass voltage Vpass4 when the coupling ratio of the word line connected to the selected memory cell is 0.6 and the coupling ratio of the word line connected to the adjacent memory cell is 0.15. The step down voltage is 0.5V × (0.6 / 0.15) = 2V. Therefore, the step-down voltage of the fourth pass voltage Vpass4 is preferably set in a range higher than the ground voltage 0V and lower than 2V.

Since the second pass voltage Vpass2 gradually increases and the fourth pass voltage Vpass4 gradually decreases, the voltage between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 before the program operation is completed. The difference may reach the threshold CD. In this case, the fifth pass voltage Vpass5 gradually increases to the second non-selection word lines WLn-2 and WLn + 2 to which the fourth pass voltage Vpass4 is applied, and the third non-selection word is applied. The fourth pass voltage Vpass4 gradually decreases to the lines WLn-3 and WLn + 3. That is, the second non-selected memory cells Fn-2 and Fn + 2 have first non-selected word lines WLn-1 and WLn + 1 than the third non-selected memory cells Fn-3 and Fn + 3. The second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2 because they are further affected by the second pass voltage Vpass2 applied to them. The potential of is raised to compensate for the influence of the second pass voltage Vpass2. At this time, the first pass voltage Vpass1 is continuously applied to the remaining unselected word lines WLn-4 to WLn-k and WLn + 4 to WLn + k.

When the fourth pass voltage Vpass4 applied to the third non-selected word lines WLn-3 and WLn + 3 is lowered and the voltage difference with the first pass voltage Vpass1 reaches the threshold value CD, the third ratio A constant eighth pass voltage Vpass8 is applied to the select word lines WLn-3 and WLn + 3.

As described above, by lowering the maximum value of the program voltage applied to the selected word line WLn, it is possible to prevent the program voltage from excessively increasing and to prevent the excessive program voltage from rising, thereby preventing the occurrence of leakage current. In addition, by adjusting the pass voltages applied to the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 adjacent to the selected word line WLn, the selected memory cell ( During the program operation of Fn, the threshold voltages of the first to third memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 adjacent to the selected memory cell Fn may be prevented from changing. .

9 is a graph illustrating a program method according to a sixth embodiment of the present invention.

9 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. The ninth pass voltage Vpass9, which gradually rises, is also applied to WLn-k and WLn + 1 to WLn + k. However, the ninth pass voltage Vpass9 is lower than the rate of increase of the first program voltage Vpgm1. As such, the reason why the ninth pass voltage Vpass9 gradually increases to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k is because of the gradually increasing first program voltage. This is to prevent the unselected memory cells included in the unselected cell string ST from being erased due to Vpgm1. That is, since the program inhibit voltage Vcc is applied to the bit lines connected to the unselected cell strings, channel boosting is performed by the program inhibit voltage and the voltage applied to the word lines WLn-k to WLn + k. ) Occurs. In this case, when a voltage gradually increasing, such as the ninth pass voltage Vpass9, is applied, channel boosting may be more efficiently generated to increase the potential of the channel.

In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 is smaller than the critical voltage CD, so that the selected word lines WLn connected to the selected memory cells Fn are gradually selected. The rising program voltage Vpgm is applied, and the ninth pass voltage Vpass9 is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not erased. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

When the first first program voltage Vpgm1 applied to the selected word line WLn is 12V and the ninth pass voltage Vpass9 is 7V, the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 is 5V, lower than the threshold (CD). In this case, since the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn are not affected by the first program voltage Vpgm1, all of the unselected word lines WLn-1. To WLn + k and WLn + 1 to WLn + k), a ninth pass voltage Vpass9 is applied. That is, until the threshold voltages of the selected memory cells Fn do not reach the target voltage and the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 reaches the threshold CD, the first program In proportion to the number of times the voltage Vpgm1 is applied, the first program voltage Vpgm1 and the ninth pass voltage Vpass9 are gradually raised.

While executing the program while gradually applying the first program voltage Vpgm1 rising to the selected word line WLn, the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 reaches the threshold value CD. After that, a second program voltage Vpgm2 having a constant level is applied instead of the first program voltage Vpgm1 applied to the selected word line WLn thereafter. That is, the second program voltage that is maintained constant without increasing the first program voltage Vpgm1 when the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 reaches the threshold CD. Apply (Vpgm2). Therefore, the second program voltage Vpgm2 does not have a step voltage.

In this case, the ninth pass voltage Vpass1 is applied to the remaining non-selected word lines WLn-2 to WLn-k and WLn + 2 to WLn + k except for the first non-selected word lines WLn-1 and WLn + 1. Continue to apply).

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, it is possible to prevent the program voltage from excessively increasing, and by preventing the excessive voltage increase, it is possible to prevent leakage of unselected memory cells. In addition, while the program voltage is fixed at a predetermined level, the selected memory cells are gradually increased by increasing a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn. It is possible to prevent a decrease in program efficiency.

10 is a graph illustrating a program method according to a seventh embodiment of the present invention.

10 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. The ninth pass voltage Vpass9, which gradually rises, is also applied to WLn-k and WLn + 1 to WLn + k. However, the ninth pass voltage Vpass9 is lower than the rate of increase of the first program voltage Vpgm1. As such, the reason why the ninth pass voltage Vpass9 gradually increases to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k is because of the gradually increasing first program voltage. This is to prevent the unselected memory cells included in the unselected cell string ST from being erased due to Vpgm1. That is, since the program inhibit voltage Vcc is applied to the bit lines connected to the unselected cell strings, channel boosting is performed by the program inhibit voltage and the voltage applied to the word lines WLn-k to WLn + k. ) Occurs. In this case, when a voltage gradually increasing, such as the ninth pass voltage Vpass9, is applied, channel boosting may be more efficiently generated to increase the potential of the channel.

In the initial stage of the program, the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 is smaller than the critical voltage CD, so that the selected word lines WLn connected to the selected memory cells Fn are gradually selected. The rising program voltage Vpgm is applied, and the ninth pass voltage Vpass9 is applied to the remaining unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k. The threshold CD may include the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn under the influence of the first program voltage Vpgm1 when the selected memory cell Fn is programmed. This means the maximum voltage difference that is not programmed. Since the threshold value CD may vary depending on the semiconductor device, the threshold value CD may be calculated by testing the semiconductor device. In the present invention, the case where the threshold value CD is 7.5V will be described by way of example.

When the first first program voltage Vpgm1 applied to the selected word line WLn is 12V and the ninth pass voltage Vpass9 is 7V, the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 is 5V, lower than the threshold (CD). In this case, since the first non-selected memory cells Fn-1 and Fn + 1 adjacent to the selected memory cell Fn are not affected by the first program voltage Vpgm1, all of the unselected word lines WLn-1. To WLn + k and WLn + 1 to WLn + k), a ninth pass voltage Vpass9 is applied. That is, until the threshold voltages of the selected memory cells Fn do not reach the target voltage and the voltage difference between the first program voltage Vpgm1 and the ninth pass voltage Vpass9 reaches the threshold CD, the first program The first program voltage Vpgm1 and the ninth pass voltage Vpass9 are gradually raised in proportion to the number of times of applying the voltage Vpgm1.

When a constant second program voltage Vpgm2 is applied to the selected word line WLn, program efficiency of selected memory cells connected to the selected word line WLn may be reduced. To compensate for this, the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1 adjacent to both ends of the selected word line WLn. That is, even though a constant second program voltage Vpgm2 is applied to the selected word line WLn, the second pass voltage Vpass2 gradually rising to the first non-selected word lines WLn-1 and WLn + 1 is applied. When applied, it is influenced by the second pass voltage Vpass2, thereby preventing a decrease in efficiency of program operation according to the second program voltage Vpgm2. Preferably, the step up voltage of the second pass voltage Vpass2 may be set equal to the step up voltage of the first program voltage Vpgm1. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 is gradually increased by 0.5V.

In particular, while applying the second pass voltage Vpass2 gradually rising to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1. ) And second non-selected memory cells Fn-2 and Fn + 2 adjacent to the first non-selected memory cells Fn-1 and Fn + 1 and the first non-selected memory cells Fn-1 and Fn + 1. Threshold voltage can be lowered. To prevent this, the threshold value (rather than the ninth pass voltage Vpass9 is applied to the second unselected word lines WLn-2 and WLn + 2 adjacent to the first unselected word lines WLn-1 and WLn + 1. The third pass voltage Vpass3 as low as CD) is applied. In this case, the remaining non-selected word lines WLn-3 to WLn− except for the first non-selected word lines WLn-1 and WLn + 1 and the second non-selected word lines WLn-2 and WLn + 2. The ninth pass voltage Vpass9 is continuously applied to k and WLn + 3 to WLn + k. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are prevented from being lowered due to the gradually rising second pass voltage Vpass2. For example, the level of the ninth pass voltage Vpass9 applied to the second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2 may be adjusted. After lowering by the threshold value CD, a third pass voltage Vpass3 gradually rising is applied. For example, when the step voltage of the first program voltage Vpgm1 is 0.5V, the second pass voltage Vpass2 and the third pass voltage Vpass3 are gradually increased by 0.5V.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, an excessive increase in the program voltage can be prevented, and an excessive increase in the program voltage can be prevented, thereby preventing leakage of unselected memory cells. have. In addition, while performing a program operation using a program voltage having a constant level, a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn is gradually applied. The increase may prevent the program efficiency of the selected memory cells from decreasing. In this case, the first and second ratios are applied to the second unselected word lines WLn-2 and WLn + 2 by applying a third pass voltage Vpass3 lower than the second pass voltage Vapss2 by a threshold value CD. It is possible to prevent the threshold voltages of the selected memory cells Fn-1, F-2, Fn + 1, and Fn + 2 from lowering.

11 is a graph illustrating a program method according to an eighth embodiment of the present invention.

11 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing the program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. The ninth pass voltage Vpass9, which gradually rises, is also applied to WLn-k and WLn + 1 to WLn + k. However, the ninth pass voltage Vpass9 is lower than the rate of increase of the first program voltage Vpgm1. As such, the reason why the ninth pass voltage Vpass9 gradually increases to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k is because of the gradually increasing first program voltage. This is to prevent the unselected memory cells included in the unselected cell string ST from being erased due to Vpgm1. That is, since the program inhibit voltage Vcc is applied to the bit lines connected to the unselected cell strings, channel boosting is performed by the program inhibit voltage and the voltage applied to the word lines WLn-k to WLn + k. ) Occurs. In this case, when a voltage gradually increasing, such as the ninth pass voltage Vpass9, is applied, channel boosting may be more efficiently generated to increase the potential of the channel.

When the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1 are applied. A fourth pass voltage Vpass4 that is gradually lowered is applied to the adjacent second unselected word lines WLn-2 and WLn + 2. In this case, except for the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn and the second unselected word lines WLn-2 and WLn + 2 adjacent to the selected word line WLn. A ninth pass voltage Vpass9 is continuously applied to the unselected word lines WLn-3 to WLn-k and WLn + 3 to WLn + k.

The fourth pass voltage Vpass4 is a voltage applied to the second unselected memory cells Fn-2 and Fn + 2 adjacent to the first unselected memory cells Fn-1 and Fn + 1, respectively. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are prevented from being lowered due to the gradually rising second pass voltage Vpass2. In order to do so, the fourth pass voltage (step down voltage) may be gradually lowered to the second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2. Vpass4) is applied. The fourth pass voltage Vpass4 will be described in detail as follows. In the selected memory cell, the maximum step of the fourth pass voltage Vpass4 when the coupling ratio of the word line connected to the selected memory cell is 0.6 and the coupling ratio of the word line connected to the adjacent memory cell is 0.15. The step down voltage is 0.5V × (0.6 / 0.15) = 2V. Therefore, the step-down voltage of the fourth pass voltage Vpass4 is preferably set in a range higher than the ground voltage 0V and lower than 2V.

Since the second pass voltage Vpass2 gradually increases by the step-up voltage, and the fourth pass voltage Vpass4 gradually decreases by the step-down voltage, the second pass voltage Vpass2 and the second pass voltage Vpass2 and the first pass voltage before the program operation is completed. The voltage difference between the four pass voltages Vpass4 may reach the threshold CD. When the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 reaches the threshold CD, the second unselected word lines WLn-2 and WLn + to which the fourth pass voltage Vpass4 is applied. A fifth pass voltage Vpass5 that gradually rises is applied to 2). That is, when the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 becomes too large above the threshold CD, the corresponding memory cells Fn-1 and the second pass voltage Vpass2 gradually increase. Since the threshold voltage of Fn + 1) may be lowered, the fifth pass voltage Vpass5 gradually increases by the step-up voltage to the second unselected word lines WLn-2 and WLn + 2 to prevent this. Is authorized. When the second or fifth pass voltage Vpass2 or Vpass5 is applied to the first and second unselected word lines WLn-1, WLn-2, WLn + 1, and WLn + 2, the remaining unselected word lines The ninth pass voltage Vpass9 is continuously applied to the fields WLn-3 to WLn-k and WLn + 3 to WLn + k.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, an excessive increase in the program voltage can be prevented, and an excessive increase in the program voltage can be prevented, thereby preventing leakage of unselected memory cells. have. In addition, while performing a program operation using a program voltage having a constant level, a pass voltage applied to the first unselected word lines WLn-1 and WLn + 1 adjacent to the selected word line WLn is gradually applied. The increase may prevent the program efficiency of the selected memory cells from decreasing. In addition, by controlling the pass voltages applied to the second and third non-selection word lines WLn-2, WLn-3, WLn + 2 and WLn + 3, the first non-selection word lines WLn-1 and It is possible to prevent the threshold voltage change of the first to third unselected memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 due to the second pass voltage Vpass2 applied to WLn + 1. have.

12 is a graph illustrating a program method according to a ninth embodiment of the present invention.

12 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing a program voltage Vpgm. In a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. The ninth pass voltage Vpass9, which gradually rises, is also applied to WLn-k and WLn + 1 to WLn + k. However, the ninth pass voltage Vpass9 is lower than the rate of increase of the first program voltage Vpgm1. As such, the reason why the ninth pass voltage Vpass9 gradually increases to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k is because of the gradually increasing first program voltage. This is to prevent the unselected memory cells included in the unselected cell string ST from being programmed due to Vpgm1. That is, since the program inhibit voltage Vcc is applied to the bit lines connected to the unselected cell strings, channel boosting is performed by the program inhibit voltage and the voltage applied to the word lines WLn-k to WLn + k. ) Occurs. In this case, when a voltage gradually increasing, such as the ninth pass voltage Vpass9, is applied, channel boosting may be more efficiently generated to increase the potential of the channel.

Since the second pass voltage Vpass2 gradually increases and the fourth pass voltage Vpass4 gradually decreases, the voltage between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 before the program operation is completed. The difference may reach the threshold CD. At this time, the fifth pass voltage Vpass5 gradually increases to the second unselected word lines WLn-2 and WLn + 2 to which the fourth pass voltage Vpass4 is applied, and the second non-selected word is applied. The sixth pass voltage Vpass6 that is gradually lowered is applied to the third unselected word lines WLn-3 and WLn + 3 adjacent to the lines WLn-2 and WLn + 2. That is, when the voltage difference between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 becomes too large above the threshold CD, the first non-selected memory cells Fn by the gradually increasing second pass voltage Vpass2. Since the threshold voltages of −1 and Fn + 1 may be lowered, a fifth pass voltage Vpass5 gradually applied to the second unselected word lines WLn-2 and WLn + 2 may be applied to prevent the threshold voltages of −1 and Fn + 1. will be. Second, fifth, or sixth pass voltages on the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 sequentially adjacent to the selected word line WLn. When applying Vpass2, Vpass5, or Vpass6, the ninth pass voltage Vpass9 is continuously applied to the remaining unselected word lines WLn-4 through WLn-k and WLn + 4 through WLn + k.

When the sixth pass voltage Vpass6 is gradually applied to the third non-selected word lines WLn-3 and WLn + 3, a voltage between the sixth pass voltage Vpass6 and the ninth pass voltage Vpass9 is applied. The difference may reach the threshold CD. At this time, in order to prevent the voltage difference between the third unselected word lines WLn-3 and WLn + 3 and the fourth word lines WLn-4 and WLn + 4 from increasing further, the sixth pass voltage ( A tenth pass voltage Vpass10 that is gradually increased is applied to the third unselected word lines WLn-3 and WLn + 3 having the potential lowered to Vpass6). The rate of increase of the tenth pass voltage Vpass10 is equal to the rate of increase of the fifth pass voltage Vpass5.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, an excessive increase in the program voltage can be prevented, and an excessive increase in the program voltage can be prevented, thereby preventing leakage of unselected memory cells. have. In addition, by adjusting the pass voltages applied to the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 adjacent to the selected word line WLn, the selected memory cell ( During the program operation of Fn, the threshold voltages of the first to third memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 adjacent to the selected memory cell Fn may be prevented from changing. .

13 is a graph for explaining a program method according to a tenth embodiment of the present invention.

Referring to FIGS. 13 and 3, the program operation is performed by an incremental step pulse program (ISPP) method of gradually increasing the program voltage Vpgm. During a program operation, a program allowance voltage (ground voltage) is applied to bit lines connected to selected cell strings, and a program prohibition voltage (power supply voltage) is applied to bit lines connected to unselected cell strings. In the state where the program permission voltage or the program inhibit voltage is applied to the bit lines, the first program voltage Vpgm1 that gradually rises is applied to the selected word line WLn, and the remaining unselected word lines WLn-1 through. The ninth pass voltage Vpass9, which gradually rises, is also applied to WLn-k and WLn + 1 to WLn + k. However, the ninth pass voltage Vpass9 is lower than the rate of increase of the first program voltage Vpgm1. As such, the reason why the ninth pass voltage Vpass9 gradually increases to the unselected word lines WLn-1 to WLn-k and WLn + 1 to WLn + k is because of the gradually increasing first program voltage. This is to prevent the unselected memory cells included in the unselected cell string ST from being erased due to Vpgm1. That is, since the program inhibit voltage Vcc is applied to the bit lines connected to the unselected cell strings, channel boosting is performed by the program inhibit voltage and the voltage applied to the word lines WLn-k to WLn + k. ) Occurs. In this case, when a voltage gradually increasing, such as the ninth pass voltage Vpass9, is applied, channel boosting may be more efficiently generated to increase the potential of the channel.

When the second pass voltage Vpass2 gradually increases to the first unselected word lines WLn-1 and WLn + 1, the first unselected word lines WLn-1 and WLn + 1 are applied. A fourth pass voltage Vpass4 that is gradually lowered is applied to sequentially adjacent second and third unselected word lines WLn-2, WLn + 2, WLn-3, and WLn + 3. In this case, the first unselected word lines WLn-1 and WLn + 1 and the second and third unselected word lines WLn-2, WLn + 2, WLn-3 and the adjacent word line WLn. The ninth pass voltage Vpass9 is continuously applied to the unselected word lines WLn-4 to WLn-k and WLn + 4 to WLn + k except for WLn + 3. That is, the threshold voltages of the first and second non-selected memory cells Fn-1, Fn-2, Fn + 1, and Fn + 2 are prevented from being lowered due to the gradually rising second pass voltage Vpass2. In order to do so, step down the second and third unselected word lines WLn-2, WLn + 2, WLn-3, and WLn + 3 connected to the second unselected memory cells Fn-2 and Fn + 2. The fourth pass voltage Vpass4 gradually decreases by voltage. The fourth pass voltage Vpass4 will be described in detail as follows. In the selected memory cell, the maximum step of the fourth pass voltage Vpass4 when the coupling ratio of the word line connected to the selected memory cell is 0.6 and the coupling ratio of the word line connected to the adjacent memory cell is 0.15. The step down voltage is 0.5V × (0.6 / 0.15) = 2V. Therefore, the step-down voltage of the fourth pass voltage Vpass4 is preferably set in a range higher than the ground voltage 0V and lower than 2V.

Since the second pass voltage Vpass2 gradually increases and the fourth pass voltage Vpass4 gradually decreases, the voltage between the second pass voltage Vpass2 and the fourth pass voltage Vpass4 before the program operation is completed. The difference may reach the threshold CD. In this case, the fifth pass voltage Vpass5 gradually increases to the second non-selection word lines WLn-2 and WLn + 2 to which the fourth pass voltage Vpass4 is applied, and the third non-selection word is applied. The fourth pass voltage Vpass4 gradually decreases to the lines WLn-3 and WLn + 3. That is, the second non-selected memory cells Fn-2 and Fn + 2 have first non-selected word lines WLn-1 and WLn + 1 than the third non-selected memory cells Fn-3 and Fn + 3. The second unselected word lines WLn-2 and WLn + 2 connected to the second unselected memory cells Fn-2 and Fn + 2 because they are further affected by the second pass voltage Vpass2 applied to them. The potential of is raised to compensate for the influence of the second pass voltage Vpass2. At this time, the ninth pass voltage Vpass9 is continuously applied to the remaining unselected word lines WLn-4 to WLn-k and WLn + 4 to WLn + k.

When the fourth pass voltage Vpass4 applied to the third non-selected word lines WLn-3 and WLn + 3 is lowered and the voltage difference with the ninth pass voltage Vpass9 reaches the threshold value CD, the third ratio. An eleventh pass voltage Vpass11 that is gradually increased is applied to the select word lines WLn-3 and WLn + 3. The eleventh pass voltage Vpass11 is equal to the rate of increase of the ninth pass voltage Vpass9.

As such, by lowering the maximum value of the program voltage applied to the selected word line WLn, it is possible to prevent the program voltage from excessively increasing and to prevent the excessive program voltage from rising, thereby preventing the occurrence of leakage current of the unselected memory cells. It can prevent. In addition, by adjusting the pass voltages applied to the first to third unselected word lines WLn-1 to WLn-3 and WLn + 1 to WLn + 3 adjacent to the selected word line WLn, the selected memory cell ( During the program operation of Fn, the threshold voltages of the first to third memory cells Fn-1 to Fn-3 and Fn + 1 to Fn + 3 adjacent to the selected memory cell Fn may be prevented from changing. .

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

110: memory cell array 120: control circuit
130: voltage generation circuit 140: low decoder
150: page buffer group 160: column selection circuit
170: input / output circuit 180: pass / fail determination circuit
Fn: selected memory cell Fn-1, Fn + 1: first non-selected memory cell
Fn-2, Fn + 2: second non-selected memory cell Fn-3, Fn + 3: third non-selected memory cell
WLn: selected word line WLn-1, WLn + 1: first unselected word line
WLn-2, WLn + 2: second unselected wordline WLn-3, WLn + 3: third unselected wordline
Vpgm: Program Voltage Vpass: Pass Voltage

Claims

Programming the selected memory cells by applying a gradually rising first program voltage to the selected word line and applying a constant first pass voltage to the remaining unselected word lines; And
When the voltage difference between the first program voltage and the first pass voltage reaches a threshold, a constant second program voltage is applied to the selected word line, and is gradually applied to the first unselected word lines adjacent to the selected word line. Programming the selected memory cells while applying a rising second pass voltage.

The method of claim 1,
When the second pass voltage is applied to the first unselected word lines,
And performing a program operation while applying a third pass voltage having the potentials of the second unselected word lines adjacent to the first non-selected word lines respectively lowered by the threshold value than the first pass voltage. How it works.

The method of claim 2,
And the third pass voltage gradually increases in proportion to the second pass voltage.

The method of claim 1,
When the second pass voltage is applied to the first unselected word lines,
Applying a fourth pass voltage that is gradually lowered to second unselected wordlines adjacent to the first unselected wordlines; And
If the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, applying a fifth pass voltage gradually increasing in proportion to the second pass voltage to second unselected word lines. Method of operation of a semiconductor device comprising.

5. The method of claim 4,
When the fifth pass voltage is applied to the second unselected word lines,
Applying a sixth pass voltage that is gradually lowered to third unselected word lines adjacent to the second unselected word lines, respectively; And
And applying a seventh pass voltage to the second unselected word lines when the voltage difference between the sixth pass voltage and the first pass voltage reaches the threshold.

The method of claim 1,
When the second pass voltage is applied to the first unselected word lines,
Applying a fourth pass voltage that is gradually lowered to second and third non-selected word lines sequentially adjacent to the first non-selected word lines; And
When the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, a fifth pass voltage gradually increasing in proportion to the second pass voltage is applied to the second unselected word lines, and the second pass voltage is applied. And further applying the fourth pass voltage to the unselected word lines until the voltage difference with the first pass voltage reaches the threshold.

The method according to claim 6,
And applying a constant eighth pass voltage to the second non-selected word lines when the voltage difference between the fourth pass voltage applied to the third non-selected word lines and the first pass voltage reaches the threshold. Method of operation.

The selected word line is applied with a first program voltage that gradually increases by a first step voltage, and the remaining unselected word lines are applied with a ninth pass voltage that gradually rises to a level lower than the first program voltage. Programming selected memory cells connected to a word line; And
During programming of the selected memory cells, if a voltage difference between the first program voltage and the ninth pass voltage reaches a threshold, a second program voltage is applied to the selected word line, and the second word adjacent to the selected word line is applied. And programming the selected memory cells while applying a second pass voltage that gradually increases by the first step voltage to unselected word lines.

9. The method of claim 8,
When the second pass voltage is applied to the first unselected word lines,
And applying a third pass voltage lowering the potential of second non-selected word lines adjacent to the first non-selected word lines, respectively, by the threshold value, than the ninth pass voltage.

10. The method of claim 9,
And the third pass voltage gradually increases in proportion to the second pass voltage.

9. The method of claim 8,
When the second pass voltage is applied to the first unselected word lines,
Applying a fourth pass voltage that is gradually lowered to second unselected word lines adjacent to the first unselected word lines, respectively; And
If the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, applying a fifth pass voltage gradually increasing in proportion to the second pass voltage to second unselected word lines. Method of operation of a semiconductor device comprising.

The method of claim 11,
When the fifth pass voltage is applied to the second unselected word lines,
Applying a sixth pass voltage that is gradually lowered to third unselected word lines adjacent to the second unselected word lines, respectively; And
When the voltage difference between the sixth pass voltage and the ninth pass voltage reaches the threshold, applying a tenth pass voltage gradually increasing in proportion to the ninth pass voltage to the third unselected word lines. A method of operating a semiconductor device further comprising.

9. The method of claim 8,
When the second pass voltage is applied to the first unselected word lines,
Applying a fourth pass voltage that is gradually lowered to second and third non-selected word lines sequentially adjacent to the first non-selected word lines; And
When the voltage difference between the fourth pass voltage and the second pass voltage reaches the threshold, a fifth pass voltage gradually increasing in proportion to the second pass voltage is applied to the second unselected word lines, and the second pass voltage is applied. And applying the fourth pass voltage to the non-selected word lines until the voltage difference with the ninth pass voltage reaches the threshold.

The method of claim 13,
When the voltage difference between the fourth pass voltage and the ninth pass voltage applied to the third unselected word lines reaches the threshold, the third unselected word lines are gradually increased in proportion to the ninth pass voltage. An operating method of a semiconductor device applying a rising eleventh pass voltage.