JP2009205728A - Nand type nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for preventing insufficiency of write-in of selection cells. <P>SOLUTION: The NAND type nonvolatile semiconductor memory includes: n memory cells (where n is an integer of 4 or more) connected in series to one another; and a driver which applies first voltage to a control gate electrode of a first memory cell being an object of programming out of n memory cells during programming, applies second voltage being lower than the first voltage to each of a control gate electrode of a second memory cell being adjacent to a source line side of the first memory cell and a control gate electrode of a third memory cell being adjacent to a bit line side of the first memory cell, and applies third voltage being lower than the second voltage to control gate electrodes of residual memory cells other than the first, the second, and the third memory cell out of n memory cells. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a programming method for a NAND type nonvolatile semiconductor memory.

  In recent years, the use of NAND-type non-volatile semiconductor memories has been expanded, and the memory capacity has been steadily increasing (for example, see Patent Document 1). However, when a memory cell is miniaturized due to an increase in memory capacity, the capacity generated between a selected cell to be programmed and an unselected cell adjacent to it (hereinafter, between adjacent cells) increases. Problem of insufficient writing.

  In particular, in multi-level technology, which is attracting attention as a technology that contributes to an increase in memory capacity, data of three or more values is stored in one memory cell. There are cases where the threshold value must be increased.

  In this case, for example, a program voltage must be applied to the control gate electrode to inject many electrons from the substrate into the charge storage layer of the memory cell, but when a certain amount of electrons are injected into the charge storage layer, A high electric field is generated between the control gate and the charge storage layer, and a leak current is generated between the two.

For this reason, thereafter, even if electrons are injected from the substrate into the charge storage layer of the memory cell, electrons are released from the charge storage layer of the memory cell to the control gate electrode, and the electrons are directed into the charge storage layer. Does not accumulate, that is, the threshold value of the memory cell cannot be raised, causing a problem of insufficient writing.
Japanese Patent Laid-Open No. 2005-100548

  The present invention proposes a technique for preventing insufficient writing of selected cells.

  A NAND-type nonvolatile semiconductor memory according to an example of the present invention includes a charge storage layer and a control gate electrode, and n (n is an integer of 4 or more) memory cells connected in series, and n memory cells A first select gate transistor connected between one end of the memory cell and the source line; a second select gate transistor connected between the other end of the n memory cells and the bit line; Among the memory cells, the first voltage is applied to the control gate electrode of the first memory cell to be programmed, and the control gate electrode and the first memory cell of the second memory cell adjacent to the source line side of the first memory cell A second voltage lower than the first voltage is applied to the control gate electrode of the third memory cell adjacent to the bit line side of each of the n memory cells. Chi, and a first driver for applying a lower third voltage than the second voltage to the control gate electrode of the second and remaining memory cells other than the third memory cell. The first, second, and third voltages are equal to or greater than a value that turns on the n memory cells regardless of their thresholds.

  According to the present invention, insufficient writing of a selected cell can be prevented.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Overview
In the NAND type nonvolatile semiconductor memory, a program voltage Vpgm is applied to the control gate electrode of the selected cell in the NAND cell unit and a transfer voltage Vpass lower than the program voltage Vpgm is applied to the control gate electrode of the non-selected cell during programming. .

  In the present invention, at least two transfer voltages Vpass are prepared.

  One is a transfer voltage Vpass.h1 applied to the control gate electrodes of two adjacent cells (non-selected cells) adjacent to both sides of the selected cell, and the other is the remaining voltage other than the selected cell and the adjacent cell. The transfer voltage Vpass is lower than the transfer voltage Vpass.h1 applied to the control gate electrode of the non-selected cell.

  That is, Vpass <Vpass.h1 <Vpgm.

  Here, these three voltages Vpass, Vpass.h1, and Vpgm are equal to or higher than values for turning on the memory cells in the NAND string regardless of their threshold values.

  In this case, the potential Vfg of the charge storage layer (for example, floating gate electrode) of the selected cell is the program voltage Vpgm applied to the control gate electrode of the selected cell and the transfer voltage Vpass applied to the control gate electrode of the adjacent cell. Is determined mainly by the higher transfer voltage Vpass.h1.

  That is, the potential Vfg of the charge storage layer of the selected cell is higher when the transfer voltage Vpass.h1 is applied than when the transfer voltage Vpass is applied to the control gate electrode of the adjacent cell. The high electric field between the layers is relaxed, and the leakage current generated between the two is suppressed.

  Therefore, insufficient writing to the selected cell is prevented.

  By the way, the problem of insufficient writing occurs when the threshold value of the memory cell is raised to some extent, as described in the background art. That is, in the initial stage of writing in which not many electrons are stored in the charge storage layer, even if the transfer voltage Vpass.h1 is not applied to the adjacent cell, the electron is stored in the charge storage layer only by the program voltage Vpgm applied to the selected cell. It is possible to accumulate.

  Further, when the transfer voltage applied to the control gate electrode of the adjacent cell is changed from Vpass to Vpass.h1, there is a concern of erroneous writing (threshold increase) to the adjacent cell.

  Therefore, in order to shorten the period for applying the transfer voltage Vpass.h1 to the adjacent cell and eliminate the fear of erroneous writing, the timing for applying the transfer voltage Vpass.h1 accumulates some electrons in the charge storage layer of the selected cell, After a state where a leakage current is generated between the charge storage layer and the control gate.

  Specifically, the transfer voltage Vpass.h1 is given after the program voltage Vpgm is given. When the program voltage Vpgm reaches a maximum value through a plurality of steps, the transfer voltage Vpass.h1 is set to a maximum value after the program voltage Vpgm reaches the maximum value.

  As a result, the problem of insufficient writing to the selected cell can be solved without leaving the fear of erroneous writing in adjacent cells.

  The present invention is effective within the range of Vpass <Vpass.h1 <Vpgm. However, the specific value of the transfer voltage Vpass.h1 satisfies both prevention of insufficient writing of the selected cell and prevention of erroneous writing of the adjacent cell. Therefore, the optimum value is set within the above-mentioned range.

  The present invention is very effective when the threshold value of the memory cell has to be very high as in the multi-value technology.

2. Embodiment
(1) NAND type nonvolatile semiconductor memory
First, an outline of the NAND type nonvolatile semiconductor memory will be described.

  In the following explanation, for simplicity, binary is assumed.

  A state where the threshold value of the memory cell is low is referred to as an erased state (“1” -state), and a state where the threshold is high is referred to as a written state (“0” -state). The initial state of the memory cell is an erased state.

  There are two types of programming: “1” -programming and “0” -programming. The former means that writing is prohibited (maintaining an erased state), and the latter means that writing is executed (threshold rise).

  FIG. 1 is an overall view of a NAND type nonvolatile semiconductor memory.

  The memory cell array 11 has a plurality of blocks BK1, BK2,... BLj. Each of the plurality of blocks BK1, BK2,... BLj has a NAND cell unit.

  The data latch circuit 12 has a function of temporarily latching data at the time of reading / programming, and is composed of, for example, a flip-flop circuit. An I / O (input / output) buffer 13 functions as an interface circuit for data, and an address buffer 14 functions as an interface circuit for address signals.

  The address signal includes a block address signal, a row address signal, and a column address signal.

  The row decoder 15 selects one of the plurality of blocks BK1, BK2,... BLj based on the block address signal, and selects the plurality of word lines in the selected block based on the row address signal. Select one of them. The word line driver 17 drives a plurality of word lines in the selected block.

  The column decoder 16 selects one of the plurality of bit lines based on the column address signal.

  The substrate voltage control circuit 18 controls the voltage of the semiconductor substrate. Specifically, when a double well region including an n type well region and a p type well region is formed in a p type semiconductor substrate and a memory cell is formed in the p type well region, the voltage of the p type well region is determined. Is controlled according to the operation mode.

  For example, the substrate voltage control circuit 18 sets the p-type well region to 0V at the time of reading / programming, and sets the p-type well region to a voltage of 15V to 40V at the time of erasing.

  The voltage generation circuit 19 generates a voltage for controlling the word line driver 17.

  In the present invention, the voltage generation circuit 19 generates a voltage to be supplied to a plurality of word lines in the selected block, that is, a program voltage Vpgm and two transfer voltages Vpash and Vpass.

  The selector 24 selects values of voltages supplied to a plurality of word lines in the selected block based on information such as the operation mode and the position of the selected word line.

  The control circuit 20 controls operations of the substrate voltage control circuit 18 and the voltage generation circuit 19.

  FIG. 2 shows a circuit example of the memory cell array and the word line driver.

  The memory cell array 11 has a plurality of blocks BK1, BK2,... Arranged in the column direction. Each of the plurality of blocks BK1, BK2,... Has a plurality of NAND cell units arranged in the row direction. The NAND cell unit has a NAND string composed of a plurality of memory cells MC connected in series, and two select gate transistors ST connected to both ends of the NAND string unit.

  The NAND cell unit has, for example, a layout as shown in FIG. The cross-sectional structure of the NAND cell unit in the column direction is, for example, as shown in FIG.

  One end of the NAND cell unit is connected to the bit lines BL1, BL2,... BLm, and the other end is connected to the source line SL.

  A plurality of word lines WL1,... WLn,... And a plurality of select gate lines SGS1, SGD1,.

  For example, n (n is a plurality) word lines WL1,... WLn and two select gate lines SGS1, SGD1 are arranged in the block BK1. Word lines WL1,... WLn and select gate lines SGS1, SGD1 extend in the row direction, and are respectively connected to signal lines (control gate lines) via transfer transistor unit 21 (BK1) in word line driver 17 (DRV1). ) CG1,... CGn and signal lines SGSV1, SGDV1.

  The signal lines CG1,... CGn, SGSV1, SGDV1 extend in the column direction intersecting with the row direction, and are connected to the selector 24.

  The transfer transistor unit 21 (BK1) is composed of a high voltage type MISFET so that a voltage higher than the power supply voltage Vcc can be transferred.

  Booster 22 in word line driver 17 (DRV1) receives a decode signal output from row decoder 15. The booster 22 turns on the transfer transistor unit 21 (BK1) when the block BK1 is selected, and turns off the transfer transistor unit 21 (BK1) when the block BK1 is not selected.

(2) Programming operation
A. First embodiment
In the first embodiment, the transfer voltage Vpass.h1 is applied to the control gate electrode of the adjacent cell adjacent to the source line side of the selected cell and the control gate electrode of the adjacent cell adjacent to the bit line side of the selected cell.

FIG. 5 shows a voltage relationship in the NAND cell unit at the time of programming.
The selected cell is a memory cell MC (k) that exists in the center of the NAND string.

  A program voltage Vpgm is applied to the control gate electrode CG of the memory cell MC (k). Further, the memory cell MC (k) adjacent to the source line SL side and the memory cell (non-selected cell) MC (k−1) adjacent to the control gate electrode CG and the memory cell MC (k) adjacent to the bit line BL side. A transfer voltage Vpass.h1 is applied to each control gate electrode CG of the cell (non-selected cell) MC (k + 1).

  The remaining memory cells (non-selected cells) other than the memory cells MC (k), MC (k-1), MC (k + 1) MC (k-2), MC (k + 2), MC (k-3), MC ( A transfer voltage Vpass lower than the transfer voltage Vpass.h1 is applied to the control gate electrode CG of k + 3).

  The magnitude relationship between these three voltages is Vpass <Vpass.h1 <Vpgm.

  Vpass, Vpass.h1, and Vpgm have values greater than or equal to values that turn on the memory cells MC (k−3),... MC (k + 3) in the NAND string regardless of their threshold values.

FIG. 6 shows a first example of voltage application timing for the device of FIG.
Here, only three of Vpass, Vpass.h1, and Vpgm according to the present invention are shown.

  First, at time t1, the transfer voltage Vpass is applied to the control gate electrodes CG of all the memory cells MC (k−3),... MC (k + 3) in the NAND string of the selected block. That is, the transfer voltage Vpass.h1 and the program voltage Vpgm are set to Vpass as an intermediate value before reaching the maximum value.

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and two memory cells (adjacent cells) MC (k−1) adjacent to both sides of the memory cell MC (k) are displayed. , MC (k + 1) and the voltage of the control gate electrode CG are further increased from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is set to Vpgm (maximum value), and the memory cells (adjacent cells) MC (k−1) and MC (k + 1) are controlled. The voltage of the gate electrode CG is set to Vpass.h1 (maximum value).

At this time, the potential Vfg (k) Inv. Of the floating gate electrode FG of the memory cell MC (k) is
Vfg (k) Inv. = (Crn x Vpass.h1) + Cr1 x (Vpgm-Vpass.h1)… (1)
It becomes.

  However, Crn is the coupling of the memory cell MC (k) by capacitive coupling when the voltage of the control gate electrode CG of the three memory cells MC (k−1), MC (k), MC (k + 1) is increased. Cr1 is a coupling ratio of the memory cell MC (k) when the voltage of the control gate electrode CG of only one memory cell MC (k) is increased.

On the other hand, all the remaining memory cells (non-selected cells) other than the memory cell (selected cell) MC (k) MC (k−3),... MC (k−1), MC (k + 1),. In the conventional case of writing with the control gate electrode CG of Vpass as Vpass,
The potential Vfg (k) Con. Of the floating gate electrode FG of the memory cell MC (k) is
Vfg (k) Con. = (Crn x Vpass) + Cr1 x (Vpgm-Vpass)… (2)
It becomes.

  Here, when Crn = 0.73, Cr1 = 0.6, Vpass = 9 V, Vpass.h1 = 12.5 V, Vpgm = 24 V, Vfg (k) Inv. = 16.025 V and Vfg (k) Con. = 15.57 V It becomes.

  That is, according to the present invention, the potential Vfg (k) of the floating gate electrode FG of the memory cell (selected cell) MC (k) is Vfg (k) Inv.−Vfg (k) Con. = 0.455 V can be raised.

  Therefore, the threshold value of the memory cell (selected cell) MC (k) can be increased as compared with the conventional case, and occurrence of insufficient writing can be prevented.

  From another viewpoint, this effect means that the program voltage Vpgm necessary for injecting a certain amount of electrons into the floating gate electrode FG of the memory cell (selected cell) MC (k) can be reduced.

  In this case, the control gate electrode CG of the memory cell MC (k) is Vpgm−ΔVpgm. ΔVpgm is a value of the program voltage that can be made smaller than before.

At this time, the potential Vfg (k) Inv. Of the floating gate electrode FG of the memory cell MC (k) is
Vfg (k) Inv. = (Crn x Vpass.h1) + Cr1 x (Vpgm-ΔVpgm-Vpass.h1)… (3)
It becomes.

If the amount of electrons injected into the floating gate electrode FG of the memory cell MC (k) is the same between the present invention and the conventional one,
Vfg (k) Con. In Expression (2) is equal to Vfg (k) Inv. In Expression (3).

Therefore,
ΔVpgm = ((Crn / Cr1)-1) x (Vpass.h1-Vpass)… (4)
It becomes.

Where Crn = 0.73, Cr1 = 0.6, Vpass = 9 V, Vpass.h1 = 12.5 V, Vpgm = 24 V,
ΔVpgm = about 0.76 V
It becomes.

  As described above, according to the present invention, the same amount of electrons is set in the floating gate electrode FG in a state where the program voltage is lower by ΔVpgm (= about 0.76 V) than the conventional program voltage Vpgm (= 24 V). It becomes possible to inject.

  As a result, the electric field between the control gate electrode CG and the floating gate electrode FG is reduced by about 6%, whereby the leakage current generated between them is reduced by about 24%. In addition, since the program voltage Vpgm can be lowered, interference between adjacent cells can be reduced.

  Another example of voltage application timing for the device of FIG. 5 will be described.

FIG. 7 shows a second example of voltage application timing for the device of FIG.
The feature of the second example is that the transfer voltage Vpass.h1 is maximized after the program voltage Vpgm is maximized.

  First, at time t1, the transfer voltage Vpass is applied to the control gate electrodes CG of all the memory cells MC (k−3),... MC (k + 3) in the NAND string of the selected block. That is, the transfer voltage Vpass.h1 and the program voltage Vpgm are set to Vpass as an intermediate value before reaching the maximum value.

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and two memory cells (adjacent cells) MC (k−1) adjacent to both sides of the memory cell MC (k) are displayed. , MC (k + 1) and the voltage of the control gate electrode CG are further increased from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is set to Vpgm (maximum value), and at time t4, the memory cells (adjacent cells) MC (k−1), MC ( The voltage of the control gate electrode CG of (k + 1) is set to Vpass.h1 (maximum value).

  In the second example, by delaying the timing when Vpass.h1 reaches the maximum value, the possibility of erroneous writing to the memory cells (adjacent cells) MC (k−1) and MC (k + 1) can be eliminated. In addition, since the problem of insufficient writing occurs when the threshold value of the memory cell becomes high to some extent, the delay in timing at which Vpass.h1 reaches the maximum value has no influence on the effect of the present invention to eliminate insufficient writing. Absent.

  FIG. 8 shows changes in the potential of the floating gate electrode FG (Vfg with Vpass.h1) when Vpass and Vpass.h1 are used, and the potential (Vfg without Vpass.h1) of the floating gate electrode FG when only Vpass is used. ) Changes.

  The difference between the potentials Vfg of the two floating gate electrodes FG is particularly noticeable at the final stage of writing, and this difference affects how high the threshold value of the memory cell can be increased.

  The potential of the floating gate electrode FG when using Vpass and Vpass.h1 (Vfg with Vpass.h1) is higher than the potential of the floating gate electrode FG when using only Vpass (Vfg without Vpass.h1). The problem of insufficient writing can be solved.

FIG. 9 shows a third example of voltage application timing for the device of FIG.
The third example is a modification of the second example.
The feature of the third example is that the transfer voltage Vpass.h1 is maximized in two steps from Vpass, and the transfer voltage Vpass.h1 is maximized after the program voltage Vpgm is maximized.

  First, at time t1, the transfer voltage Vpass is applied to the control gate electrodes CG of all the memory cells MC (k−3),... MC (k + 3) in the NAND string of the selected block. That is, the transfer voltage Vpass.h1 and the program voltage Vpgm are set to Vpass as an intermediate value before reaching the maximum value.

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and two memory cells (adjacent cells) MC (k−1) adjacent to both sides of the memory cell MC (k) are displayed. , MC (k + 1) and the voltage of the control gate electrode CG are further increased from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is set to Vpgm (maximum value), and the memory cells (adjacent cells) MC (k−1) and MC (k + 1) are controlled. The voltage of the gate electrode CG is set higher than Vpass and lower than Vpass.h1.

  At time t4, the voltage of the control gate electrode CG of the memory cells MC (k−1) and MC (k + 1) is further increased, and at time t5, the control of the memory cells MC (k−1) and MC (k + 1) is performed. The voltage of the gate electrode CG is set to Vpass.h1 (maximum value).

  In the third example, similarly to the second example, the possibility of erroneous writing to the memory cells (adjacent cells) MC (k−1) and MC (k + 1) is delayed by delaying the timing at which Vpass.h1 reaches the maximum value. Can be eliminated. Also, the problem of insufficient writing can be solved by giving Vpass.h1.

FIG. 10 shows a fourth example of voltage application timing for the device of FIG.
The feature of the fourth example is that the program voltage Vpgm is maximized after the transfer voltage Vpass.h1 is maximized.

  First, at time t1, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and two memory cells (adjacent cells) MC (k−1) adjacent to both sides of the memory cell MC (k). , MC (k + 1), the transfer voltage Vpass is applied to the control gate electrode CG of the memory cells MC (k-3), MC (k-2), MC (k + 2), MC (k + 3).

  Further, a transfer voltage Vpass.h1 higher than the transfer voltage Vpass is applied to the control gate electrodes CG of the two memory cells MC (k−1) and MC (k + 1) adjacent to both sides of the memory cell MC (k).

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is further raised from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell MC (k) is set to Vpgm (maximum value).

  In the fourth example, the timing at which Vpass.h1 reaches the maximum value is advanced, but by adjusting the value of the transfer voltage Vpass.h1, the memory cells (adjacent cells) MC (k−1), MC (k + 1) The possibility of erroneous writing to can be eliminated. Also, the problem of insufficient writing can be solved by giving Vpass.h1.

  Next, a specific programming method for the NAND string in the selected block will be described with reference to FIGS.

  In order to simplify the following description, it is assumed that the NAND string is composed of four memory cells which are the minimum values for carrying out the present invention. Further, consider a case where “0” is programmed for the memory cell connected to the bit line BL1, and “1” is programmed for the memory cell connected to the bit line BL2.

  The initial state of the memory cell in the NAND string is an erased state (“1” state).

  In this case, the bit line BL1 is set to “0” -low voltage Vbl1 (eg, 0V) for programming, and the bit line BL2 is set to “1” -positive voltage Vbl2 (eg, 1.2V). -4.0V).

The voltage Vsgd is applied to the bit line side select gate line SGD. The value of Vsgd is
Vth_sgd (0) <Vsgd <Vbl2 + Vth_sgd (Vbl2)
Shall be satisfied.

  However, Vth_sgd means a threshold voltage of the bit line side select gate transistor, and () means a back bias voltage applied to the source of the bit line side select gate transistor.

  Normally, Vsgd is set to the same value as Vbl2.

  Further, a voltage Vsgs (for example, 0 V) for cutting off the source line side select gate transistor is applied to the source line side select gate line SGS.

  The source line SL is set to Vs, for example, 0V.

  As a result, the bit line side select gate transistor connected to the bit line BL1 is turned on, and the voltage Vbl1 is transferred from the bit line BL1 to the channel of the memory cell in the NAND string.

  Therefore, when Vpgm is applied to the selected word line, in the selected cell, electrons are injected from the channel into the charge storage layer (for example, floating gate electrode), and writing (threshold increase) is performed.

  On the other hand, in the bit line side select gate transistor connected to the bit line BL2, for example, when Vpass.h1 and Vpass are applied to the word line, the channel of the memory cell in the NAND string is boosted by capacitive coupling. Cut off automatically.

  In addition, when Vpgm is applied to the selected word line, the channel voltage of the selected cell further increases. Therefore, in the selected cell, electrons are not injected from the channel into the charge storage layer, and writing is prohibited (erasure state is maintained).

  In such a programming operation, a transfer voltage Vpass.h1 higher than the transfer voltage Vpass is applied to the control gate electrodes of two adjacent cells adjacent to both sides of the selected cell, that is, the word line.

  11 and 12, among the four memory cells constituting the NAND string, the two end memory cells adjacent to the source line side / bit line side select gate transistor are dummy cells DUMMY not to be programmed. It is an example.

  For example, programming is sequentially performed one by one from the memory cell on the source line side to the memory cell on the drain side.

  First, as shown in FIG. 11, the program voltage Vpgm is applied to the word line WL2, the transfer voltage Vpass.h1 is applied to the word lines WL1 and WL3, and the transfer voltage Vpass is applied to the word line WL4. Then, programming is performed on the memory cell (selected cell) connected to the word line WL2.

  Next, as shown in FIG. 12, the program voltage Vpgm is applied to the word line WL3, the transfer voltage Vpass.h1 is applied to the word lines WL2 and WL4, and the transfer voltage Vpass is applied to the word line WL1. Then, programming is performed for the memory cell (selected cell) connected to the word line WL3.

  FIG. 13 to FIG. 16 are examples in which all of the four memory cells constituting the NAND string are targeted for programming.

  For example, programming is sequentially performed one by one from the memory cell on the source line side to the memory cell on the drain side.

  First, as shown in FIG. 13, the program voltage Vpgm is applied to the word line WL1, the transfer voltage Vpass.h1 is applied to the word line WL2, and the transfer voltage Vpass is applied to the word lines WL3 and WL4. Then, programming is performed for the memory cell (selected cell) connected to the word line WL1.

  Here, when programming a memory cell (selected cell) connected to the word line WL1, there is only one adjacent cell on the bit line side adjacent to the selected cell. What is necessary is just to give Vpass.h1 to the one adjacent cell.

  Next, as shown in FIG. 14, the program voltage Vpgm is applied to the word line WL2, the transfer voltage Vpass.h1 is applied to the word lines WL1 and WL3, and the transfer voltage Vpass is applied to the word line WL4. Then, programming is performed on the memory cell (selected cell) connected to the word line WL2.

  Next, as shown in FIG. 15, the program voltage Vpgm is applied to the word line WL3, the transfer voltage Vpass.h1 is applied to the word lines WL2 and WL4, and the transfer voltage Vpass is applied to the word line WL1. Then, programming is performed for the memory cell (selected cell) connected to the word line WL3.

  Finally, as shown in FIG. 16, the program voltage Vpgm is applied to the word line WL4, the transfer voltage Vpass.h1 is applied to the word line WL3, and the transfer voltage Vpass is applied to the word lines WL1 and WL2. Then, programming is performed for the memory cell (selected cell) connected to the word line WL4.

  Here, when programming is performed on the memory cell (selected cell) connected to the word line WL4, there is only one adjacent cell on the source line side adjacent to the selected cell. What is necessary is just to give Vpass.h1 to the one adjacent cell.

  As described above, according to the first embodiment, by providing Vpass.h1 higher than Vpass to two adjacent cells existing on both sides of the selected cell, it is possible to solve the shortage of writing to the selected cell.

B. Second embodiment
The second embodiment is an application example of the first embodiment including the features of the first embodiment.

  In the second embodiment, the control gate electrode of the memory cell adjacent to the source line side of the adjacent cell adjacent to the source line side of the selected cell, and the bit line side of the adjacent cell adjacent to the bit line side of the selected cell The transfer voltage Vpass.h2 is applied to at least one of the control gate electrodes of the memory cells adjacent to.

  The transfer voltage Vpass.h2 is higher than the transfer voltage Vpass applied to the control gate electrode of the non-selected cell and lower than the transfer voltage Vpass.h1 applied to the control gate electrode of the adjacent cell. That is, Vpass <Vpass.h2 <Vpass.h1.

  By providing Vpass.h2 to the control gate electrode of the memory cell adjacent to the source line side / bit line side of the adjacent cell, the coupling ratio of the memory cell MC (k) due to capacitive coupling is further increased, and the non-selected cell Prevents erroneous writing.

FIG. 17 shows the voltage relationship in the NAND cell unit at the time of programming.
The selected cell is a memory cell MC (k) that exists in the center of the NAND string.

  A program voltage Vpgm is applied to the control gate electrode CG of the memory cell MC (k). Further, the memory cell MC (k) adjacent to the source line SL side and the memory cell (non-selected cell) MC (k−1) adjacent to the control gate electrode CG and the memory cell MC (k) adjacent to the bit line BL side. A transfer voltage Vpass.h1 is applied to each control gate electrode CG of the cell (non-selected cell) MC (k + 1).

  Further, a memory cell (unselected cell) MC (k−2) further adjacent to the source line SL side of a memory cell (unselected cell) MC (k−1) adjacent to the source line SL side of the memory cell MC (k). ) And the memory cell (unselected cell) MC adjacent to the bit line BL side of the memory cell (unselected cell) MC (k + 1) adjacent to the bit line BL side of the memory cell MC (k). The transfer voltage Vpass.h2 is applied to at least one of the control gate electrodes (k + 2).

  The remaining memory cells (non-selected cells) MC (k-3), MC () other than the memory cells MC (k), MC (k-1), MC (k + 1), MC (k-2), MC (k + 2) A transfer voltage Vpass lower than the transfer voltage Vpass.h2 is applied to the control gate electrode CG of k + 3).

  The magnitude relationship between these four voltages is Vpass <Vpass.h2 <Vpass.h1 <Vpgm.

  Vpass, Vpass.h2, Vpass.h1, and Vpgm have a value that is equal to or greater than a value that turns on the memory cells MC (k−3),... MC (k + 3) in the NAND string regardless of their threshold values.

FIG. 18 shows a first example of voltage application timing for the device of FIG.
Here, only four of Vpass, Vpass.h2, Vpass.h1, and Vpgm according to the present invention are shown.

  First, at time t1, the transfer voltage Vpass is applied to the control gate electrodes CG of all the memory cells MC (k−3),... MC (k + 3) in the NAND string of the selected block. That is, the transfer voltages Vpass.h1 and Vpass.h2 and the program voltage Vpgm are set to Vpass as an intermediate value before reaching the maximum value.

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and four memory cells (non-selected cells) MC (k− adjacent to both sides of the memory cell MC (k) are displayed. 1) The voltage of the control gate electrode CG of MC (k + 1), MC (k-2), MC (k + 2) is further raised from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is set to Vpgm (maximum value), and the memory cells (adjacent cells) MC (k−1) and MC (k + 1) are controlled. The voltage of the gate electrode CG is set to Vpass.h1 (maximum value), and the voltage of the control gate electrode CG of the memory cells (non-selected cells) MC (k−2) and MC (k + 2) is set to Vpass.h2 (maximum value). .

  At this time, the potential Vfg (k) Inv. Of the floating gate electrode FG of the memory cell MC (k) becomes a value represented by the expression (1) of the first embodiment, and similarly to the first embodiment, the memory cell ( Insufficient writing of the selected cell) MC (k) can be prevented.

  Further, as shown by the equation (4) in the first embodiment, when the amount of electrons injected into the floating gate electrode is constant, the program voltage can be lowered by ΔVpgm than the conventional one. Thereby, a leak current generated between the control gate electrode CG and the floating gate electrode FG can be suppressed.

  Another example of voltage application timing for the device of FIG. 17 will be described.

FIG. 19 shows a second example of voltage application timing for the device of FIG.
The feature of the second example is that the transfer voltage Vpass.h1 is maximized after the program voltage Vpgm is maximized.

The transfer voltage Vpass.h2 is set to the maximum value simultaneously with the program voltage Vpgm.
However, like the transfer voltage Vpass.h1, the transfer voltage Vpass.h2 may be maximized after the program voltage Vpgm is maximized.

  First, at time t1, the transfer voltage Vpass is applied to the control gate electrodes CG of all the memory cells MC (k−3),... MC (k + 3) in the NAND string of the selected block. That is, the transfer voltages Vpass.h1 and Vpass.h2 and the program voltage Vpgm are set to Vpass as an intermediate value before reaching the maximum value.

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and four memory cells (non-selected cells) MC (k− adjacent to both sides of the memory cell MC (k) are displayed. 1) The voltage of the control gate electrode CG of MC (k + 1), MC (k-2), MC (k + 2) is further raised from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is set to Vpgm (maximum value), and the memory cells (non-selected cells) MC (k−2), MC (k + 2) The voltage of the control gate electrode CG is set to Vpass.h2 (maximum value), and the voltage of the control gate electrode CG of the memory cells (adjacent cells) MC (k−1) and MC (k + 1) is set to Vpass.h2 (intermediate value). .

  At time t4, the voltage of the control gate electrode CG of the memory cells (adjacent cells) MC (k−1) and MC (k + 1) is further increased from Vpass.h2, and at time t5, the memory cells (adjacent cells) The voltage of the control gate electrode CG of MC (k−1), MC (k + 1) is set to Vpass.h1 (maximum value).

  In the second example, by delaying the timing when Vpass.h1 reaches the maximum value, the possibility of erroneous writing to the memory cells (adjacent cells) MC (k−1) and MC (k + 1) can be eliminated. In addition, since the problem of insufficient writing occurs when the threshold value of the memory cell becomes high to some extent, the delay in the timing at which Vpass.h1 reaches the maximum value has no effect on the effect of the present invention of eliminating the insufficient writing. Absent.

  Further, by giving Vpass.h2 to the memory cells (non-selected cells) MC (k-2) and MC (k + 2), the memory cells MC (k-1), MC (k + 1), MC (k-2), Capacitance interference occurring in MC (k + 2) can be suppressed.

FIG. 20 shows a third example of voltage application timing for the device of FIG.
The characteristic of the third example is that the program voltage Vpgm is maximized after the transfer voltages Vpass.h1, Vpassh2 are maximized.

  First, at time t1, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) and the four memory cells MC (k−1), MC (k + 1) adjacent to both sides of the memory cell MC (k). ), (K−2), and MC (k + 2) other than the memory cell MC (k−3) and MC (k + 3), the transfer voltage Vpass is applied to the control gate electrode CG.

  Further, a transfer voltage Vpass.h1 higher than the transfer voltage Vpass is applied to the control gate electrodes CG of the two memory cells MC (k−1) and MC (k + 1) adjacent to both sides of the memory cell MC (k).

  Further, the control gate electrode CG of the memory cell MC (k−2) adjacent to the source line side of the memory cell MC (k−1) and the memory cell MC (adjacent to the bit line side of the memory cell MC (k + 1)) A transfer voltage Vpass.h2 higher than the transfer voltage Vpass and lower than the transfer voltage Vpass.h1 is applied to the control gate electrode CG of k + 2).

  Thereafter, at time t2, the voltage of the control gate electrode CG of the memory cell (selected cell) MC (k) is further raised from Vpass.

  At time t3, the voltage of the control gate electrode CG of the memory cell MC (k) is set to Vpgm (maximum value).

  In the third example, the timing at which Vpass.h1 and Vpass.h2 become maximum values is advanced, but by adjusting the values of the transfer voltages Vpass.h1 and Vpass.h2, the memory cells MC (k−1), The possibility of erroneous writing to MC (k + 1), MC (k-2), and MC (k + 2) can be eliminated. Also, the problem of insufficient writing can be solved by giving Vpass.h1.

  Next, a specific programming method for the NAND string in the selected block will be described with reference to FIGS.

  In order to simplify the following description, it is assumed that the NAND string is composed of four memory cells which are the minimum values for carrying out the present invention. Further, consider a case where “0” is programmed for the memory cell connected to the bit line BL1, and “1” is programmed for the memory cell connected to the bit line BL2.

  The initial state of the memory cell in the NAND string is an erased state (“1” state).

  In this case, the bit line BL1 is set to “0” -low voltage Vbl1 (eg, 0V) for programming, and the bit line BL2 is set to “1” -positive voltage Vbl2 (eg, 1.2V). -4.0V).

The voltage Vsgd is applied to the bit line side select gate line SGD. The value of Vsgd is
Vth_sgd (0) <Vsgd <Vbl2 + Vth_sgd (Vbl2)
Shall be satisfied.

  However, Vth_sgd means a threshold voltage of the bit line side select gate transistor, and () means a back bias voltage applied to the source of the bit line side select gate transistor.

  Normally, Vsgd is set to the same value as Vbl2.

  Further, a voltage Vsgs (for example, 0 V) for cutting off the source line side select gate transistor is applied to the source line side select gate line SGS.

  The source line SL is set to Vs, for example, 0V.

  As a result, the bit line side select gate transistor connected to the bit line BL1 is turned on, and the voltage Vbl1 is transferred from the bit line BL1 to the channel of the memory cell in the NAND string.

  Therefore, when Vpgm is applied to the selected word line, in the selected cell, electrons are injected from the channel into the charge storage layer (for example, floating gate electrode), and writing (threshold increase) is performed.

  On the other hand, in the bit line side select gate transistor connected to the bit line BL2, for example, when the transfer voltages Vpass, Vpass.h1, Vpass.h2 are applied to the word line, the channel of the memory cell in the NAND string is capacitively coupled. Since it is boosted by the ring, it automatically cuts off.

  In addition, when Vpgm is applied to the selected word line, the channel voltage of the selected cell further increases. Therefore, in the selected cell, electrons are not injected from the channel into the charge storage layer, and writing is prohibited (erasure state is maintained).

  In such a programming operation, a transfer voltage Vpass.h1 higher than the transfer voltage Vpass is applied to the control gate electrodes of two adjacent cells adjacent to both sides of the selected cell, that is, the word line. A transfer voltage Vpass.h2 higher than the transfer voltage Vpass and lower than the transfer voltage Vpass.h1 is applied to the control gate electrode of the memory cell adjacent to the source line side / bit line side, that is, the word line.

  21 and 22, among the four memory cells constituting the NAND string, the two endmost memory cells adjacent to the source line side / bit line side select gate transistor are the dummy cells DUMMY that are not programming targets. It is an example.

  For example, programming is sequentially performed one by one from the memory cell on the source line side to the memory cell on the drain side.

  First, as shown in FIG. 21, the program voltage Vpgm is applied to the word line WL2, the transfer voltage Vpass.h1 is applied to the word lines WL1 and WL3, and the transfer voltage Vpass.h2 is applied to the word line WL4. Then, programming is performed on the memory cell (selected cell) connected to the word line WL2.

  Next, as shown in FIG. 22, the program voltage Vpgm is applied to the word line WL3, the transfer voltage Vpass.h1 is applied to the word lines WL2 and WL4, and the transfer voltage Vpass.h2 is applied to the word line WL1. Then, programming is performed for the memory cell (selected cell) connected to the word line WL3.

  FIG. 23 to FIG. 26 are examples in which all four memory cells constituting the NAND string are targeted for programming.

  For example, programming is sequentially performed one by one from the memory cell on the source line side to the memory cell on the drain side.

  First, as shown in FIG. 23, a program voltage Vpgm is applied to the word line WL1, a transfer voltage Vpass.h1 is applied to the word line WL2, a transfer voltage Vpass.h2 is applied to the word line WL3, and a transfer voltage Vpass is applied to the word line WL4. give. Then, programming is performed for the memory cell (selected cell) connected to the word line WL1.

  Here, when programming a memory cell (selected cell) connected to the word line WL1, there is only one adjacent cell on the bit line side adjacent to the selected cell. What is necessary is just to give Vpass.h1 to the one adjacent cell.

  Next, as shown in FIG. 24, the program voltage Vpgm is applied to the word line WL2, the transfer voltage Vpass.h1 is applied to the word lines WL1 and WL3, and the transfer voltage Vpass.h2 is applied to the word line WL4. Then, programming is performed on the memory cell (selected cell) connected to the word line WL2.

  Next, as shown in FIG. 25, the program voltage Vpgm is applied to the word line WL3, the transfer voltage Vpass.h1 is applied to the word lines WL2 and WL4, and the transfer voltage Vpass.h2 is applied to the word line WL1. Then, programming is performed for the memory cell (selected cell) connected to the word line WL3.

  Finally, as shown in FIG. 26, the program voltage Vpgm is applied to the word line WL4, the transfer voltage Vpass.h1 is applied to the word line WL3, the transfer voltage Vpass.h2 is applied to the word line WL1, and the transfer voltage is applied to the word line WL2. Give Vpass. Then, programming is performed for the memory cell (selected cell) connected to the word line WL4.

  Here, when programming is performed on the memory cell (selected cell) connected to the word line WL4, there is only one adjacent cell on the source line side adjacent to the selected cell. What is necessary is just to give Vpass.h1 to the one adjacent cell.

  As described above, according to the second embodiment, by providing Vpass.h1 higher than Vpass to two adjacent cells existing on both sides of the selected cell, it is possible to eliminate insufficient writing to the selected cell.

  Further, by applying a transfer voltage Vpass.h2 higher than Vpass and lower than the transfer voltage Vpass.h1 to two memory cells existing on the source line side / bit line side of two adjacent cells, Incorrect writing can be prevented.

(3) Summary
As described above, according to the present invention, insufficient writing to the selected cell is performed by applying the transfer voltage Vpass.h1 to the control gate electrodes of two adjacent cells (non-selected cells) adjacent to both sides of the selected cell. Can be eliminated.

3. Modified example
Some of the modified examples of the present invention will be described.

(1) Multi-level NAND type nonvolatile semiconductor memory
The present invention is not limited to the number of values stored in one memory cell.

  In the above-described embodiment, binary is assumed. However, the NAND nonvolatile semiconductor memory of the present invention may be a multi-level memory that stores three or more values in one memory cell.

  As already described, in the NAND type nonvolatile semiconductor memory to which the multi-value technology is applied, three or more threshold distributions must be set within a predetermined voltage range. In this case, the threshold distribution must be provided at a high position within a predetermined voltage range.

  In view of such a situation, the programming technique of the present invention is effective for programming data having the highest threshold voltage when, for example, data of three or more values is stored in a memory cell to be programmed.

  Specifically, taking a quaternary memory as an example, the present invention applies to “3” -write among four data “0”, “1”, “2”, “3” stored in a memory cell. The conventional method is used for “1” -write and “2” -write.

  However, “0” is the erased state (initial state) and the threshold voltage is the lowest, and “3” is the highest threshold voltage, that is, “0” <“1” <“2” <“3” It shall have.

  Of course, there is no problem even if the present invention is applied to “1” -write and “2” -write.

  According to the present invention, since the threshold distribution can be provided even at a high position within a predetermined voltage range by eliminating the shortage of writing, the present invention is a very effective technique for realizing a multi-value memory. I can say that.

(2) Programming order
In the above-described embodiment, the sequential programming method in which the programming is sequentially performed one by one from the memory cell on the most source line side toward the memory cell on the most bit line side among the plurality of memory cells in the NAND cell unit has been described. However, the present invention is naturally applicable to a random program system.

(3) Sense method
As a sensing method for reading data of memory cells, a shield bit line sensing method in which all bit lines are divided into even bit lines and odd bit lines and reading is performed, and ABL (All Bits) in which data of all bit lines are read simultaneously. Line) sense method.

  The programming method of the present invention can be combined with each other to realize a NAND type nonvolatile semiconductor memory.

(4) Page setting
A group consisting of a plurality of memory cells connected to one word line is usually defined as one page.

  However, in recent years, a plurality of pages may be assigned to a group consisting of a plurality of memory cells connected to one word line. Even in such a case, the programming method of the present invention can be applied without any change.

(5) Channel boosting method
In the present invention, when changing the threshold value of the selected cell, the channel of the selected cell is fixed to a fixed potential (for example, 0 V), and when the threshold value of the selected cell is not changed, the channel of the selected cell is higher than the fixed potential. Boost to potential.

  As such a method, a self-boost method, a local self-boost method, an erase area self-boost (ESB) method, or a modified method thereof is known. Of course, this method can also be applied.

(6) Step-up writing
When programming is performed to increase the threshold value of the selected cell during programming, the program voltage may be set to a maximum value through a plurality of steps. In this case, the value of the transfer voltage applied to the adjacent cell may be lower than the maximum value of the program voltage.

  Further, there may be a period in which the program voltage has the same value as the value of the transfer voltage before reaching the maximum value.

(7) Memory cell structure
In the above embodiment, the memory cell is premised on a stack gate structure having a floating gate electrode and a control gate electrode, but the memory cell structure is not limited to this.

FIG. 27 shows a MONOS type memory cell.
The MONOS type refers to a nonvolatile semiconductor memory cell in which the charge storage layer is formed of an insulating film.

  A source / drain diffusion layer 26 is arranged in the semiconductor substrate (active area) 25. On the channel region between the source / drain diffusion layers 26, a gate insulating film (tunnel insulating film) 27, a charge storage layer 28, a block insulating film 29, and a control gate electrode (word line) 30 are disposed.

  The block insulating film 29 is made of, for example, an ONO (oxide / nitride / oxide) film, a high dielectric constant (high-k) material, or the like.

4). Application examples
An example of a system to which the NAND type nonvolatile semiconductor memory of the present invention is applied will be described.

FIG. 28 shows an example of a memory system.
This system is, for example, a memory card or a USB memory.

  In the package 31, a circuit board 32 and a plurality of semiconductor chips 33, 34, and 35 are arranged. The circuit board 32 and the semiconductor chips 33, 34, and 35 are electrically connected by bonding wires 36. One of the semiconductor chips 33, 34, and 35 is a NAND type nonvolatile semiconductor memory according to the present invention.

FIG. 29 shows a chip layout.
On the semiconductor chip 40, memory cell arrays 41A and 41B are arranged. Memory cell arrays 41A and 41B have blocks BK0, BK1,... BKn−1 arranged in the second direction, respectively. Each of the blocks BK0, BK1,... BKn−1 has a plurality of cell units CU arranged in the first direction.

  As shown in FIG. 30, the cell unit CU is a NAND string composed of a plurality of memory cells MC connected in series in the second direction, and two select gate transistors ST connected one to the both ends. is there.

  Bit lines BL extending in the second direction are arranged on the memory cell arrays 41A and 41B, respectively. Page buffers (PB) 43 are arranged at both ends in the second direction of the memory cell arrays 41A and 41B. The page buffer 43 has a function of temporarily storing read data / write data during read / write. The page buffer 43 functions as a sense amplifier (S / A) at the time of reading or at the time of verifying the write / erase operation.

  A row decoder (RDC) 44 is disposed at one end of the memory cell arrays 41A and 41B in the first direction (the end opposite to the end on the edge side of the semiconductor chip 40). A pad area 42 is arranged along the edge of the semiconductor chip 40 on one end side in the second direction of the memory cell arrays 41A and 41B. A peripheral circuit 45 is arranged between the page buffer 43 and the pad area 42.

5. Conclusion
According to the present invention, insufficient writing of a selected cell can be prevented.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

The block diagram which shows a NAND type non-volatile semiconductor memory. FIG. 3 is a diagram illustrating a circuit example of a memory cell array and a word line driver. The top view of a NAND cell unit. Sectional drawing of a NAND cell unit. The figure which shows the voltage relationship of the programming system of 1st Embodiment. The figure which shows the 1st example of the timing of the voltage given to a word line. The figure which shows the 2nd example of the timing of the voltage given to a word line. The figure which shows the change of the electric potential of a floating gate electrode. The figure which shows the 3rd example of the timing of the voltage given to a word line. The figure which shows the 4th example of the timing of the voltage given to a word line. The figure which shows the 1st example of the programming method. The figure which shows the 1st example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the voltage relationship of the programming system of 2nd Embodiment. The figure which shows the 1st example of the timing of the voltage given to a word line. The figure which shows the 2nd example of the timing of the voltage given to a word line. The figure which shows the 3rd example of the timing of the voltage given to a word line. The figure which shows the 1st example of the programming method. The figure which shows the 1st example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows the 2nd example of the programming method. The figure which shows a MONOS type | mold memory cell. The figure which shows the system as an application example. The figure which shows the chip layout as an application example. The figure which shows a NAND cell unit.

Explanation of symbols

  11: Memory cell array, 12: Data latch circuit, 13: I / O buffer, 14: Address buffer, 15: Row decoder, 16: Column decoder, 17: Word line driver, 18: Substrate voltage control circuit, 19: Voltage generation Circuit: 20: Control circuit, 21: Transfer transistor unit, 22: Booster, 24: Selector, 25: Semiconductor substrate, 26: Source / drain diffusion layer, 27: Gate insulating film, 28: Charge storage layer, 29: Block insulation Membrane, 30: Control gate electrode, 31: Package, 32: Circuit board, 33, 34, 35, 40: Semiconductor chip, 36: Bonding wire, 41A, 41B: Memory cell array, 42: Pad area, 43: Page buffer,4: row decoder, 45: peripheral circuits.

Claims (5)

  N (n is an integer of 4 or more) memory cells having a charge storage layer and a control gate electrode and connected in series to each other, and nth memory cells connected between one end of the n memory cells and a source line. One select gate transistor, a second select gate transistor connected between the other end of the n number of memory cells and the bit line, and a target of programming among the n number of memory cells during programming A first voltage is applied to the control gate electrode of the first memory cell and adjacent to the control gate electrode of the second memory cell adjacent to the source line side of the first memory cell and the bit line side of the first memory cell. A second voltage lower than the first voltage is applied to each control gate electrode of the third memory cell, and among the n memory cells, A driver that applies a third voltage lower than the second voltage to the control gate electrodes of the remaining memory cells other than the first, second, and third memory cells, and the first, second, and third voltages are: A NAND-type non-volatile semiconductor memory characterized by having a value equal to or greater than a value for turning on the n memory cells regardless of their threshold values.   The driver is lower than the second voltage at a control gate electrode of a fourth memory cell adjacent to the source line side of the second memory cell or the bit line side of the third memory cell during the programming, The NAND-type nonvolatile semiconductor memory according to claim 1, wherein a fourth voltage higher than the third voltage is applied.   3. The nmost memory cells adjacent to the first and second select gate transistors among the n memory cells are dummy cells that are not subject to the programming. The NAND-type nonvolatile semiconductor memory described.   During the programming, the first voltage reaches a maximum value through a plurality of steps, the second and third voltages are lower than the maximum value, and the second voltage is determined by the first voltage being the maximum value. The NAND-type nonvolatile semiconductor memory according to claim 1, wherein the NAND-type nonvolatile semiconductor memory has a maximum value after becoming.   5. The programming of the first memory cell according to claim 1, wherein programming of the data having the highest threshold voltage among data of three or more values stored in the first memory cell is performed. The NAND-type nonvolatile semiconductor memory according to item.

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