KR101213729B1 - Semiconductor memory device a method of driving the same - Google Patents

Abstract

The present invention can minimize the program disturb and pass disturb by precharging the prepass voltage lower than the pass voltage to the word lines adjacent to the select word line before applying the program voltage to the select word line. A semiconductor memory device and a driving method thereof are provided. A semiconductor memory device according to an embodiment of the present invention provides a row select circuit for applying a pre-pass voltage lower than a pass voltage to at least one unselected adjacent word line adjacent to a selected word line based on an address signal. And a memory cell array coupled to the row select circuit through a plurality of word lines, the unselected adjacent memory cells coupled to the unselected adjacent word line and precharged based on the prepass voltage.

Description

Semiconductor memory device and driving method therefor {Semiconductor memory device a method of driving the same}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of minimizing interference between adjacent memory cells by precharging the memory cells adjacent to the programmed memory cells. It is about.

Semiconductor memory devices used in portable devices are required to be highly integrated due to the characteristics of the portable devices. The semiconductor memory device may be divided into a volatile memory device and a nonvolatile memory device according to whether data can be maintained when power is cut off.

The flash memory device included in the nonvolatile memory device may be classified into a NOR flash memory device and a NAND flash memory device according to the structure of the memory cell. In NOR flash memory devices, memory cells are connected between bit lines and word lines that cross each other, and in NAND flash memory devices, a plurality of memory cells connected in series through word lines corresponding to one bit line are respectively NAND cell strings. To form. NOR flash memory can be accessed in units of memory cells, and NAND flash memory is suitable for miniaturization due to high integration of memory cells. The NOR flash memory device may be used as a code storage device, and the NAND flash memory device may be used as a data storage device.

SUMMARY OF THE INVENTION The present invention provides a prepass voltage lower than a pass voltage for a word line adjacent to a selected word line during a program operation so that a program voltage is applied to a selected word line. The present invention provides a semiconductor memory device and a driving method thereof for preventing selected memory cells from being programmed.

A semiconductor memory device according to an embodiment of the present invention provides a row select circuit for applying a pre-pass voltage lower than a pass voltage to at least one unselected adjacent word line adjacent to a selected word line based on an address signal. And a non-selected adjacent memory cell connected to the row select circuit through a plurality of word lines and connected to the unselected adjacent word line and precharged based on the pre-pass voltage. Include.

A method of driving a semiconductor memory device according to an embodiment of the present invention may include a prepass voltage having a voltage level smaller than a pass voltage for an unselected adjacent word line adjacent to a selected word line in response to a prepass activation signal. Applying a pass voltage to the plurality of word lines included in the memory cell array in response to a pass activation signal, and applying a program voltage to the selected word line in response to a program activation signal. It includes.

The semiconductor memory device according to the embodiments of the present invention minimizes program disturb by applying a pre-pass voltage having a voltage level lower than the pass voltage to unselected adjacent word lines adjacent to a selected memory cell to be programmed. can do.

In addition, the method of driving the semiconductor memory device according to the embodiments of the present invention adaptively reduces the program disturb phenomenon by applying different pre-pass voltages to unselected adjacent word lines adjacent to the program memory cell. Can improve the operation reliability.

1 is a circuit diagram illustrating a memory cell array in accordance with an embodiment of the present invention.
2A and 2B are diagrams for describing a program disturb and a pass disturb phenomenon.
3 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
4 is a flowchart illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention.
5 to 7 are waveform diagrams illustrating voltage changes for explaining a method of driving a semiconductor memory device according to example embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a memory cell array in accordance with an embodiment of the present invention.

1 illustrates a NAND type memory cell array, but the present invention is not limited thereto.

Referring to FIG. 1, a memory cell array includes a selection coupled to a plurality of bit lines BL1, BL2, BL3,..., BLn, a string select line SSL, a ground select line GSL, and select lines. The memory cells M11, ..., M16n coupled to the memory cells ST11, ..., ST1n, GT11, ..., GT1n, and the plurality of word lines WL1, ..., WL16 Include.

For example, when the memory cell M32 is programmed, the program voltage Vpgm is applied to the select word line WL3 coupled to the memory cell M32, and the unselected word lines WL1, WL2, WL4, ..., a pass voltage Vpass is applied to WL16.

The program operation refers to a state in which electrons are accumulated in a floating gate of a memory cell implemented in a transistor form. The erase operation refers to an operation of removing electrons stored in the floating gate by removing the electrons stored in the floating gate to the surface of the channel. When the erase operation is performed, a threshold voltage Vth decreases. For example, when the memory cell M32 is programmed with the data # 0 ', the threshold voltage Vth increases, and when the memory cell M32 is programmed with the data # 1', the threshold voltage Vth of the erased state can be maintained. .

According to an embodiment, when the pass voltage Vpass applied to the unselected word lines WL1, WL3,..., WL16 is increased, the non-selected adjacent to the memory cell M32 programmed to the data # 0 'is increased. Threshold voltages of the memory cells M12, M22, M42,..., And M162 may increase. That is, unselected memory cells M1n, M2n, M4n, ..., M16n may be programmed. For example, this phenomenon is called Vpass disturbance.

According to an embodiment, when the pass voltage Vpass applied to the unselected word lines WL1, WL2, WL4,..., WL16 decreases, the word line WL3 coupled to the selected memory cell M32 is reduced. The program voltage Vpgm is simultaneously applied to the memory cells M31 and M33 connected along the same. Therefore, due to the coupling between the channel region of the adjacent memory cells M21 and M23 and the floating gate under the influence of the program voltage Vpgm, the charge is charged in the floating gate to change the threshold voltage. Therefore, an unintended program can be executed. This phenomenon is referred to as program disturb (Vpgm disturbance).

2A and 2B are diagrams for describing a program disturb and a pass disturb phenomenon.

2A is a diagram illustrating a change in threshold voltage according to an increase in a pass voltage.

In FIG. 2A, the X axis represents a voltage level of a pass voltage Vpass applied to unselected word lines, and the Y axis represents a change in threshold voltages of memory cells.

Referring to FIG. 2A, the program disturb phenomenon is most severe when the pass voltage Vpass has a magnitude of about 8V. As the magnitude of the pass voltage Vpass increases, the program disturb phenomenon decreases, but a pass disturb phenomenon occurs.

If the threshold voltage of the memory cells is changed, even if the desired program voltage Vpgm is applied, the charge may not be charged to the floating gate, which may cause a program operation failure and reduce the program state distribution characteristic. Is lowered.

The program disturb and the pass disturb are in a trade off relationship, and the most optimal pass voltage level can be selected for the two phenomena.

FIG. 2B is a diagram illustrating a pass voltage section for preventing each phenomenon according to the program disturb and pass disturb phenomenon observed in FIG. 2A.

As described above, the program disturb phenomenon occurs as the pass voltage Vpass decreases, and the pass disturb phenomenon occurs as the pass voltage Vpass increases. The pass voltage Vpass level is determined according to a pass voltage Vpass section for preventing program disturb and pass disturb.

3 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device may include a controller 200, a voltage generator 300, an address buffer 500, a row select circuit 400, a memory cell array 100, a column select circuit 600, And an input / output buffer 700.

The controller 200 may communicate with an external device such as a host, and may include a voltage generation control signal VCON, an address signal ADDR, a free pass activation signal PREN, a pass activation signal PASSEN, and a program activation signal PGMEN) can be generated.

The controller 200 may provide signals generated in the voltage generator 300, the address buffer 500, the row select circuit 400, and the like to control the overall operation of the semiconductor memory device 10.

The controller 200 may include a program control circuit implemented separately, and the program control circuit may control a program operation of the semiconductor memory device 10.

The voltage generator 300 may generate a program voltage Vpgm, a pass voltage Vpass, and a free pass voltage Vprep based on the voltage generation control signal VCON. When the program is performed on the memory cell array 100, it is required to maintain the difference between the program voltage Vpgm and the pass voltage Vpass at a constant level. The voltage generator 300 according to the present invention generates the program voltage Vpgm, the pass voltage Vpass, and the free pass voltage Vprep. The pre-pass voltage Vprep has a voltage level smaller than the program voltage Vpgm and the pass voltage Vpass.

In some embodiments, the pre-pass voltage Vprep may be provided before the program voltage Vpgm and the pass voltage Vpass are applied.

The row select circuit 400 provides a voltage corresponding to each word line of the memory cell array 100 based on the row select signal XADDR provided through the address buffer 500. For example, the row select circuit 400 provides a program voltage Vpgm for the selected word line connected to the selected memory cell, and applies a pass voltage Vpass to the plurality of unselected word lines except for the selected word line. Can provide. However, the row select circuit 400 according to an exemplary embodiment of the present invention may apply a program voltage Vpgm and a pass voltage Vpass to an unselected adjacent word line adjacent to the selected word line among a plurality of unselected word lines. The pre-pass voltage Vprep is applied before the application. By applying the pre-pass voltage Vprep first, it is possible to prevent program disturb and pass disturb that may occur when the program voltage Vpgm is subsequently applied to the selected word line.

The program voltage Vpgm is provided to the selected word line of the memory cell array 100 in response to the program activation signal PGMEN provided by the controller 200, and the prepass voltage Vprep is a prepass activation signal PREN. In response to the non-selected adjacent word line of the memory cell array 100, the pass voltage Vpass is applied to both the selected and unselected word lines of the memory cell array 100 in response to the pass enable signal PASSEN. Can be provided.

For example, the free pass activation signal PREN, the pass activation signal PASSEN, and the program activation signal PGMEN may be sequentially activated.

The column select circuit 600 may receive a column address YADDR through the address buffer 500 to provide an appropriate voltage to the memory cell array 100. The column select circuit 600 may be connected to the memory cell array 100 through a bit line, may provide a voltage corresponding to data to be written to the selected bit line during a program operation, and may be provided through the bit line during a read operation. Data may be read from the memory cell corresponding to the selected address.

The input / output buffer 700 may receive an input signal to input write data to the column select circuit 600 or receive an output signal from the column select circuit 600 to provide an output signal to the outside. In FIG. 3, an input signal and an output signal are shown as input / output signals (I / O).

Therefore, the semiconductor memory device 10 according to an embodiment of the present invention precharges the pre-pass voltage Vprep by pre-charging the unselected adjacent word lines adjacent to the selected word line provided with the program voltage Vpgm. The channel voltage of the memory cells adjacent to the selected memory cell is increased to prevent program disturb and pass disturb that may occur when the program voltage Vpgm is applied.

4 is a flowchart illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, a program voltage Vpgm, a pass voltage Vpass, and a free pass voltage Vprep may be generated based on the voltage generation control signal VCON provided by the controller 200 (step S410). . The voltage generation control signal VCON may control the voltage levels of the respective voltages and control the voltage generation time.

The row select circuit 400 applies the prepass voltage Vprep to an unselected adjacent word line adjacent to the selected word line based on the row select signal XADDR in response to the prepass activation signal PREN (step S420). .

For example, in FIG. 1, second and fourth word lines WL2 and WL4 and first and fifth word lines adjacent to a third word line WL3, which is a selected word line connected to the selection memory cell M32. (WL1, WL5) may correspond to an unselected adjacent word line. According to an exemplary embodiment, the second and fourth word lines WL2 and WL4, which are directly adjacent to the third word line WL3, which is the selected word line, may be the first non-selected adjacent word line, and the selected word line and the first non-selected word line. Adjacent first and fifth word lines WL1 and WL5 may be represented as a second non-selected adjacent word line with an adjacent word line therebetween.

In some embodiments, the pre-pass voltage Vprep applied to the first non-selected adjacent word line and the second non-selected adjacent word line may have different values. For example, the pre-pass voltage Vprep provided to the first non-selected adjacent word line is the first pre-pass voltage Vprep1, and the pre-pass voltage Vprep provided to the second non-selected adjacent word line is the second. It may be represented by the free pass voltage Vprep2. The first prepass voltage Vprep1 may have a voltage level higher than the second prepass voltage Vprep2. However, the first pre-pass voltage Vprep1 and the second pre-pass voltage Vprep2 may be provided to the first non-selected adjacent word line and the second non-selected adjacent word line, respectively, in response to the pre-pass activation signal PREN. Therefore, the time points applied to the memory cell array 100 may be substantially the same.

When the pre-pass voltage Vprep is applied to the unselected adjacent word line, the channel voltage of the memory cells connected to the unselected adjacent word line rises, and also the memory cells M31, M33, which are connected to the selected word line but not programmed. ..., M3n) Also, the channel voltage is increased due to capacitive coupling with an unselected adjacent word line, so that the program voltage Vpgm is not applied to the selected word line.

The row select circuit 400 applies a pass voltage Vpass to all word lines included in the memory cell array in response to the pass activation signal PASSEN (step S430). As described above, since the pass voltage Vpass has a lower voltage level than the program voltage Vpgm, the pass voltage Vpass is applied after the pass voltage Vpass is applied rather than directly applying the program voltage Vpgm to the selected word line. Applying a higher program voltage Vpgm may minimize coupling to memory cells adjacent to the selected memory cell.

The row select circuit 400 applies a program voltage Vpgm to the selected word line to which the selected memory cell is connected in response to the program activation signal PGMEN (step S440). The application of the program voltage Vpgm to the selected word line may be different depending on the program method used in the semiconductor memory device 10.

According to an embodiment, the programming method of the semiconductor memory device 10 may include an incremental step pulse program method. Based on the incremental step pulse program method, the program voltage Vpgm may be sequentially increased, and a verify voltage for verifying a program state may be applied between the times when the program voltage Vpgm is increased.

When the program for the selected memory cell is completed, the ground voltage GND may be provided to the plurality of word lines of the memory cell array 100 to inactivate the word line. According to an embodiment, a time point at which the selected word lines and the non-selected word lines are deactivated may be controlled differently. Since the voltage level of the program voltage Vpgm is higher than the pass voltage Vpass at the time when the program operation is completed, the time required for the program voltage Vpgm to fall to the ground voltage GND level is the pass voltage. (Vpass) is relatively longer than the time it takes to lower to ground voltage (GND) level. Therefore, the time when the selected word line is inactivated may be set before the time when the non-selected word line is inactivated, so that all the word lines become the ground voltage GND level.

5 to 7 are waveform diagrams illustrating voltage changes for explaining a method of driving a semiconductor memory device according to example embodiments.

5 to 7, SSL is the voltage level of the source select line, WL1 to WL 16 is the voltage level of the first to 16th word lines, the voltage level of the GSL ground select line, PREN is the voltage level of the free pass activation signal , PASSEN represents the voltage level of the pass activation signal, and PGMEN represents the voltage level of the program activation signal.

In the present specification, the memory cell M32 included in the third word line WL3 is a selected memory cell based on the address signal ADDR. In addition, the number of word lines of the memory cell array 100 has been described as 16, but is not limited thereto.

FIG. 5 is a waveform diagram illustrating a case where a substantially same pre-pass voltage Vprep is applied to an unselected adjacent word line directly adjacent to the selected word line.

Referring to FIG. 5, the source select line SSL maintains a power supply voltage Vcc level and the ground select line GSL maintains a ground voltage GND level during a program operation. The voltage levels of the source select line SSL and the ground select line GSL are the same in FIGS. 5 to 7.

In the program operation, a ground voltage GND may be provided to a bit line connected to a selected memory cell, and a power supply voltage Vcc may be provided to unselected bit lines.

At the time t1, the row select circuit 400 frees the second and fourth word lines WL2 and WL4 directly adjacent to the third word line WL3, which is the select word line, in response to the pass activation signal PREN. The pass voltage Vprep is applied. In FIG. 5, the second and fourth word lines WL2 and WL4 may be included in an unselected adjacent word line.

The pre-pass voltage Vprep may have a lower voltage level than the pass voltage Vpass. In some embodiments, the voltage level of the pre-pass voltage Vprep is determined to be a value capable of minimizing program disturb and pass disturb. For example, the pre-pass voltage Vprep may have a voltage level of about 20% of the pass voltage Vpass.

When the non-selected adjacent word line is charged with the pre-pass voltage Vprep at a time t1, the plurality of memory cells M21,..., M2n, M41, which are connected to the second and fourth word lines WL2 and WL4, may be charged. The channel voltage of M4n) rises. In addition, the channel voltages of the non-selected memory cells WL31, M33,..., M3n connected to the third word line WL3 are increased to prevent unwanted programming.

At a time t2, the pass voltage Vpass is applied to all word lines WL1,..., WL16 included in the memory cell array 100 in response to the pass activation signal PASSEN. The pass voltage Vpass may also be applied to the select word line WL3.

At time t3, the row select circuit 400 applies a program voltage Vpgm to the select word line WL3 in response to the activation signal PGMEN. A pass voltage Vpass having a voltage level lower than the program voltage Vpgm is applied to the selection word line WL3 before the program voltage Vpgm is applied, thereby applying the program voltage Vpgm at one time. Therefore, the time required for reaching the program voltage Vpgm level can be shortened than when the voltage level is increased, and the coupling phenomenon that can occur in adjacent word lines can be minimized by providing the program voltage Vpgm. At the time t3, the pass voltage Vpass is continuously applied to the unselected word lines WL1, WL2, WL4,..., and WL16 to prevent unwanted programs.

As described above, the program voltage Vpgm may be applied in a different manner according to a program method applied to the semiconductor memory device 10. 5 to 7 illustrate a case in which the incremental step pulse program method is used, and the threshold voltage distribution characteristic of the memory cells may be improved by repeatedly repeating the verification operation while repeatedly increasing the program voltage Vpgm.

When the program verification is completed for the selected memory cell M32, the word line is inactivated to complete the program operation. As described above, since the program voltage Vpgm level may be higher than the pass voltage Vpass level, the selection word line WL3 is inactivated at time t4, and the non-selection word lines excluding the selection word line at time t5 ( WL1, WL2, WL4, ..., WL16) can be deactivated.

However, the time points at which the plurality of word lines WL1,..., WL16 become inactive and become the ground voltage GND level may be substantially the same.

Therefore, in the method of driving the semiconductor memory device according to the embodiment of the present invention, the threshold voltage level is lowered by applying the pre-pass voltage Vprep to the unselected adjacent word lines before charging the program voltage Vpgm. Therefore, program phenomena that may occur in unwanted memory cells can be minimized.

6 is a diagram illustrating a method of programming a semiconductor memory device according to an exemplary embodiment of the present invention, wherein a pre-pass voltage is applied to a word line adjacent to a selected word line through a word line directly adjacent to a word line directly adjacent to the selected word line. It is a waveform chart which shows how to apply Vprep).

At time t1, the pre-pass voltage Vprep is applied to the first, second, fourth, and fifth word lines, that is, the non-selected adjacent word line, in response to the pre-pass activation signal PREN. However, the second and fourth word lines WL2 and WL4, which are directly adjacent to the third word line WL3, which is the selected word line, are represented by the first non-selected adjacent word line, and the third word line WL3 and the third word line are selected. The first and fifth word lines WL1 and WL5 adjacent through the first non-selected adjacent word line may be represented as a second non-selected adjacent word line. The unselected adjacent word line may include first and second unselected adjacent word lines.

When the non-selected adjacent word line is charged with the pre-pass voltage Vprep at a time t1, a plurality of memory cells connected to the first, second, fourth, and fifth word lines WL1, WL2, WL4, and WL5. Their channel voltages will rise. In addition, the channel voltages of the non-selected memory cells WL31, M33,..., M3n connected to the third word line WL3 increase. Therefore, a program disturb phenomenon occurring in the vicinity of the selection memory cell M32 while being connected to the selection word line WL3 and in the word lines WL1, WL2, WL4, and WL5 adjacent to the selection word line WL3 may occur. Pass disturb can be reduced.

According to an embodiment, the row select circuit 400 applies a first pre-pass voltage Vprep1 to the second and fourth word lines WL2 and WL4 included in the first non-selected adjacent word line, and the second The second pre-pass voltage Vprep2 may be applied to the first and fifth word lines WL1 and WL5 included in the unselected adjacent word line. The first pre-pass voltage Vprep1 and the second pre-pass voltage Vprep2 may have substantially the same or different values. For example, the voltage level of the second pre-pass voltage Vprep2 is equal to the first pre-pass. It may be smaller than the voltage level of the voltage Vprep1. However, the voltage levels of the first and second pre-pass voltages Vprep1 and Vprep2 may be controlled by the voltage generation control signal VCON.

At a time t2, the pass voltage Vpass is applied to all word lines WL1,..., WL16 included in the memory cell array 100 in response to the pass activation signal PASSEN. The pass voltage Vpass may also be applied to the select word line WL3.

At a time t3, the program voltage Vpgm is applied to the select word line WL3 in response to the program activation signal PGMEN. At the time t3, the pass voltage Vpass is continuously applied to the unselected word lines WL1, WL2, WL4,..., and WL16 to prevent unwanted programs.

When the program verification is completed for the selected memory cell M32, the word line is inactivated to complete the program operation. As described above, since the program voltage Vpgm level may be higher than the pass voltage Vpass level, the selection word line WL3 is inactivated at time t4, and the non-selection word lines excluding the selection word line at time t5 ( WL1, WL2, WL4, ..., WL16) can be deactivated.

However, the time points at which the plurality of word lines WL1,..., WL16 become inactive and become the ground voltage GND level may be substantially the same. Therefore, in the semiconductor memory device 10 and the driving method thereof according to an embodiment of the present invention, the unselected word lines WL1, WL2, WL4,..., WL16 are grounded when the word line is inactivated. Although the voltage GND is reached, it takes time for the program voltage Vpgm of the selected word line to reach the ground voltage GND, thereby preventing a coupling phenomenon that may occur during the discharge process.

FIG. 7 illustrates a method of driving a semiconductor memory device according to an exemplary embodiment of the present invention, wherein a pre-pass voltage Vprep is applied to first and second non-selected adjacent word lines, and a program voltage Vpgm and a pass voltage. A waveform diagram illustrating a case where a plurality of word lines to which Vpass is applied are deactivated at the same time.

In comparison with FIG. 5, in the method of driving the semiconductor memory device of FIG. 7, the pre-pass voltage Vprep at the time t1 for the second and fourth word lines WL2 and WL4 directly adjacent to the selection word line WL3. ) Is applied.

As compared with FIG. 6, in the driving method of the semiconductor memory device of FIG. 7, the deactivation time points of the program voltage Vpgm and the pass voltage Vpass are substantially the same. Therefore, in this case, the voltage or current discharge driving capability for discharging the third word line WL3 corresponding to the selected word line to the ground voltage GND level may be greater than the driving capability for discharging the unselected word line.

Therefore, in the semiconductor memory device and the driving method thereof according to an embodiment of the present invention, before applying the program voltage Vpgm to the selected memory cell selected on the basis of the address signal, the non-selected adjacent to the selected word line. By applying a pre-pass voltage Vprep lower than the pass voltage Vpass to the word lines to charge the charge in advance, the program disturb and the influence of the pass voltage Vpass may occur due to the program voltage Vpgm. Pass disturb that can occur can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

10: semiconductor memory device
100: memory cell array
200:
300: voltage generator
400: row selection circuit

Claims (14)

A row select circuit for applying a pre-pass voltage lower than a pass voltage to at least one unselected adjacent word line adjacent to the selected word line based on the address signal; And
A memory cell array connected to the row select circuit through a plurality of word lines, the memory cell array including unselected adjacent memory cells connected to the unselected adjacent word line and precharged based on the prepass voltage; ,
The row select circuitry provides the prepass voltage to the unselected adjacent word lines in response to a prepass enable signal, and applies the pass voltage to the unselected adjacent word lines and the selected word line in response to a pass enable signal; Applying a program voltage to the selection word line in response to a program activation signal;
And the free pass activation signal, the pass activation signal, and the program activation signal are sequentially activated. delete delete Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1,
The non-selected adjacent word line is a first non-selected adjacent word line directly adjacent to the selected word line, and a second non-selected adjacent word line adjacent between the selected word line and the first non-selected adjacent word line. Including;
And the pre-pass voltage includes a first pre-pass voltage applied to the first non-selected adjacent word line and a second pre-pass voltage applied to the second non-selected adjacent word line. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4,
And the first free pass voltage has a lower voltage level than the second free pass voltage. Claim 6 has been abandoned due to the setting registration fee. The method according to claim 1,
The row selection circuit,
And discharging the plurality of word lines to a ground voltage level in response to a program completion signal. Claim 7 has been abandoned due to the setting registration fee. The method of claim 6,
The row selection circuit,
And applying the ground voltage to the word lines except for the selected word line among the plurality of word lines after applying the ground voltage to the selected word line. Claim 8 was abandoned when the registration fee was paid. The method according to claim 1,
And the program voltage is applied by an incremental step pulse program (ISPP) method that sequentially increases by a predetermined step voltage. Claim 9 has been abandoned due to the setting registration fee. The method according to claim 1,
A controller configured to generate the address signal, a prepass activation signal, a pass activation signal, a program activation signal, and a voltage generation control signal; And
And a voltage generator configured to generate the pre-pass voltage, the pass voltage, and the program voltage based on the voltage generation control signal. Applying a pre pass voltage having a voltage level less than the pass voltage to an unselected adjacent word line adjacent to the selected word line in response to the prepass activation signal;
In response to a pass activation signal, applying the pass voltage to a plurality of word lines included in a memory cell array; And
Applying a program voltage to the select word line in response to a program activation signal;
And the pre-pass activation signal, the pass activation signal, and the program activation signal are sequentially activated. delete Claim 12 is abandoned in setting registration fee. The method of claim 10,
And generating the pre-pass voltage, the pass voltage, and the program voltage based on a voltage generation control signal. Claim 13 was abandoned upon payment of a registration fee. The method of claim 10,
Verifying a memory cell connected to the selected word line by applying a verify voltage to the selected word line. Claim 14 has been abandoned due to the setting registration fee. The method of claim 10,
And the pass activation signal is deactivated after the program activation signal is deactivated.

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