JPH10126244A - Integrated circuit with input resistance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a pull-up resistance or pull-down resistance with linear resistance characteristics by providing a pull-up resistance means, which has the gate electrode of a 1st P-type transistor(TR) connected to a 2nd power source or a specific potential developing a gate-source voltage larger than a threshold voltage and the gate electrode of a 2nd P-type TR connected to an input terminal. SOLUTION: The P-type MOS TR P1 has its gate terminal connected to a ground power source Vss or a specific control terminal, which holds the gate-source voltage above the threshold voltage. The P-type MOS TR P2, on the other hand, has its gate terminal connected to the input terminal IN (a). The P-type MOS TR P1 has diode characteristics as shown by a broken line 20, and the P-type MOS TR P2 has diode characteristics shown by a broken line 21. Therefore, when both the P type-MOS TRs P1 and P2 are put together, the input current Iin has nearly linear characteristics like the solid line 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a built-in input resistance provided at an input terminal of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art An input terminal of a semiconductor integrated circuit (LSI) may be actively supplied with an H or L level signal from the outside or may be opened. Depending on the situation in which the LSI is used, an internal pull-up or pull-down input resistor may be provided so that the input terminal is forcibly pulled up to a high power supply or pulled down to the ground power supply when the input terminal is opened. is there.

Usually, the provision of a diffused resistor or the like is performed by using a transistor element to form a resistor because the control of the resistance value is difficult in a process and the area becomes large.

FIG. 3 is a diagram showing an example in which an input resistor is constituted by a transistor element. FIG. 3A shows an example in which a pull-up resistor is formed by the P-type MOS transistor P1, and FIG. 3B shows a characteristic curve thereof. In this example, the gate electrode of the transistor P1 is connected to the ground power supply Vss.
, So that a voltage equal to or higher than the threshold voltage is always applied between the gate and the source. 10 is an input buffer circuit,
The output is supplied to an internal circuit. This transistor P
The value of the on-resistance of 1 is designed such that when a driver having a predetermined drive capability is connected to the outside, the drive capability can overcome and the input Vin can be set to the H level or the L level. .

[0005] As shown in FIG.
When in is lowered from the high power supply Vdd, the resistance value decreases and the input current Iin gradually increases. However, when the voltage between the source and the drain reaches a certain voltage, the transistor P1
Is saturated, and the input current Iin becomes a constant value. Therefore, the resistance exhibits a non-linear characteristic.

FIG. 3C shows an N-type MOS transistor N
This is an example in which a pull-down resistor utilizing No. 1 is configured.
(D) is the characteristic diagram. This circuit operates in a manner opposite to that of the above-described pull-up resistor. When the input Vin rises and reaches a certain potential, the transistor N1 enters a saturation region and the input current Iin is fixed.

[0007]

As described above, the pull-up resistance means and the pull-down resistance means using a transistor are advantageous in that they are simple in manufacturing process and do not require a large area. Therefore, a linear resistance characteristic cannot be obtained as described above.

An object of the present invention is to provide an integrated circuit having a pull-up resistor or a pull-down resistor having a linear resistance characteristic.

[0009]

According to the present invention, a first power supply, a second power supply lower than the first power supply, an input terminal to which an external input signal is supplied, and the input terminal are provided. And an input buffer circuit for supplying the input signal to an internal circuit, the first P-type MOS transistor and the second P-type MOS transistor connected in parallel between the input terminal and the first power supply. A gate electrode of the first P-type transistor, wherein a gate electrode of the first P-type transistor is connected to the second power supply or a predetermined potential at which a voltage between a gate and a source is equal to or higher than a threshold voltage; Is achieved by providing an integrated circuit having a pull-up resistor connected to the input terminal.

Further, according to the present invention, there is provided a first power supply, a second power supply lower than the first power supply, an input terminal to which an external input signal is supplied, and an internal terminal connected to the input terminal. An integrated circuit having an input buffer circuit for supplying the input signal to a circuit, wherein a first N-type MOS transistor and a second N-type MOS transistor are connected in parallel between the input terminal and the second power supply. And the gate electrode of the first N-type transistor is connected to the first power supply or a predetermined potential at which the voltage between the gate and the source is equal to or higher than a threshold voltage, and the gate electrode of the second N-type transistor is An object of the present invention is to provide an integrated circuit having a pull-down resistor connected to the input terminal.

With the above configuration, it is possible to provide input resistance means having a linear characteristic.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

FIG. 1 is a diagram showing a circuit of a pull-up resistor according to an embodiment of the present invention and its characteristics. This pull-up resistor circuit includes two P-type MOS transistors P1, P1 provided in parallel between an input terminal IN and a power supply Vdd.
The transistor P1 has a gate terminal connected to the ground power supply Vss or a predetermined control terminal whose gate-source is maintained at a threshold voltage or more, as in the case of FIG. The transistor P2 is a transistor added this time, and has a gate terminal connected to the input terminal IN.

FIG. 1B is a diagram showing the characteristics of the pull-up resistor. The transistor P1 has the characteristics as indicated by the broken line 20 as described above, and the transistor P2 has the input voltage Vin falling from the power supply Vdd. Then, it has a diode characteristic (broken line 21) in which the current Iin flows from a point where the voltage between the gate and the source becomes equal to or higher than the threshold voltage. Therefore, when the two transistors P1 and P2 are combined, the input current Iin becomes as shown by the solid line 22, and has a substantially linear characteristic.

FIG. 1A shows an example of the input buffer circuit 10. C composed of transistors P3 and N3
It is composed of a MOS inverter and a CMOS inverter similarly composed of transistors P4 and N4. The input buffer circuit is supplied with an input signal supplied to an input terminal and performs waveform shaping.

FIG. 2 is a diagram showing a circuit of a pull-down resistor and its characteristics according to the embodiment of the present invention. This pull-down resistor circuit includes two N-type MOS transistors N provided in parallel between an input terminal IN and a ground power supply Vss.
The transistor N1 has its gate terminal connected to the power supply Vdd or a predetermined control terminal whose gate-source voltage is maintained at a threshold voltage or higher, as in the case of FIG. The transistor N2 is a transistor added this time, and has a gate terminal connected to the input terminal IN.

FIG. 2B is a diagram showing the characteristics of the pull-down resistor. The transistor N1 has the characteristics as indicated by the broken line 24 as described above, and the transistor N2 has the input voltage Vin rising from the ground power supply Vss. Then, the diode has a diode characteristic (broken line 25) in which the current Iin flows from a point where the voltage between the gate and the source becomes equal to or higher than the threshold voltage. Accordingly, when the two transistors N1 and N2 are combined, the input current Iin becomes as shown by the solid line 26, and has a substantially linear characteristic.

By appropriately selecting the size of the transistor of the pull-up resistor circuit and the pull-down resistor circuit, the slope of the linear characteristic can be appropriately selected.

[0019]

As described above, according to the present invention, the input resistance of a semiconductor integrated circuit can be constituted by transistors and can have a linear characteristic. It is possible to provide an input resistance having a linear characteristic.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit of a pull-up resistor according to an embodiment of the present invention and its characteristics.

FIG. 2 is a diagram showing a circuit of a pull-down resistor and characteristics thereof according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a case where an input resistor is configured by a transistor element.

[Explanation of symbols]

 Vdd High power supply Vss Ground power supply 10 Input buffer P1, P2 P-type MOS transistor for pull-up N1, N2 N-type MOS transistor for pull-down

Claims (2)

[Claims] A first power supply and a lower second power supply;
An integrated circuit having an input terminal to which an input signal from the outside is supplied, and an input buffer circuit connected to the input terminal and supplying the input signal to an internal circuit, between the input terminal and the first power supply A first P-type MOS transistor and a second P-type MOS transistor connected in parallel, wherein a gate electrode of the first P-type transistor has a threshold voltage equal to or higher than the second power supply or a gate-source voltage; Wherein the gate electrode of the second P-type transistor has a pull-up resistor connected to the input terminal. 2. A first power supply and a lower second power supply,
An integrated circuit having an input terminal to which an input signal from the outside is supplied, and an input buffer circuit connected to the input terminal and supplying the input signal to an internal circuit, between the input terminal and the second power supply A first N-type MOS transistor and a second N-type MOS transistor connected in parallel, wherein a gate electrode of the first N-type transistor has a threshold voltage equal to or higher than the threshold voltage between the first power supply or the gate and the source. Wherein the gate electrode of the second N-type transistor has a pull-down resistor connected to the input terminal.