JP3457392B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In particular, it relates to a semiconductor integrated circuit in which noise in an output buffer circuit is reduced.

[0002]

2. Description of the Related Art Recently, semiconductor integrated circuits have been widely used in various fields. The transistor that constitutes this semiconductor integrated circuit is extremely small because the circuit is miniaturized. Therefore, when a signal inside the semiconductor integrated circuit is taken out, the signal is often taken out through an output buffer having a large driving capability.

An example of a circuit diagram of a conventional output buffer is shown in FIG.
Is shown in. As shown in FIG. 8, the conventional output buffer has a configuration in which two inverters are connected in series. Of these, the transistor that constitutes the inverter on the output pad 10 side is generally called the final stage transistor. The inverter on the input terminal 12 side is called a prebuffer.

The operation of the output buffer having such a configuration is "H" at the input terminal 12, as is apparent from FIG.
Alternatively, when a signal of “L” is input, the node indicated by A in FIG. 8 changes to “L” or “H” to drive the final stage transistor. Then, finally, the output signal of the final stage transistor appears on the output pad 10 as "H" or "L".

Usually, the charge / discharge charge amount of the final stage transistor is extremely large, and when the state of the final stage transistor transits, a large noise is induced in the power supply line, that is, the Vdd and Vss nodes. Since such noise causes malfunction of the circuit, various measures have been taken to reduce the noise. One method of reducing this noise is to slowly turn on the final stage transistor. For this purpose, a method is adopted in which the change in the potential of the node that drives the gate of the final stage transistor is moderated. A circuit diagram of an output buffer to which such a method is applied is shown in FIG. As shown in FIG. 9, the output buffer shown here is
The pre-buffer is divided into an N-channel side and a P-channel side, and a dedicated pre-buffer is provided for each.
The pre-buffer on the P-channel side is the transistors P1 and N.
1 and the N-channel side pre-buffer is composed of transistors P2 and N2. Then, in the output buffer shown in FIG. 9, in order to moderate turning on of the final stage transistor, the potential of the node indicated by B and C is gradually changed so that the potential of the prebuffer is reduced. The size of the transistor is defined. For example, in the circuit diagram shown in FIG. 9, the transistor N1 is formed smaller than the transistors P1, whereas, preparative transistor P2 is formed smaller relative transistor N2.

As described above, by adjusting the size ratio of the transistors forming the pre-buffer , the transistor N1 is formed smaller for the node B, for example, so that the final stage P-channel transistor is The potential of the gate terminal (that is, the node B) gradually drops to Vss. This is because the driving capability of the transistor N1 is low. Similarly, for node C ,
Since the size of the transistor P2 is small, the potential of the node C rises slowly to Vdd. As a result, it is possible to gently set the final N-channel transistor to be turned on.

As described above, according to the output buffer shown in FIG. 9, the potential change of the nodes (B, C) for turning on the final stage transistor is adjusted by adjusting the size ratio of the transistors forming the pre-buffer. This made it looser. As a result, the last-stage transistor is turned on slowly, and it is possible to reduce the noise induced in the Vdd and Vss nodes. Incidentally, JP-A-6-7
No. 7,807 discloses an output buffer designed to reduce noise.

[0008]

As described above, according to the conventional improved output buffer, the prebuffer is constructed.
By adjusting the size ratio of the transistor
Specifically, the transistors N1 and P2 shown in FIG.
By reducing the size of, the ability to drive the final stage transistor was reduced. This allows node B,
The change in the potential of C (see FIG. 9) can be moderated, and the turning-on of the final-stage transistor can be set gently.

However, due to the layout of the semiconductor integrated circuit, there is a limit to the size reduction of the transistors N1 and P2. Therefore, even if the potential changes of the nodes B and C in FIG.
Since there is a certain limit, there is a problem that noise reduction does not exceed a certain level.

The present invention has been made in view of the above problems, and an object thereof is to make the change in the potential of the gate of the final stage transistor more gradual than ever before, thereby making it possible to significantly reduce noise as compared with the past. To provide a semiconductor integrated circuit having a simple buffer circuit.

[0011]

In order to solve the above-mentioned problems, the first present invention provides a semiconductor integrated circuit having an output buffer including a drive transistor and a pre-buffer for driving the drive transistor. Saw
The gate of the transistor whose
The drain terminal is connected to the power supply and the gate terminal
Transistor for gate voltage control where input signal is supplied to child
The semiconductor integrated circuit is characterized in that, when the pre-buffer drives the drive transistor, the magnitude of the drive current is limited by the control means including the drive circuit.

[0012] The second aspect of the present invention, in order to solve the above problems, a semiconductor integrated circuit of the first aspect of the present invention, the gate voltage to be applied before Symbol pre-buffer is the threshold voltage of the gate voltage suppression transistor It is a semiconductor integrated circuit characterized by being reduced by the amount.

[0013]

Since the limiting means in the first aspect of the present invention limits the output current of the pre-buffer, the so-called driving ability for the drive transistor becomes weak. Therefore, the drive transistor can be turned on slowly.

In the limiting means of the second aspect of the present invention, the gate voltage suppressed by the gate voltage suppressing transistor is applied to the gate terminal of the prebuffer. Therefore, the gate voltage of the pre-buffer can be suppressed with a simple structure, and as a result, the output current of the pre-buffer can be easily limited.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an output buffer of a semiconductor integrated circuit which is a preferred embodiment of the present invention.
As shown in FIG. 1, the N-channel control 100 that drives the final-stage transistor on the N-channel side is
It includes transistors P10 and P11 in addition to the transistors P12 and N12 which are pre-buffers. The transistors P10 and P11 are the gate voltage suppressing transistors of the present invention. These two transistors P
The gate voltage of the transistor P12, which is a transistor forming the pre-buffer, is suppressed by 10 and P11. As described above, in this embodiment, the gate voltage applied to the transistor P12 forming the pre-buffer is suppressed, so that the transistor P12.
The current flowing therethrough decreases, and as a result, the voltage change amount for turning on the final-stage transistor on the N-channel side decreases. In this way, the final-stage transistor on the N-channel side is gently turned on.

The feature of this embodiment is that the transistor P1 which is a transistor forming a pre-buffer is used.
That is, the gate voltage suppressing transistors P10 and P11 are provided as means for reducing the output current of No. 2. Accordingly, for example, when the transistor P12 forming the pre-buffer is turned on, that is, when the “L” level voltage is applied to the gate terminal of the transistor P12, the “L” level voltage is applied to the gate terminal via the transistor P11. The voltage is supplied. At this time, as shown in FIG. 1, the transistor P11 is
Since it is a P-channel side transistor, a voltage higher than Vss by the threshold voltage is generated by the transistor P12.
Is supplied to the gate terminal of.

A feature of this embodiment is that when the transistor P12 is turned on in this way, a voltage higher than the Vss potential by the threshold voltage of the transistor P11 is supplied to the gate terminal thereof, not the Vss potential. It is that you are. As a result, the value of the output current flowing through the transistor P12 is reduced, and as a result, the ON operation of the final stage transistor is moderated. As described above, in this embodiment, the output voltage of the pre-buffer is reduced by suppressing the gate voltage applied to the transistor of the pre-buffer. Therefore, while the output current of the prebuffer has been set small by reducing the size of the transistor forming the prebuffer, it is possible to further reduce the output current. As a result, the ON operation of the final stage transistor can be made even slower, which contributes to noise reduction. In the N-channel control 100 shown in FIG. 1, the transistor P10
Is a transistor for supplying an “H” level potential to the gate terminal of the transistor P12 when the transistor P12 is turned off.

FIG. 1 shows an N channel control 100.
Although the circuit diagram on the side is shown, the circuit of the P channel control 102 for the final stage transistor on the P side is
Appears symmetrically to the channel control 100. Therefore, in FIG. 1, the circuit diagram of the P-channel control 102 is omitted and not shown. The circuit of the P-channel control 102 is the same as the circuit of the N-channel control 100 except that the conductivity types of the N-type and the P-type are opposite to each other.

FIG. 2 shows a graph of voltage-current characteristics between the drain and the source of the transistor. In this graph, the horizontal axis represents the drain-source voltage | Vds |
And the vertical axis represents the drain-source current | Ids |. Note that the absolute values are used for the respective voltages and currents for the sake of easy understanding. As shown in this graph, generally, when the drain-source voltage Vds increases, the drain-source current Ids also increases accordingly, and eventually becomes a constant saturation current, and the current does not increase. This saturation current value is determined by the gate-source voltage Vgs. For example, the graph shown in FIG. 2 shows two graphs when two kinds of gate-source voltages having different voltage values are applied. In this graph, gate-
The source-to-source voltage Vgs2 is the gate-to-source voltage Vg.
It is assumed that its absolute value is larger than s1. Thus, as the gate-source voltage rises, the magnitude of the saturation current value of the drain-source current also increases accordingly. In other words, the drain of the transistor −
It will be understood that the magnitude of the gate-source voltage applied to the transistor can be reduced in order to reduce the magnitude of the current between the sources.

The present embodiment was conceived in view of the characteristics of such a transistor, and by lowering the gate voltage applied to the transistor forming the prebuffer, the output current output from the prebuffer can be reduced. It is intended to be small in size.

FIG. 3 shows a circuit diagram of a conventional output buffer, for example, on the N channel side. As understood from this figure, in order to moderate the rate of change when the gate voltage of the final-stage transistor on the N-channel side changes from “L” to “H”, the P-channel transistor that causes this change is made. It will be understood that it is sufficient to reduce the magnitude of the gate-source voltage Vgs applied to the. The signal applied to the gate terminal of this P-channel type transistor is indicated by D in FIG. 3, for example.

The P-type transistor shown in FIG.
To lower the gate-source voltage during N operation, the voltage applied to the gate terminal D is raised above Vss. An example of such a means is shown in FIG. As shown in FIG. 4, a P-type transistor connected to Vss is provided, and the drain terminal of this transistor is connected to the gate terminal of the P-type transistor shown in FIG. Thus, instead of directly applying the “L” level signal to the gate terminal (“D”) of the P-type transistor (shown in FIG. 3), the P-type signal shown in FIG. Through the transistor, a voltage higher by the threshold voltage VTH of the P-type transistor shown in FIG. 4 can be supplied. As a result, the gate-source voltage applied to the transistor of the pre-buffer can be lowered, and the output current of the pre-buffer can be reduced.

The specific operation of the N-channel control 100 of the circuit shown in FIG. 1 will be described based on the time chart shown in FIG. In the time chart shown in FIG. 5, the horizontal axis represents time and the vertical axis represents potential. First, in the time chart shown in FIG. 5, the potential of the input terminal is represented by a broken line. That is, FIG.
As shown in the time chart of, the transistor P12 is in the ON operation until the time t1, and the transistor P12 is in the OFF operation from the time t1 to the time t2. Then, after the time t2, the transistor P12 is turned off.
It operates N times.

First, until time t1, the level of the signal applied to the input terminal is "L", and the transistor P
12 is ON operation. As a result, the potential of Vdd equal to the power supply potential is applied to the gate terminal of the N-side final stage transistor, and the final stage transistor is in the ON state. In the time chart shown in FIG. 5, the potential of the drain terminal of the transistor P12, that is, the gate terminal of the final-stage transistor on the N side is indicated by a thick line.

Next, when time t1 has passed, an "H" level signal is applied to the input terminal. Thus time t
The transistor P12 is OFF from 1 to time t2
The N-type transistor N12 is turned on instead. That is, the drain terminal of the transistor P12,
That is, the gate terminal of the N-side final stage transistor is almost V
It becomes ss (ground potential).

Next, when time t2 elapses, the level of the signal applied to the input terminal becomes "L" level again. At this time, the transistor P12 is turned on again, but the level of the signal applied to the gate terminal of the transistor P12 at this time is not the level of the signal applied to the input terminal itself, but the threshold voltage of the transistor P11. The voltage becomes higher by VTH. In the time chart shown in FIG. 5, the potential of the signal applied to the gate terminal of the transistor P12 is shown by the alternate long and short dash line. As can be seen from this time chart, the potential applied to the gate terminal of the transistor P12 when it is turned on is not the level of the signal applied to the input terminal itself, but the potential higher by the threshold voltage VTH. As a result, the value of the current flowing through the transistor P12 can be made extremely small as compared with the conventional circuit. Therefore, the potential appearing at the gate terminal of the final-stage transistor gradually rises. The manner of this gradual rise is shown by the thick line in the time chart of FIG. As described above, according to this embodiment, the gate voltage of the final stage transistor is gradually increased,
The final stage transistor gradually turns on.
Therefore, it is possible to further reduce noise as compared with the conventional circuit.

FIG. 6 is a graph showing changes in the gate potential of the final stage transistor of the output buffer according to this embodiment. In this graph, the horizontal axis represents time and the vertical axis represents the potential of this gate terminal. As described above, the output current of the pre-buffer that drives the final-stage transistor can be set to be much smaller than that in the past, and as a result, the change in the gate potential of the final-stage transistor is also much more gradual than in the past. It is possible to As a result, the ON operation of the final stage transistor can be made extremely slow, and noise can be reduced. FIG. 7 shows a graph showing the state of noise caused by the current change of the final stage transistor. In this graph, the horizontal axis represents time and the vertical axis represents the potential of noise induced by Vss. As shown in FIG. 6, since the final stage transistor can be turned on much more slowly than in the conventional case, the noise induced by Vss can be suppressed to a very small level as a result. As shown in FIG. 7, in the related art, a large amplitude noise is induced in Vss by being induced by the ON operation of the final stage transistor, but according to the present embodiment, as shown by the broken line in FIG. It is possible to reduce the magnitude of this induced noise.

[0029]

As described above, according to the first aspect of the present invention, the gate voltage applied to the transistor of the pre-buffer is limited. Therefore, the output current of the transistor of the pre-buffer can be reduced without reducing the size of the transistor. It is possible to Therefore, the ON operation of the final-stage transistor can be made more gradual than in the conventional case, and as a result, the noise can be further reduced.

According to the second aspect of the present invention, a gate voltage suppressing transistor is provided as a means for limiting the gate voltage of the transistor of the prebuffer. Then, by reducing the gate voltage by the threshold voltage of the gate voltage suppressing transistor, it is possible to reduce the output current of the pre-buffer. As a result, the output current of the pre-buffer can be easily reduced without reducing the size of the transistor forming the pre-buffer, and the ON operation of the final stage transistor can be made more gradual. As a result, it is possible to easily obtain a semiconductor integrated circuit whose noise is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer of a semiconductor integrated circuit according to a preferred embodiment of the present invention.

FIG. 2 is a diagram showing voltage-current characteristics of a transistor.

FIG. 3 is a circuit diagram of an N side of a conventional output buffer.

FIG. 4 is a connection circuit diagram of a P-type transistor installed at Vss.

5 is a time chart explaining the operation of the embodiment shown in FIG. 1. FIG.

FIG. 6 is a time chart showing changes in the potential of the gate terminal of the final stage transistor.

FIG. 7 is a graph showing how noise appears in Vss.

FIG. 8 is a circuit diagram showing an example of an output buffer used in a conventional semiconductor integrated circuit.

FIG. 9 is a circuit diagram of a conventional improved output buffer.

[Explanation of symbols]

100 N channel control 102 P channel control 10 output pads 12 input terminals

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Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit having an output buffer including a drive transistor and a prebuffer for driving the drive transistor, wherein the source terminal constitutes the prebuffer.
The gate terminal and drain terminal of the
Gate voltage control transistor whose input signal is supplied to the
A semiconductor integrated circuit characterized in that, when the pre-buffer drives the drive transistor, the magnitude of the drive current is limited by the control means including the transistor. The semiconductor integrated circuit as claimed in claim 1, according to claim 1, the gate voltage to be applied before Symbol pre-buffer is a semiconductor integrated circuit, characterized in that to reduce the threshold voltage of the gate voltage suppression transistor.