JPH05290572A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the source voltage dependency of the threshold value of an external input first stage circuit and to enlarge a margin to a TTL interface on a system sharing source voltages 5V+ or -10% and 3.3V+ or -0.3V. CONSTITUTION:MOSFETs Q3, Q4 regarding an external input signal and a constant voltage signal as gates respectively are connected between an output nodal point and a grounded line in series to the external input first stage circuit consisting of the MOSFETs Q1 and Q2. The MOSFETs Q5, Q6, Q7 are diode- connected in series to a constant voltage signal nodal point between with a power source line and a resistance element is connected between the grounded line and the nodal point. Since the Q4 is turned on when source voltage is high, a first stage threshold value becomes low and when source voltage becomes low and Q4 is turned off, the threshold value becomes high. Further, the constant voltage is signal nodal point is set by resistance-division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an external signal input circuit that guarantees a TTL interface.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit guarantees a TTL interface by changing the capacity ratio between a P-type MOS field effect transistor (hereinafter referred to as FET) of an inverter and an N-type MOSFET transistor as an external signal input circuit. Was.

FIG. 6 shows a conventional semiconductor integrated circuit.
Q1 is a P-type MOSFET, Q2 is an N-type MOSFET, I
N is an external input node, and NO is an output node of the external signal input first stage circuit composed of the transistors Q1 and Q2.

For example, a dynamic random access memory (hereinafter referred to as DRAM) which is a general-purpose product
Are standardized such that the power supply voltage Vcc is 5V ± 10%, the high level input voltage V1H is a minimum of 2.4V, and the low level input voltage V1L is a maximum of 0.8V.

In the external signal input first stage circuit, the threshold value is changed by changing the comparison of the current capabilities of the transistors Q1 and Q2 in order to satisfy the above standard.

The principle will be described below. First, if the transistors Q1 and Q2 have the same capability, the power supply voltage is 5V.
When the input node IN is 2.5V, the transistors Q1 and Q
The ON resistances of 2 become equal, and the output node NO becomes 2.5V. That is, the input threshold value at this time is 2.5V.

Next, a transistor Q connected to the ground line side
When the capacity of 2 is larger than that of Q1, when the power supply voltage is 5V and the input node IN is 2.5V, the transistor Q2
Since the on resistance of is smaller than that of Q1, the output node NO becomes lower than 2.5V.

As is clear from the input / output characteristics of the CMOS inverter, the output level near the threshold value greatly changes compared with the change of the input level. That is, the output node N
The displacement of O from 2.5 V is larger than the displacement at the input node, and the output of the next stage is almost completely at the CMOS level, that is, the power supply line level or the ground line level.

Therefore, in this case, if the level of the input node IN is lowered below 2.5V, the output node NO becomes 2.5V.
Becomes That is, the input threshold is lower than 2.5V. As described above, the input threshold of the first stage is lowered by increasing the ability of the transistor that connects the output node of the first stage and the ground line.

The threshold voltage of the transistor is likely to vary in the semiconductor manufacturing process, and when the power supply line level and the ground line level are changed due to the noise due to the internal operation, the threshold value of the first stage and the apparent threshold value are respectively changed. It fluctuates greatly.

Therefore, in designing the power supply voltage 5
In order to stably set the threshold between 0.8V and 2.4V at V ± 10%, the transistor capacity ratio is determined so that the threshold becomes approximately 1.6V when the power supply voltage is 5V. ,
Make the operating margin equal for high and low levels.

Although an inverter is used as an example of the first-stage circuit in FIG. 6, a NAND or NOR is used to suppress the first-stage flow-through current during standby, and the other input is used as a power source for the first-stage output node during standby. In many cases, the internal control signal is fixed to the level or the ground level. However, I will only mention it here.

As a recent technical trend of electronic equipment, lowering of the voltage of the power supply is mentioned in order to reduce the power consumption of the system. That is, the standard of 3.3V ± 0.3V single power supply is determined as the next generation from the single power supply of power supply voltage 5V ± 10%, and some devices are starting to shift.

Further, as a new system, a method of switching between a mode in which high speed operation is performed at a power supply voltage of 5 V and a mode in which low speed but low power consumption is performed at 3.3 V is being developed on the same electronic device.

In this case, in order to guarantee the TTL interface, the first stage threshold value is set within the range of 0.8V to 2.4V in the range of power supply voltage 3.0V to 5.5V. FIG. 7 shows a design example of the power supply voltage dependency of the initial stage threshold value of the external signal input initial stage circuit of the semiconductor integrated circuit used in the system sharing 3.3V and 5V. As described above, the threshold value increases monotonically in a manner substantially proportional to the power supply voltage.

[0016]

This conventional semiconductor integrated circuit is a P-type MOSFET forming an external input first stage circuit.
Since the input threshold value is set by the ratio of the two transistors, N-type MOSFET and N-type MOSFET, the power supply voltage is set to 3.
When used in a system sharing 3V and 5V, TTL interface in a wide power supply voltage range from 3.0V to 5.5V, that is, high level input voltage 2.4V, low level input voltage 0.8V In order to guarantee the above, there was a drawback that the margin of the manufacturing range was too small.

That is, it is vulnerable to the fluctuation of the apparent threshold value due to the fluctuation of the power supply line level or the ground line level due to the noise due to the internal operation, and as a countermeasure against this, the fluctuation of the manufacturing conditions such as the threshold voltage of the transistor is reduced. However, there is a drawback that the manufacturing cost becomes high.

An object of the present invention is to provide a semiconductor integrated circuit in which the power supply voltage dependency of the threshold value of the external input first stage circuit is reduced.

[0019]

In order to achieve the above-mentioned object, a semiconductor integrated circuit according to the present invention has a first MOS which uses an external input signal as a gate and is connected between an output node and a first power supply line. An external input first-stage circuit including a field-effect transistor and a second MOS field-effect transistor that has an external input signal as a gate and is connected between the output node and a second power supply line, and gates the external input signal And the third M
An OS field effect transistor and a fourth MOS field effect transistor having a constant voltage signal line as a gate are connected in series between the output node of the input first stage circuit and the second power supply line.

The constant voltage signal line of the semiconductor integrated circuit has a plurality of MOS field effect transistors connected in series with the first power supply line in a diode connection, and has a resistance element between the second power supply line and the constant voltage signal line. Alternatively, a resistor formed by a MOS field effect transistor is connected.

The constant voltage signal line of the semiconductor integrated circuit is connected to the first power supply line by a resistance element or a resistance by a MOS field effect transistor, and is connected to the second power supply line by a resistance element or a MOS field effect. It is a resistor connected by a transistor.

[0022]

With the external input signal and the constant voltage signal as gates, two MOSFETs connected in series between the output node of the input first stage circuit and the ground line, and the constant voltage signal node between the power line and Of a plurality of MOSFETs connected in series with a diode, or a resistance element or a resistance of the MOSFET, and a resistance element or MO between the ground line and
The resistance by SFET is provided. As a result, the dependency of the first-stage threshold value on the power supply voltage is reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention. In the following description, the same parts as those of the conventional semiconductor integrated circuit of FIG.

In FIG. 1, in this embodiment, a P-type MOS is used.
N-type MOSF whose gate is the input first stage signal of the external input signal node IN with respect to the FET Q1 and the N-type MOSFET Q2
ETQ3 and N-type MO with constant voltage signal line N1 as a gate
It is connected in series between the SFET Q4, the output node N0 and the ground line.

The constant voltage signal line N1 is formed by connecting three N-type MOSFETs Q5, Q6 and Q7 in series with a power supply line in a diode connection, and connecting a resistance element R1 having a high resistance value with a ground line. Generate a constant voltage.

FIG. 2 shows the power supply voltage dependency of the first stage threshold value of the external input first stage circuit shown in FIG. In addition, FIG.
This is the power supply voltage dependency of the potential of the constant voltage signal line N1 shown in FIG.

N-type MOSFETs Q4, Q5, Q6, Q7
The threshold voltage of Vth is VTh. Strictly speaking, M
The threshold voltage of the OSFET has a back bias voltage dependency and a source-drain voltage dependency, but since it does not directly relate to the principle of this patent, it is represented by the same symbol VTh. In addition, VTh = 0.8V.

First, when the power supply voltage Vcc is sufficiently high, the MO
If the resistance value of the resistance element R1 is sufficiently larger than the on resistances of the SFETs Q5, Q6 and Q7, the level of the node N1 is V
It becomes cc-3VTh. For example, when Vcc = 5.5V,
The level of the node N1 becomes 3.1V.

At this time, the MOSFET Q4 whose gate is the constant voltage signal line N1 is on. Therefore, the output node NO is not only the MOSFET Q2 but also the MOSFET.
It is also electrically connected to the ground wire through a series circuit of TQ3 and Q4.

That is, the threshold value of the first stage is lower than that of the MOSFET Q2 alone because it corresponds to an increase in the transistor capacity for connecting the output node NO and the ground line.

Next, when the power supply voltage is gradually lowered, the level of the constant voltage signal line N1 is lowered according to Vcc-3VTh, so that the capacity of the MOSFET Q4 is sharply lowered. That is, since the transistor ability to connect the output node NO and the ground line is lowered, the threshold value of the first stage is not lower than the lowering of the power supply voltage but is a constant voltage.
When the power supply voltage is further lowered, the threshold value rises.

When Vcc = 4VTh, that is, when the potential Vcc-3VTh of the output node NO becomes VTh, finally the MOSFET Q
4 turns off (Vcc = VOFF). At this time, the output node N
Since the O and the ground line are electrically connected only by the MOSFET Q2, the threshold value becomes high, and therefore the power supply voltage dependency shows a maximum. When the power supply voltage is further lowered, the threshold value is lowered in the same manner as the power supply voltage is lowered.

As described above, the power supply voltage dependency of the first stage threshold value has a maximum and a minimum, so that the power supply voltage is 3.0 V.
In the wide range from 1 to 5.5V, the margin becomes large for the TTL interface.

In the above example, the process in which VTh is 0.8 V is described, but the power supply voltage VOFF at which the constant voltage signal line N1 cuts VTh is approximately 3.5 even in the process in which VTh is different.
It can be designed by adjusting the number of series MOSFETs of the constant voltage generation circuit so that the voltage becomes about 4.0V from V.

Further, the resistance element R1 can be replaced with an N-type MOSFET having a gate as a power supply level.

(Second Embodiment) FIG. 4 is a circuit diagram showing a second embodiment of the present invention. The same parts as those of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1 will be described with the same reference numerals.

In this embodiment, the constant voltage signal line N1 is connected to the power source line by a resistance element R2, and is connected to the ground line by a resistance element R1.
A constant voltage is generated by connecting.

FIG. 5 shows the power supply voltage dependence of the potential of the constant voltage signal line N1 shown in FIG.

The resistance values of the resistance elements R1 and R2 are respectively R
When R1 and R2 are set, R1 and R2 are set so as to follow the relational expression of R1 / (R1 + R2) = VTh / VOFF. At this time, if the power supply voltage is higher than VOFF, the constant voltage signal line N1
, That is, the gate potential of the N-type MOSFET Q4 is VTh
As described above, since the MOSFET Q4 is turned on, the first stage threshold value is low. If the power supply voltage becomes lower than VOFF, MO
Since the gate potential of SFET Q4 becomes VTh or less and is turned off, the threshold voltage of the first stage becomes high.

FIGS. 8 and 9 show the dependence of the threshold voltage of the first stage on the power supply voltage according to the embodiment of the present invention, obtained by a SPICE circuit simulation. The characteristics of the embodiment of the present invention are shown by the solid line in FIG. 8, and the circuit constants are shown in FIG. MOSFETs have gate widths WP and WN (unit: μ
m), the current capability of the P-type and N-type MOSFETs is β P = 1 in terms of WP = W N = 10 μm.
It is assumed that 50 μS / V and β N = 300 μS / V.
The characteristic of the conventional example is shown by the broken line in FIG. 8, and the circuit constants are WP = 10 .mu.m and WN = 30 .mu.m.

As is apparent from the figure, the width of the minimum and maximum values of the first-stage threshold value in the power supply voltage range of 3.0 V to 5.5 V is significantly reduced by the present invention.

[0043]

As described above, the present invention has two MOSFETs each having an external input signal and a constant voltage signal as a gate and connected in series between the output node of the input first stage circuit and the ground line. The constant voltage signal node has a plurality of MOSFEs diode-connected in series with the power supply line.
T, or resistance by a resistance element or MOSFET,
Since the resistance element or the resistance by MOSFET is provided between the power supply line and the ground line, the power supply voltage dependency of the first-stage threshold is reduced, so that the apparent threshold value due to the fluctuation of the power supply line level or the ground line level is reduced. Of the transistor, variation in manufacturing conditions such as the threshold voltage of the transistor can be tolerated, and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an external input first stage circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a power supply voltage dependency of a first stage threshold value of the external input first stage circuit shown in FIG.

3 is a diagram showing the power supply voltage dependency of the N1 node potential of the external input first-stage circuit shown in FIG.

FIG. 4 is a circuit diagram showing an external input first stage circuit according to a second embodiment of the present invention.

5 is a diagram showing the power supply voltage dependency of the N1 node potential of the external input first stage circuit shown in FIG.

FIG. 6 is a circuit diagram showing a conventional external input first-stage circuit.

7 is a diagram showing power supply voltage dependence of a first stage threshold value of the external input first stage circuit shown in FIG.

FIG. 8 is a diagram showing the power supply voltage dependency of the initial stage threshold value of the external input initial stage circuit by SPICE circuit simulation.

FIG. 9 is a diagram showing circuit constants.

[Explanation of symbols]

Q1, Q8, Q9, Q10, Q11, Q12 P-type MOSFE
T Q2, Q3, Q4, Q5, Q6, Q7 N-type MOSFE
TR1, R2 resistance IN External input signal node NO output node N1 Constant voltage signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301

Claims (3)

[Claims] 1. A first MOS field effect transistor having an external input signal as a gate and connected between an output node and a first power supply line, and an external input signal as a gate, the output node and a second power supply. A third MOS field effect transistor having a second MOS field effect transistor connected between the lines and having a second MOS field effect transistor, and a fourth MOS field effect transistor having an external input signal as a gate and a constant voltage signal line as a gate; And the MOS field effect transistor of 1) are connected in series between the output node of the input first-stage circuit and the second power supply line. 2. The constant voltage signal line of the semiconductor integrated circuit comprises:
A plurality of MOS field effect transistors are diode-connected in series with the first power supply line, and a resistance element or a resistance by a MOS field effect transistor is connected with the second power supply line. The semiconductor integrated circuit according to claim 1. 3. The constant voltage signal line of the semiconductor integrated circuit comprises:
7. A resistance element or a resistance by a MOS field effect transistor is connected to the first power supply line, and a resistance element or a resistance by a MOS field effect transistor is connected to the second power supply line. 1. The semiconductor integrated circuit according to 1.