JPH0834427B2 - Logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit in a semiconductor integrated circuit, and more particularly to a method for forming a buffer in a gate array.

[Conventional technology]

2. Description of the Related Art In recent years, as the scale of integration of integrated circuits has expanded, LSI elements, wiring, etc. have been miniaturized. In the gate array as well, the shortening of the wiring due to electromigration has become a problem with the progress of miniaturization of elements and wiring, and the wiring width of not only the power supply wiring but also the signal wiring has been reduced. , Its wiring life is becoming a problem.

Generally, this electromigration differs depending on the material of the wiring, but the smaller the width (cross-sectional area) of the wiring,
Further, the higher the current density flowing in the wiring, the more remarkable it occurs, and the life of the wiring becomes shorter.

In the gate array, because of the restrictions on CAD, automatic wiring processing is performed with a uniform wiring width, so the current value that can be passed to the signal wiring is all uniform.
In addition, various circuits have been realized in the gate array, and buffer circuits are used inside the gate array, and especially in the CMOS gate array, buffers with different load drive capacity are used according to the load of the buffer. Often used. However, since more load is connected to the buffer with a large load drive capacity,
A larger amount of current flows through the output signal wiring, and a buffer having a load driving capability above a certain level cannot be realized from the viewpoint of wiring life.

Therefore, conventionally, when the load increases, the load is divided by using a plurality of buffers to divide the current flowing through the signal wiring, as shown in FIG. In FIG. 5, the signals from the same input terminal 4 are input to the buffers 1a and 1b,
The NOR gate 20 and the NAND gate 21 are connected as the load of the buffer 1a, and the flip-flop 22 is connected as the load of the buffer 1b.
Is connected.

[Problems to be solved by the invention]

Since the conventional logic circuit described above is a circuit that uses a plurality of buffers and divides the load into each,
Even if each buffer has the same load drive capability, the connected loads are not exactly the same, so the propagation delay time of each buffer (hereafter abbreviated as tpd) is different, which is a drawback in circuit design.

[Means for solving problems]

In the logic circuit of the present invention, the sources of the plurality of MOS transistors of the first conductivity type are connected to the first power supply, and the sources of the plurality of MOS transistors of the second conductivity type are connected to the second power supply,
The output circuit in which the drains of the plurality of first and second conductivity type MOS transistors are commonly connected and an output signal is taken out from the commonly connected drains has a plurality of output terminals.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Also the second
The figure is an equivalent circuit diagram when the circuit of FIG. 1 is applied to a CMOS gate array. In FIG. 1 and FIG. 2, the inverter 2 is connected to the input terminal 4, the input ends of the buffers 3, 3a, 3b, 3c are connected to the output of the inverter 2, and the output terminals 5, 5a, 5b of the respective buffers are connected. , 5c are commonly connected. The inverter 2 and the buffers 3, 3a, 3b, 3c are configured by connecting a P-channel type transistor 6 and an N-channel type transistor 7 in series between a power source 8 and a GND 9.

Further, FIG. 3 shows an example of the layout of FIG. In the figure, the Al wiring 11a has a larger wiring width than the other Al wirings 11 so that a wiring life equivalent to that of the other wirings 11 can be obtained even when a larger amount of current flows. And this thick Al wiring 11
Output terminals 5, 5a, 5b and 5c are appropriately provided on a, and the terminals of output terminals 5 to 5c and the loads connected to them are wired by an automatic wiring program or the like.

Wiring from the terminals of output terminals 5 to 5c is automatically wired if the load connected to each terminal is limited so that the current flowing in the signal line is suppressed to some extent and the wiring life is not deteriorated. The wiring having the same wiring width as that of the other wirings will suffice. Therefore, as shown in FIG. 3, if the wiring in which a larger amount of current flows in the buffer block is made thick beforehand, the wiring life will not be reduced.

The output terminals 5 to 5c are connected inside the buffer block, so even if the load on each terminal is different, tpd
Will be exactly the same.

The example of FIG. 1 is an example in which four buffers are connected in parallel, but the number of buffers connected in parallel may be any number and the output terminals corresponding to the number are provided and the wiring in the block is It should be thick enough.

FIG. 4 shows an example of the inverting buffer. FIG. 4 shows an example in which five buffers 3 to 3d are connected in parallel and three output terminals 5, 5a and 5b are provided. In this way, the number of buffers connected in parallel and the number of output terminals do not have to match, and the layout within the buffer block is performed so that the wiring life can be satisfied, and the number of loads connected to each output terminal. You should limit the.

〔The invention's effect〕

As described above, according to the present invention, when designing a functional block in a gate array, a plurality of buffers (inverters) are connected in parallel, the interconnection wiring is sufficiently thick, and a plurality of output terminals are provided. Therefore, it is not necessary to thicken the signal wiring used in the gate array, and thinner signal wiring can be used. Therefore, there is an effect that the chip size can be reduced accordingly and the cost can be reduced.

Further, since the respective output terminals are connected to each other in the buffer block, the tpd is exactly the same even if the load connected to each is changed, and there is no problem in circuit design. Furthermore, even when automatic wiring is performed using a computer, the thickness of the signal wiring can be set to a uniform wiring width, which has the effect of simplifying the processing.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a buffer block according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is a block layout diagram of FIG. 2, and FIG. FIG. 5 is a circuit diagram of the embodiment, and FIG. 5 is a circuit diagram using a conventional buffer. 1a, 1b …… buffer, 2 …… inverter, 3,3a, 3b, 3c, 3d
... buffer, 4 ... input terminal, 5,5a, 5b, 5c ... output terminal, 6 ... P-channel type transistor, 7 ... N-channel type transistor, 8 ... power source, 8a ... power source Al wiring, 9 ... GND, 9a ... GND Al wiring, 10 ... contact hole, 11,11a ... Al wiring, 20 ... NOR gate, 21 ... NAN
D-gate, 22 ... Flip-flop.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03F 3/68 B H03K 19/173 9199-5K H01L 21/82 MP

Claims (1)

[Claims] 1. A source region of a plurality of MOS transistors of a first conductivity type is connected to a first power source, and a plurality of MO transistors of a second conductivity type are connected.
The source region of the S transistor is connected to a second power source, the drain regions of the plurality of first and second conductivity type MOS transistors are commonly connected by a common wiring to form a buffer circuit, and a plurality of outputs from the common wiring are provided. A logic circuit characterized in that terminals are taken out and connected to corresponding ones of a plurality of loads through wirings, respectively, and the wirings respectively led out from the plurality of output terminals are formed with equal widths.