JP2978501B2 - Logic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a logic circuit, and more particularly to a layout of a logic circuit configured by combining a MOS transistor and a bipolar transistor.

(Prior Art) Generally, in the layout design of an LSI logic circuit,
Since a large number of man-hours are required, conventional layouts of a plurality of types of basic logic gates having a fixed height are conventionally designed in advance, and these many basic logic gates are arranged and routed using an automatic layout tool. Many layout methods such as cells are used.

On the other hand, recently, in order to improve the speed performance of LSI, M
Bi combining OS transistor and bipolar transistor
CMOS basic logic gates are attracting attention. Such BiCMOS
The gate is a pair of N-channel and P-channel MOS.
The combination of low power consumption of CMOS gates composed of transistors and high speed of bipolar transistors makes this a promising logic gate for future LSIs.

For example, Japanese Patent Application Laid-Open No. 61-171150 discloses a configuration in which a bipolar portion is added to the upper or lower portion of a CMOS portion in a standard cell constructed with such a conventional BiCMOS gate.

(Problems to be Solved by the Invention) The above-described conventional BiCMOS gate can drive at a higher speed than a CMOS gate when driving a large load capacitance such as a large number of logic gates or long wirings. The driving speed is lower than that of the CMOS gate. In general, most of the logic gates inside the LSI are connected to only a few logic gates by a short wiring of 1 mm or less. Therefore, if all the logic gates are constituted by BiCMOS gates, there is a problem that sufficient speed performance cannot be obtained. In order to solve this problem and increase the speed, conventionally, only logic circuits with a large number of fanouts and long wiring lengths are configured with BiCMOS gates, and most of the remaining logic circuits are configured with CMOS gates. Is advantageous.

However, conventional BiCMOS gate standard cells have a configuration in which a bipolar part is added to the top of the CMOS part. In addition, there is a drawback that an unused area increases and a chip size increases, and further, according to the conventional BiCMOS gate layout method, there is a drawback that a price increase due to an increase in the chip size occurs.

An object of the present invention is to provide a logic circuit capable of reducing an unused area when arranging such a CMOS gate and a BiCMOS gate in a mixed manner, reducing the chip size of an LSI, and laying out at low cost. is there.

(Means for Solving the Problems) According to the present invention, in a logic circuit composed of a MOS transistor and a bipolar transistor, a first and a second pair of power supply wiring lines are arranged in parallel with each other, and And a MOS transistor of a first polarity is arranged on the side of the first power supply wiring line, and a MOS transistor of a second polarity is arranged on the side of the second power supply wiring line. In a region between the power supply wiring lines and in the length direction of the pair of power supply wiring lines.

Further, according to the present invention, in a logic circuit including a MOS transistor and a bipolar transistor, a first and a second pair of power supply wiring lines are arranged in parallel, and in a region between the pair of power supply wiring lines and A first polarity MOS transistor is arranged on the first power supply line side, and a second polarity MO transistor is disposed on the second power supply line side.
An S transistor is arranged, and a plurality of the bipolar transistors having different rectangular contact lengths are arranged in a region between the pair of power supply lines such that the length direction of the rectangular contact is parallel to the pair of power supply lines. It is characterized by doing.

(Operation) In the logic circuit of the present invention, by setting the standard cells of the CMOS gate and the BiCMOS gate to the same height, when the standard cells are arranged and wired by the automatic layout, the unevenness between the CMOS gate and the BiCMOS gate is obtained. And unused areas are reduced.

Also, if the driving direction of the bipolar section is increased by arranging the length direction of the bipolar section parallel to the power supply line, the contact may be extended parallel to the power supply line. The result is a BiCMOS gate with high driving capability.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a basic layout diagram of a logic circuit for explaining an embodiment of the present invention.

As shown in FIG. 1, the BiCMOS gate in this embodiment is provided with a first power supply wiring 1 and a second power supply wiring 2 which are drawn in parallel with each other. A CMOS section 3 and a bipolar section 4 are provided between the power supply wiring 2 and the CMOS section 3.
Normally, 5V (volt) is applied to the first power supply wiring 1, and the second power supply wiring 2 is used as a ground.

Since the BiCMOS gate arranged in this manner has the same height as the CMOS gate, even if the BiCMOS gate and the CMOS gate are mixedly arranged, the first power supply wiring 1 and the second power supply wiring 2
And can be drawn in parallel. Therefore, when a plurality of logic gates are connected, the unused area is reduced, and the chip size can be reduced.

FIG. 2 is a configuration diagram of a logic circuit represented by the layout shown in FIG. 1, and FIG. 3 is a specific layout diagram of the logic circuit in FIG. 1 and FIG.

Hereinafter, this embodiment will be described in detail with reference to FIG. 2 and FIG.

As shown in FIG. 2, the logic circuit of this embodiment includes a CMOS inverter including a P-channel type first MOS transistor 5 and an N-channel type second MOS transistor 6, and an N-channel type third MOS transistor. MOS transistor 7 and NPN
And a BiCMOS inverter circuit comprising a bipolar transistor 8 of the same type connected between an input terminal 9 and an output terminal 10.

In this logic circuit, when a high potential is applied to the input terminal 9, the second and third MOS transistors 6, 7 conduct, and the output terminal 10 goes to a low potential. On the other hand, when a low potential is applied to the input terminal 9, the bipolar transistor 8 conducts together with the first MOS transistor 5, and the output terminal 10 becomes high potential. That is, the output terminal 10 is connected to the power supply terminal V via the bipolar transistor 8 having a low conduction resistance. Therefore, the use of such a logic circuit enables high-speed driving even for a large-capacity load.

As shown in FIG. 3, the transistors constituting the above-described logic circuit are arranged between the first power supply wiring 11 and the second power supply wiring 12. First, the P-type diffusion layer 13 and the gate electrode
14 forms the first MOS transistor 5 described above with reference to FIG. 2, and the N-type diffusion layer 15 and the gate electrode 14
An S transistor 6 and a third MOS transistor 7 are formed. Next, the first to fifth contacts 16A to 16E are respectively connected to the P-type diffusion layer 13 and the first power supply wiring 11, the N-type diffusion layer 15 and the second power supply wiring 12, and the P-type diffusion layer 13 and the first power supply wiring 12, respectively. Layer metal wiring 1
7, N-type diffusion layer 15 and first-layer metal wiring 17, N-type diffusion layer 15
And the first-layer metal wiring 17. Further, the third and fourth contacts 16C and 16D and the base contact 18 of the bipolar transistor are connected by a first layer metal wiring 17, and the collector contact 19 of the bipolar transistor is connected to the first power supply wiring 11. In addition, the emitter contact 20 of the bipolar transistor is the first layer metal wiring
It is connected to the N-type diffusion layer 15 and the second-layer metal wiring 22 via a fifth contact 16E and a through-hole contact 21. Therefore, the above-described gate electrode 14 is
The input terminal 9 shown in the figure is used, and the second-layer metal wiring 22 is used as the output terminal 10.

Thus, the first power supply wiring 11 and the second power supply wiring 12
A transistor is formed between the contacts 16A to 16E and
By connecting via the lines 18 to 21, the logic circuit shown in FIG. 2 can be realized.

As described above, the bipolar transistor represented by the base contact 18, the collector contact 19, and the emitter contact 20 is disposed beside the P-type diffusion layer 13. This allows the height of the BiCMOS gate to be the same as the height of the CMOS gate, reducing unused area,
Enables chip size reduction.

On the other hand, the conduction resistance of such a bipolar transistor can be reduced by extending the length of the rectangular contacts (base contact 18, collector contact 19, emitter contact 20). That is, if this conduction resistance can be reduced, the bipolar transistor Driving ability can be increased. In this embodiment, as shown in FIG. 3, by arranging the rectangular contacts 18 to 20 so as to be parallel to the first power supply wiring 11 in the longitudinal direction, Bi
It is possible to increase the length of the rectangular contacts 18-20 without changing the height of the CMOS gate. In short, BiCMOS gates having various driving capabilities can be realized at the same height as the CMOS gate.

(Effects of the Invention) As described above, the logic circuit of the present invention can realize a BiCMOS gate having the same height as a CMOS gate, and can set the length direction of the contact of the bipolar transistor in parallel with the power supply line. By arranging, it is possible to realize BiCMOS gates with various driving capabilities at the same height as CMOS, so if CMOS gates and BiCMOS gates are mixedly arranged, the unused area is reduced and the LSI chip There is an effect that the size can be reduced, that is, the price can be reduced.

[Brief description of the drawings]

FIG. 1 is a basic layout diagram of a logic circuit for explaining one embodiment of the present invention, FIG. 2 is a configuration diagram of a logic circuit formed by the layout shown in FIG. 1, and FIG. FIG. 3 is a specific layout diagram of the logic circuit in FIG. 2 and FIG. 2; 1,11 ... first power supply wiring, 2,12 ... second power supply wiring, 3 ... CMOS part, 4 ... bipolar part, 5-7 ... MOS transistor, 8 ... bipolar transistor, 9 ... ... Input terminal, 10 ... Output terminal, 13 ... P-type diffusion layer, 14 ... Gate electrode, 15 ... N-type diffusion layer, 16A ~ 16E ... Contact, 17 ... First-layer metal wiring, 18 ... ... Base contact, 19 ... Collector contact, 20 ... Emitter contact, 21 ... Through hole contact, 22 ... Second layer metal wiring.

Claims (1)

(57) [Claims] In a BiCMOS gate circuit of a logic circuit in which a CMOS gate and a BiCMOS gate are mixed and a power supply wiring interval between a pair of first and second power supply wiring lines arranged in parallel is determined by the CMOS gate circuit. A MOS transistor having a first polarity is disposed in a region between the pair of power supply wiring lines and on the side of the first power supply wiring line;
A plurality of bipolar transistors having different rectangular contact lengths are arranged on the side of the power supply wiring line, and the length direction of the rectangular contact is made parallel to the pair of power supply wiring lines, and A logic circuit, wherein the logic circuit is arranged in a region between power supply wirings.