JPH0787240B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit designed to prevent a latch-up phenomenon in a CMOS transistor.

[Conventional technology]

Generally, in a gate array structure semiconductor integrated circuit, basic elements forming a logic element are used as basic cells, the cells are fixedly arranged in a matrix, and only wirings are variably configured to realize an arbitrary logic function. As a result, the manufacturing process before wiring can be standardized to enable high-mix low-volume production.

FIG. 5 shows a chip layout diagram of a gate array type CMOS semiconductor integrated circuit. In the figure, 51 is a cell row of basic cells, 52 is a wiring region provided outside or between these cell rows, 53 is an input / output buffer circuit, and 54 is a signal extraction pad. By performing the automatic placement and routing program processing in the wiring region 52 and the basic cell row 51, wiring of a desired logic function can be performed.

Further, as shown in detail in FIG. 6, the input / output buffer circuit 53 includes an input protection circuit 61, a high drive CMOS transistor region 62 and an input / output buffer CMOS transistor region 63. The high drive CMOS transistor region 62 is
The final stage of the output buffer comprises a high-driving N-channel MOS transistor region 64 and a P-channel MOS transistor region 65. Further, the input / output buffer CMOS transistor region 63 is the high drive CMOS when the output buffer circuit is configured.
It is composed of an N-channel MOS transistor region 66 and a P-channel MOS transistor region 67 of MOS transistors which drive the transistor region 62 or constitute an input buffer circuit. 68 is the gate of these transistors.

In this structure, for the purpose of reducing the chip area and cost, between the regions 62 and 63, in other words, the high drive P-channel MOS transistor region 65 and the N-channel MOS transistor of the input / output buffer region 63. No wiring region is provided between the region 66 and both regions, and both regions are close to each other.

[Problems to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the P channel MOS transistor region 65 and the N channel MOS transistor region 66 are provided.
Since and are close to each other, a parasitic transistor is generated between both transistors as shown in FIG. 7, and latch-up is likely to occur.

That is, in FIG. 7, a P-channel MOS transistor (6
The lateral PNP transistors Tr ₁ and Tr ₃ having the P-type source region 71 and the P-type drain region 72 of 5) as an emitter, the N substrate 77 as a base, and the P-well 78 as a collector are formed. Also, N
A vertical NPN transistor Tr _{2 in which} the N-type source region 73 or the N-type drain region 74 of the channel MOS transistor (66) is the emitter, the P-well 78 is the base, and the N-substrate 77 is the collector.
And Tr ₄ are configured. The base resistors that bias the bases of these transistors are R ₁ and R ₃ , but the V _DD electrode
75 and the base 77, and the resistance between the V _SS electrode 76 and the base 78 is a distributed constant resistance formed in the vicinity of each diffusion layer. The emitter resistances R ₂ and R ₄ of the transistors Tr ₁ and Tr ₂ are resistances formed between the source electrodes 71 and 73 of the P and N channel transistors and the V _DD or V _SS electrodes, respectively.

Therefore, for example, when a sufficiently large positive external noise voltage is applied to the output terminal V _OUT , the transistor Tr ₃ (which becomes the transistor Tr ₄ when the signal is negative) connected to the output terminal is normally connected between the base and emitter. It is biased to turn on Tr ₃ and a noise current flows into V _SS through the base resistance R ₃ of transistor Tr ₂ . As a result, the transistor Tr ₂ is turned on, current flows from V _DD through the base resistor R ₁ of the transistor Tr _1, turns on the transistor Tr _1. Furthermore, the collector current of the transistor Tr ₁ rebiases the base of the transistor Tr ₂ . After all, as shown in FIG. 8, a positive feedback is applied to the closed loop circuit composed of the transistors Tr ₁ and Tr ₂ and the resistors R ₁ , R ₂ , R ₃ and R _4, and even if the trigger current due to external noise disappears, the power supply A current constantly flows between the terminals V _DD and V _SS , and a so-called latch-up phenomenon occurs.

[Means for solving problems]

The semiconductor integrated circuit of the present invention can prevent latch-up without increasing the chip size,
The transistor driving the high drive transistor of the output buffer and the transistor region of the input buffer are taken in the region of the cell row, and the cell row is arranged so as to sandwich the wiring region with respect to the high drive transistor area.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram in the vicinity of an input / output buffer circuit of a gate array type CMOS integrated circuit of the present invention. In the figure, 1 is an N-channel MOS at the final stage of a high drive output buffer.
Transistor area, 2 is a P-channel MOS transistor area in the same manner, 3 is an input protection circuit area, 4 is a signal extraction pad, 5 and 6 are basic cell rows, and 7 is between the areas 1, 2, 3, 4 and cell row A wiring area 8 is provided between the cell rows 5 and 6. An N channel MOS transistor 11 is provided in the N channel MOS transistor region 1 and a P channel MOS transistor is provided.
P-channel MOS transistor 12 is provided in the transistor region 2.
Are arranged respectively. Further, the cell rows 5 and 6 have P
N-channel MOS transistor array 15 arranged in well 14
And a P-channel MOS transistor array 16 adjacent thereto are arranged to form a required CMOS circuit. In addition, in this embodiment, the circuit is configured to obtain a desired logical function by the wiring 9. This wiring 9 is the first
The layer wiring 21 and the second layer wiring 22 are formed into a multi-layer structure, and the required connection is achieved by a contact hole, a through hole 25, or the like.

In this embodiment, when each circuit of the input buffer, the output buffer, and the input / output buffer is configured as shown in FIGS. 2 to 4, these are combinations of blocks 31 to 35 surrounded by broken lines in the drawing. Can be configured with. Here, the block 31 comprises the input protection circuit region 3 and
33 is each channel MO of N and P for high drive output buffer
It is composed of S transistors 11 and 12. Further blocks 32, 34, 35
Is formed by using the MOS transistor array 14 in the cell arrays 5 and 6 as a function cell. In the figure, reference numerals 40 to 49 denote respective terminals in each block, which are interconnected by wiring 9 as shown in the figure. In addition, although the blocks 32, 34, and 35 are shown in the logical diagram in FIG.
It goes without saying that the required circuit is composed of S transistors.

According to this structure, the wiring region 7 has no active regions such as transistors at all, and is similar to the wiring region 8. For this reason, the distance W between the high drive P-channel MOS transistor region 2 and the P-well 14 of the N-channel MOS transistor 15 in the cell column 5 becomes extremely large due to the wiring region 7. Therefore, this distance W is equal to the transistor Tr shown in FIG.
The base width W of ₃ is shown, and the base width of the parasitic lateral PNP transistor formed by the regions 2, 7, and 14 in FIG. 1 is increased. As a result, the DC current amplification factor of this parasitic transistor becomes small, and the occurrence of latch-up is effectively prevented.

Further, in this configuration, since the transistor corresponding to the conventional input / output buffer is configured in the cell column, the region 63 in FIG. 6 can be omitted, and the function cell column is newly added to the space obtained by this omission. However, as a result, the chip size is not increased.

〔The invention's effect〕

As described above, according to the present invention, the regions of the transistors that drive the high drive transistors of the output buffer and the transistors of the input buffer are formed in the cell row in which the wiring region is arranged with respect to the high drive transistor region. Therefore, it is possible to effectively prevent the latch-up by increasing the base width of the parasitic transistor generated between the high drive transistor and the other transistors and decreasing the DC current amplification factor thereof. Further, since the transistor region other than the high drive transistor can be omitted and a new cell column can be arranged here, the chip size is not increased even if the transistors in the cell column are configured as function cells.

[Brief description of drawings]

FIG. 1 is a plan layout diagram of a main part of a semiconductor integrated circuit according to the present invention, and FIGS. 2 to 4 are diagrams showing an input buffer, an output buffer, and an input / output buffer. FIG. 1A is a logic circuit diagram. , (B) is a block circuit diagram, FIG. 5 is a layout diagram of a general gate array, FIG. 6 is an enlarged view of a part thereof, FIG. 7 is a schematic sectional view for explaining a parasitic transistor, FIG. 8 is a circuit diagram of the parasitic thyristor. 1 ... Highly driven N-channel MOS transistor region, 2 ...
… Highly driven P-channel MOS transistor area, 3 …… Input protection circuit area, 4 …… Signal extraction pad, 5,6 ……
Basic cell example, 7,8 ... Wiring area, 9 ... Wiring, 14 ... P
Well, 15 ... N-channel MOS transistor such as input buffer, 16 ... P-channel MOS transistor such as input buffer, 21 ... First layer wiring, 22 ... Second layer wiring, 25 ...
Contact, 31-35 …… Block, 40-49 …… Terminal, 51
…… Basic cell row, 52 …… Wiring area, 53 …… I / O buffer, 54 …… Signal extraction pad, 62 …… High drive CMOS transistor area, 63 …… CMOS buffer area such as input buffer, 64 …… High Drive N-channel MOS transistor area, 65 ... High drive P-channel MOS transistor area, 66
... N-type MOS transistor area such as input buffer, 67 ...
... P-type MOS transistor area such as input buffer, 71,72 ...
… P-type source / drain regions, 73,74 …… N-type source /
Drain region, 77 ... N type substrate, 78 ... P well, Tr ₁
~ Tr ₄ …… Parasitic transistor, R ₁ ~ R ₄ …… Resistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/08 331 Z 9170-4M

Claims (1)

[Claims] 1. In a gate array type CMOS integrated circuit having a cell array and an input / output buffer, a high drive transistor region for an output buffer, which is composed of P and N channel MOS transistors, and drives the high drive transistor. Alternatively, a P and N channel transistor region acting as an input buffer is provided, and the transistor for driving this high driving transistor or acting as an input buffer is constituted by a transistor in the cell row, and the cell row and the high driving transistor are provided. A wiring region is arranged between the high-driving transistor and the transistor that drives the transistor, or a wiring to the transistor as the input buffer, between cells in the cell row A semiconductor integrated circuit having wiring formed therein.