JPS6237537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to complementary insulated gate field effect devices fabricated as integrated circuits. Complementary circuits have been widely used in low power, high speed devices such as electronic desk calculators, clocks, and microcomputers. In the conventional structure, an N-channel transistor is formed in the P region, and a P-channel transistor is formed in the N region. In this case, in the region between the N-channel and P-channel transistors, a P ⁺ -type contact is formed in the P region and an N-type contact is formed in the N-type region. In such a structure, when a high-density circuit is configured, the element spacing becomes narrow and a PNPN structure is formed by four regions. Under normal operating conditions as a FET circuit, this structure acts as an SCR, and under the conditions In some cases, it becomes latched. As a result, the FET malfunctions and the circuit becomes unusable.

Conventionally, to avoid this problem, the FETs are spaced far enough apart that parasitic circuits can be ignored. Therefore, it has been difficult to integrate such high-density circuits on one semiconductor substrate.

The complementary inverter circuit shown in FIG. 1 has conventionally been realized as shown in FIG. In FIG. 2, a P-type region (P-well) 2 is formed in an N-type semiconductor substrate 1 by ion implantation, thermal diffusion, etc., and N ⁺ source and drain regions 3 and 4 are formed in this region 2. , an N-channel transistor _Q1 is formed. Surrounding this device area is a P ⁺ diffusion region 5,
5' is formed, region 5 acts as a guard ring to prevent parasitic current, and region 5' is P
- Also works as a contact area to well2. Note that the metallized layer and the insulating layer are not shown for convenience of explanation and to simplify the drawing.

The P-channel transistor Q ₂ also includes P ⁺ source and drain regions 6 and 7 on the N-type substrate 1 . The N ⁺ region 8 serves as a guard ring for the P-channel transistor and as a contact to the N-type substrate 1. To operate as a complementary FET, the gate G ₁ of Q ₁ and the gate G ₂ of Q ₂ are commonly connected and biased according to the circuit of FIG. The guard ring region 5 may be in a floating state,
Alternatively, when used as a substrate contact, it may be connected to an appropriate bias potential. In the P-channel transistor Q ₂ , the source region 6 is connected to V _DD to the drain region 7 and the N ⁺ region 8 serves as a contact to the substrate region 1 . In an N-channel transistor, the source region 3 is grounded. P ⁺ region 5' serves as a contact to P-well region 2. Interconnections between these regions are made from surface metallized regions.

The conventional device shown in FIG. 1 uses transistors Q ₁ and Q ₂ to avoid problems caused by parasitic currents.
are placed sufficiently separated. For example, the space between the P ⁺ region 7 and the P-well region 2 and the space between the N region 1 and the N ⁺ region 4 are set wider than possible based on manufacturing technology. However, if the spacing between the high impurity concentration P ⁺ and N ⁺ regions is inadequate, the circuit becomes equivalent to the one shown in FIG. That is, high impurity concentration regions 6, 8,
5' and 3 form a four-layer PNPN structure and operate as an SCR.

Here, the resistors RN and RP shown in Figure 2 are
This appears in the SCR equivalent circuit shown in the figure. P area 6
becomes the anode of the SCR, and the N region 3 becomes the cathode.
N region 8 and P region 5 are intermediate layers. Viewed as a two-transistor structure, regions 6, 8 and 5'
constitute the emitter, base, and collector of the PNP transistor, respectively, and regions 8, 5', and 3 are
Configure the collector, base, and emitter of the NPN transistor. Potential V _DD is directly connected to P region 6 and also connected to N region 8 via resistor RN.
It is connected to the.

The ground potential is connected directly to N region 3 and also to P region 5' via resistor RP. In this state, the anodic and cathodic junctions are connected to the resistance RN and
Since it is biased by RP, a transient pulse applied to region 5' corresponding to the base will turn on the NPN transistor and the current will cause region 8 corresponding to the base of the PNP transistor to turn on. Be biased. This causes the PNP transistor to conduct and the current biases region 5' as the base of the NPN transistor. That is, when the loop gain of the circuit is greater than unity, the SCR circuit becomes latched because one transistor makes the other transistor conductive.

In other words, when βNPN・βPNP≧1 (βNPN and βPNP are the current amplification factors of the NPN transistor and PNP transistor, respectively), one transistor saturates the other, and all junctions become forward biased.
The total voltage drop across the SCR is approximately equal to the voltage drop across the PN junction plus the terminal characteristics of the saturated transistor,
The anode current becomes limited only by the external circuit.

Conventionally, in order to prevent this kind of SCR effect,
The distance between the P channel region of FET Q ₂ and the N channel region of FET Q ₁ was made large so that parasitic current could be ignored, but this sacrificed circuit density and miniaturization.

The object of the present invention is to solve this problem of SCR operation and to be able to increase the circuit density as much as possible with conventional manufacturing techniques. The purpose of the present invention is to provide semiconductor devices.

A complementary insulated gate field effect semiconductor device according to the present invention is a complementary semiconductor device in which an insulated gate field effect transistor of one conductivity type and an insulated gate field effect transistor of an opposite conductivity type are formed on the same semiconductor substrate. A guard region of one conductivity type is provided in the substrate region of the transistor of one conductivity type between the transistors, and the guard region is connected to the same bias potential as the source region of the transistor of the opposite conductivity type.
Alternatively, between the two transistors, a guard region of one conductivity type formed near the transistor of one conductivity type is in contact with the substrate region of the transistor of the opposite conductivity type, and is connected to the same potential as the substrate region.

Next, one embodiment of the present invention will be described with reference to FIGS. 4 and 5.

In FIG. 4, first, a P-type region (P-well) 12 is formed by ion implantation into an N-type substrate 11 by thermal diffusion, etc.
N ⁺ source and drain regions 13 and 14 are formed in these regions, and an N channel transistor is formed.
Q ₁ is formed. An N ⁺ diffusion region 15 is formed surrounding this device region 12 so as to be in contact with the N type substrate 11, and is used as a guard ring to prevent parasitic current in the region, or as a P-well 12.
A diffusion region 15' is provided, which also serves as a contact region to. Also, in the P channel transistor,
P ⁺ source and drain regions 16 and 17 are provided on an N-type substrate 11 . N ⁺ region 18 serves as a guard ring for the P-channel transistor and as a contact to N-type substrate 11. Here, in order to operate as a complementary FET as shown in FIG. 1, the gate _G1 of the N-channel transistor _Q1 and the gate _G2 of the P-channel transistor _Q2 are connected in common, and the input _I It is connected and used as input I _N.
The drain 14 of the N-channel transistor Q ₁ and the drain 17 of the P-channel transistor Q ₂ are commonly connected and output OUT. P ⁺ area 1
5' and the source of transistor Q ₁ are commonly connected to ground potential, N ⁺ region 15, transistor Q ₂
The source 16 and the N ⁺ region 18 are commonly connected to the power supply _VDD .

Further, the substrate 11 is also biased to the power supply V _DD from its back side. By doing this, the opposite conductivity type (P) type region 12 can be exposed to V _S only from its surface.
Since it cannot take _S (ground) potential, parasitic
The P ⁺ region 16 absorbs a part of the collector current of the PNP transistor, and since the N-type substrate 11 is biased to the power supply V _DD from both the front and back sides of the N-type substrate 11,
The resistance RN' with respect to the substrate 11, particularly the N ⁺ region 18, is reduced to a level that does not continue the turn-on operation of the NPN transistor.

To explain this using the equivalent circuit shown in FIG. 5, the P region 16 forms an anode and the N region 13 forms a cathode. Regions 18, 15' are intermediate layers. Area 1
6, 18 and 15' form the emitter, base and collector of the PNP transistor, and region 1
8, 15' and 13 form the emitter, base and collector of the NPN transistor. N type guard region 15 is connected to N type substrate 11 and positive potential _VDD . Therefore, in the operating state, a transient pulse is applied to the base 15', turning on the NPN transistor, at which time the base 15'
A portion of the collector current from to collector 13 is collected by N region 15 and flows to _VDD . This reduces the base current in the base 18 of the PNP transistor, reducing its tendency to turn on and preventing saturation. Also, since RN' is connected to the positive potential V _DD from above and below the N-type substrate, it is very small, and the NPN transistor has even less tendency to turn on.

Therefore, the latch phenomenon caused by the SCR effect is reduced, and these phenomena can be dealt with without increasing the chip area.

In other words, the P channel region has V _DD from the front and back sides of the board.
The purpose is to reduce the resistance RN' to absorb a part of the collector current of the parasitic NPN transistor and make the loop gain smaller than 1. As a result, a major advantage of the present invention is that the space between adjacent diffusion regions can be reduced.

Although the present invention has been described above with respect to the case where an N-type substrate is used, the present invention can be similarly applied to the case where a P-type substrate is used. Further, the circuit connection of each FET is not limited to an inverter.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an inverter circuit using complementary insulated gate field effect transistors.
FIG. 2 is a diagram showing a cross-sectional structure of a conventional complementary insulated gate field effect semiconductor device, FIG. 3 is a diagram showing an equivalent circuit of an SCR structure resulting from the structure of FIG. 1, and FIG. 4 is a diagram showing a complementary insulated gate field effect semiconductor device according to the present invention. 1 shows a cross-sectional structure of an insulated gate field effect semiconductor device. FIG. 5 is a diagram showing an equivalent circuit of the SCR structure resulting from the structure of FIG. 3. 1, 11...N-type semiconductor substrate, 2, 12...P
-well, 3, 13...N ⁺ source, 4, 14...
N ⁺ drain, 5,15'...P ⁺ guard ring, 1
5...N ⁺ guard ring, 6,16...P ⁺ source, 7,17...P ⁺ drain, 8,18...N ⁺
Guard ring.

Claims (1)

[Claims] 1 Complementary type in which an opposite conductivity type well region is provided in a semiconductor substrate of one conductivity type, an insulated gate field effect transistor of one conductivity type is formed in the well region, and an insulated gate field effect transistor of the opposite conductivity type is formed in the substrate. In the semiconductor device, a guard region of one conductivity type with higher impurity concentration than the one conductivity type semiconductor substrate is provided spanning the surface of the well region of the opposite conductivity type and the surface of the semiconductor substrate of the one conductivity type, and the guard region is of the opposite conductivity type. A complementary insulated gate field effect semiconductor device, characterized in that it is connected to the same potential as one of the source and drain of the transistor and at least one of the substrate region of the opposite conductivity type transistor.