JPS58186947A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the erroneous operation due to the operation of a parasitic transistor by forming a region, which is the same conductive type as a collector region and to which a bias voltage is applied, between adjacent transistors. CONSTITUTION:Equal N type regions 3'' are formed between the collector regions of transistors Tr1, Tr2, an N<+> type region 6' is formed in the region 3'', electrodes 8'' are further formed, and the prescribed voltage V is applied. In this embodiment, V=Vcc (power source voltage). Accordingly, a parasitic N-P-N type transistor Tr4 which has as a collector the collector of the transistor Tr1, as a base the region 4 and as an emitter the collector of the transistor Tr2, and a parasitic N-P-N type transistor Tr5 which has as a collector the region 3'', as a base the region 4, and as an emitter the collector of the Tr2 are composed. This voltage V becomes the collector of the transistor Tr5, thereby performing the operation of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an integrated circuit device (IC) K having a structure in which a parasitic transistor is formed.

In integrated circuit devices, especially in integrated circuit devices such as bipolar integrated circuits in which each element is separated by a PN junction, parasitic NPN) transistors and parasitic PNP) transistors often operate, which may interfere with normal circuit operation. .

Figure 1 shows 1. 1 is a partial cross-sectional view showing a conventional integrated circuit,
In particular, the formation of a parasitic NPfl transistor will be explained with reference to this. In FIG. 1, N+ buried region 2
An N-type epitaxial layer 10 is formed on a P-type substrate 1 having a P-type insulating layer 4, and an island region 3 serving as a collector region is formed by a P-insulating layer 4. Each island region 3 is provided with a P-type base region 5, and an emitter region 6 is formed in this base region.

6' is a region where the number of collector electrodes is shown. An insulating layer 7 is provided on the surface, and collector, base, and emitter electrodes 8 are provided by forming predetermined openings in this layer. 1st
The integrated circuit shown in the figure has two transistors Tr 1 , Tr2t- arranged next to each other.

In this structure, a parasitic NPN transistor is formed in which the collector region 3 of the transistor Tri is used as a collector, the insulating region 4 is used as a base, and the collector region 3 of the transistor Tr2 is used as an emitter. Therefore, the price circuit diagram is as shown in Figure 2. Here, if the transistors Tri, 2 are operating normally, each collector C1, C
Since mK is supplied with a voltage and region 4 is normally supplied with a ground potential, the parasitic transistor T r 3 does not operate; however, if the transistor Tr2 is used, for example, with an open collector, i.e. When the collector C2 is connected to an external terminal, the collector C2 of the transistor 2 is exposed to the external shadow I.
N (e.g., a noise voltage). In this case, since the space between the pin and the emitter of the parasitic NPN transistor Tr3 is forward biased, the parasitic transistor Tr3 operates. Therefore, even if transistor 1 is cut off, transistor T
The potential of the collector C1 of the transistor Tr2 becomes approximately equal to the potential of the collector C2 of the transistor Tr2, and an undesired voltage is applied to the collector 1 of the transistor Tr1, causing the circuit to malfunction.

An object of the present invention is to provide an integrated circuit that prevents malfunctions due to the operation of parasitic transistors.

A semiconductor device according to the present invention is characterized in that a region having the same conductivity type as the collector region and to which a bias voltage is applied is provided between adjacent transistors.The present invention will be described in detail below with reference to the drawings.

3 and 4 are plan and cross-sectional views showing one embodiment of the present invention. In this embodiment, the transistor Trl
, one same N-type region 31 for each collector region 3 of Tr2.
is provided. This region 3''t'i is formed by dividing the epitaxial layer 10 with an insulating region 4.

An N+ region 6'' is provided within the region 3°, and an electrode 8' is further provided to which a predetermined potential ■ is applied. (Pace-emitter voltage V of parasitic transistor
! IE), and in this example, ■
= Vcc (power supply voltage). Therefore, a parasitic NPN transistor Tr4 whose collector is the collector of the transistor Trl, a region 4 is the pace, and an emitter is the collector of the transistor Tr2, and the region 3'' is the collector and the region By constructing a parasitic NPN (NPN) transistor Tr5 with the collector of Tr2 as the emitter and with the collector of Tr2 as the emitter, its equivalent circuit diagram becomes as shown in Fig. 5.In other words, the region Q It is characterized in that it is provided between the transistors Trl and Tr2.This voltage (2) is for the region 3'' to serve as the collector of the parasitic transistor Tr5 and to operate the transistor.

According to such a configuration, due to the above-mentioned cause, the transistor 2
If the collector C2 of is negatively biased, the parasitic NPN
) Transistor T r 5 operates. Therefore, parasitic NP
Since the output voltage of the N transistor Tr4 becomes the voltage ■, the parasitic NPN transistor Tr4 does not operate, and therefore the potential of the collector C1 of the transistor Tr1 is maintained at a normal level. Note that the transistor Trl may also be an open collector, and in this case, the influence of the transistor Trl on the transistor Tr2 is also prevented. Further, the number is not limited to two, but the same applies to three or more.

As described above, according to the present invention, it is possible to prevent the flipping operation caused by the parasitic transistor without adding any additional manufacturing steps.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional integrated circuit device in which two NPN transistors are adjacent to each other, and FIG. 2 is an equivalent circuit diagram thereof. FIG. 3 is a plan view showing the structure of an integrated circuit device according to the present invention, FIG. 4 is a sectional view taken along line II' in FIG. 3, and FIG. 5 is an equivalent circuit diagram thereof. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type buried layer, 3... N-type epitaxial region, 4...
... P type insulating field, 5 ... P type layer (pace), 6 ... N + type layer (emitter and collector), 7 ... insulating film, 8...Metal electrode.

Claims (1)

[Claims] A semiconductor device having at least two transistors arranged adjacent to each other, characterized in that a region having the same conductivity type as the collector region and to which a bias voltage is supplied is interposed between the collector regions of each transistor. semiconductor devices.