JP3117260B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a method for preventing latch-up of a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, particularly a MOS type semiconductor integrated circuit composed of an insulated gate type field effect transistor (hereinafter referred to as a MOS transistor), when a surge voltage due to static electricity is applied to its input terminal, It is known that internal elements are destroyed. Therefore MO
In an S-type integrated circuit, an input protection circuit is provided at an input portion thereof.

The applicant of the present invention has proposed a MOS type integrated circuit having this kind of input protection circuit, in which the input terminal is P ⁺ A device having an input protection circuit without connecting the structure has been proposed (Japanese Patent Application No. 3-286602). FIG. 6 is a circuit diagram for explaining this proposal, wherein 1 is an IC (integrated circuit) input terminal, 2 is an input protection circuit, 3 is an IC internal circuit, 4 is an output terminal, 5 is a power supply Vcc, 6, 7 Is an NPN bipolar transistor of the input protection circuit 2, and 8 is the same resistor. Transistor 7
Is configured using the source and the drain of the MOS transistor as an emitter and a collector and using the substrate as a base. However, an NPN bipolar transistor itself may of course be used. The transistor 6 may be an element equivalent to an NPN transistor.

Until now, an input protection circuit as shown in FIG.
When laying out on the conductor chip,
It was designed out. Here, 11 is the portion of the N-type layer of the chip.
Indicates the minute, and 12 indicates the end of the chip. 13 is a tran
The P-well layer (base layer) forming the transistor 6 and 14
Mitter layer, 15 is a collector layer, 16 is P⁺ Guard ring
(A part for stabilizing the potential of the P-well 13), 17 is a power supply
This is a portion for applying the voltage Vcc. 18 is the transistor 7
P-well layer (base layer) for forming a gate, 19 is a collector
Layer, 20 is an emitter layer, 21 is P⁺ In the guard ring
You. Each emitter 14 and each collector 19 are bonded in common.
Connected to the operating pad 22. 23 is the N substrate 11
A source diffusion region of a P-channel transistor to be formed;
24 surrounds the P-channel transistor
N to stabilize the potential of the N substrate 11⁺ In the guard ring
You.

That is, in the pattern arrangement of FIG. 7, the transistor 7 is arranged on the internal circuit side (corresponding to the source diffusion region 23 and the guard ring 24), and the transistor 6 is arranged on the edge side of the chip farther from the transistor 7 . FIG. 8 shows a latch-up forming circuit generated at this time.

In FIG. 8, T1, T2, and T3 indicate parasitic bipolar transistors forming a latch-up circuit (thyristor circuit). The transistor T1 is formed by an N-substrate bias guard ring 24, a P well 18, and a collector layer 19. The transistor T2 is formed by the source diffusion layer 23, the N substrate 11, and the P well 18. The transistor T3 is formed by the guard ring 24, the P well 18, and the emitter layer 20. 31 indicates the resistance of the N substrate 11 and 32 indicates the resistance of the P well 18.

[0007] The latte-up operation of FIG. 8 is as follows. When a negative trigger (surge) voltage is applied from the pad 22, the collector layer 19 is pulled more negative than ground. Then, the transistor T1 is turned on, and the potential at the point A is changed to the power supply Vc.
lower than c. The potential at point A is "Vcc-VF" (VF
Is lower than the forward voltage of the PN junction), the transistor T2 turns on and the potential at the point B rises. When the potential at the point B exceeds VF, the parasitic transistor T
3 turns on. Then, even if the trigger input of the pad 22 returns to the ground level, the thyristor current continues to flow by the transistors T1, T3 and T2. At this time, the potential of the input pad 22 is set higher than the ground level by "potential at point B-VF".
If the current is increased to such a value, no current flows through the transistor T1, but the thyristor current continues to flow due to the transistors T3 and T2. Such a latch-up phenomenon occurs because the transistor 7, the source diffusion region 23 and the guard ring 24 are too close to each other as shown in FIG. It is because.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a semiconductor integrated circuit having a pattern arrangement that can improve the latch-up resistance without changing the chip size at the time of laying out the chip.

[0009]

According to the present invention, an emitter and a collector of a first NPN transistor are connected between an input terminal of an integrated circuit and a power supply, and a first NPN transistor is connected between the input terminal and ground. The first transistor and the second transistor are connected by connecting the emitter and the collector of two NPN transistors.
An input protection circuit in which the base of the transistor
An N-type region for mold substrate bias and a source diffusion region of a P-channel transistor provided on the N-type substrate, wherein an emitter and a base of a second NPN transistor are provided with respect to the N-type region and the source diffusion region. To the first NP
It is characterized in that it is arranged farther from the N-type transistor. Further, according to the present invention, an emitter and a collector of a first NPN transistor are connected between an input terminal of an integrated circuit and a power supply, and a second NPN transistor is connected between the input terminal and ground.
An input protection circuit which connects the emitter and the collector of the N-type transistor and grounds the bases of the first transistor and the second transistor; an N-type region for N-type substrate bias; and a P-channel type provided on the N-type substrate. A source diffusion region of the transistor;
The arrangement direction of the emitter and base of the transistor is N
It is characterized in that the arrangement relationship intersects the mold region and the source diffusion region. Further, according to the present invention, an emitter and a collector of a first NPN transistor are connected between an input terminal of the integrated circuit and a power supply, and an emitter and a collector of the second NPN transistor are connected between the input terminal and ground. An input protection circuit connected to the base of the first and second transistors, and an N-type substrate bias N-type region and a source diffusion region of a P-channel transistor provided on the N-type substrate. Wherein a first NPN transistor is disposed between the N-type region and the source diffusion region and a second NPN transistor.

That is, according to the present invention, the second transistor causing the latch-up phenomenon is located farther from the N-type region and the source diffusion region than the first transistor, and the N-type region and the source diffusion region By making the opposite side of the second transistor smaller, the latch-up phenomenon is less likely to occur.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a pattern layout diagram of the embodiment, which is an example of a case where it is made to correspond to that of the above-mentioned conventional example, and corresponding portions are denoted by the same reference numerals.

A feature of the embodiment of FIG. 1 is that the arrangement of NPN transistors 6 and 7 is different from that of the prior art of FIG.
That is, the patterns are replaced with each other. With such a structure, the transistor 7 can be farther from the source diffusion layer 23 and the guard ring 24 than the transistor 6. That is, the collector layer 19 and the emitter layer 20 of the transistor 7 serving as a trigger current source for latch-up can be separated from the internal circuit (in this case, the source diffusion layer 23 and the guard ring 24). As a result, the transistors T1 and T3 constituting the parasitic thyristor can be eliminated, so that the thyristor current path flowing between the power supply Vcc and the ground can be cut off, and the latch-up phenomenon can be prevented.

FIG. 2 shows a second embodiment of the present invention. In this embodiment, the arrangement of the emitters and collectors of the transistors 6 and 7 is set in a parallel state, and the extending direction of these and the arrangement direction of the emitters and collectors of the transistors 6 and 7 intersect between the internal circuit and the chip edge. The arrangement is as follows. With such an arrangement, the opposing sides of the source diffusion layer 23, the guard ring 24, and the emitter 20 and the collector 19 of the transistor 7, which effectively work to cause the latch-up, are small. It can be hardly generated.

FIG. 3 shows a third embodiment of the present invention. In this embodiment, although the transistor 7 is closer to the internal circuit than the transistor 6, the collector 19 of the transistor 7,
Since the arrangement direction of the emitters 20 intersects the source diffusion layer 23 and the guard ring 24 as the internal circuit, the opposing sides of these layers 23 and 24 and the layers 19 and 20 become very small. , Also makes it difficult for latch-up to occur.

FIG. 4 shows a fourth embodiment of the present invention. In this embodiment, the transistor 6 and the pad 22 are arranged between the transistor 7 and the internal circuit. Even in this case, the transistor 7 can be kept away from the internal circuit.
Again, latch-up hardly occurs.

FIG. 5 shows a fifth embodiment of the present invention. Also in this embodiment, as in the embodiment of FIG. 1, the arrangement of the transistor 7 is farther from the internal circuit than the transistor 6, so that latch-up hardly occurs.

The distance between the transistor 7 and the internal circuit, which may cause the latch-up, and the length of the opposing sides of the emitter 20, the collector 19 and the internal circuit are made as small as possible. Was. By the way, by adopting the present embodiment, the layout having the withstand capacity of about 300 mA can be improved to have the withstand capacity of 500 mA or more at the ambient temperature of 85 ° C., the power supply voltage Vcc = 5 V, and the current pulse application method. Note that the present invention is not limited to the embodiments, and various applications are possible, such as devising an arrangement relationship between the internal circuit and the transistor 7.

[0018]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of greatly improving the latch-up resistance.

[Brief description of the drawings]

FIG. 1 is a plan view of a pattern according to a first embodiment of the present invention.

FIG. 2 is a plan view of a pattern according to a second embodiment of the present invention.

FIG. 3 is a plan view of a pattern according to a third embodiment of the present invention.

FIG. 4 is a pattern plan view of a fourth embodiment of the present invention.

FIG. 5 is a plan view of a pattern according to a fifth embodiment of the present invention.

FIG. 6 is an electrical equivalent circuit diagram of the pattern.

FIG. 7 is a plan view of an integrated circuit pattern before the improvement of the present invention.

FIG. 8 is an equivalent circuit diagram for explaining a latch-up operation by the circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Input protection circuit, 11 ... Chip, 12
... Chip end, 13, 18 P well, 14, 20 emitter layer, 15, 19 collector layer, 16, 21 guard ring, 22 pad (input terminal), 23 source diffusion layer, 24 guard ring , Vcc ... power supply.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-51-137385 (JP, A) JP-A-58-48960 (JP, A) JP-A-63-202056 (JP, A) JP-A-1- 140657 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8249 H01L 21/8238 H01L 27/06 H01L 27/092

Claims (4)

(57) [Claims] 1. An emitter and a collector of a first NPN transistor are connected between an input terminal of an integrated circuit and a power supply, and an emitter and a collector of a second NPN transistor are connected between the input terminal and ground. An input protection circuit connected to the base of the first and second transistors, and an N-type substrate bias N-type region and a source diffusion region of a P-channel transistor provided on the N-type substrate. An emitter of a second NPN transistor with respect to the N-type region and the source diffusion region;
A semiconductor integrated circuit, wherein a base is arranged away from a first NPN transistor. 2. An emitter and a collector of a first NPN transistor are connected between an input terminal of an integrated circuit and a power supply, and an emitter and a collector of a second NPN transistor are connected between the input terminal and ground. An input protection circuit connected to the base of the first and second transistors, and an N-type substrate bias N-type region and a source diffusion region of a P-channel transistor provided on the N-type substrate. The arrangement direction of the emitter and the base of the second NPN transistor is the same as that of the N-type region.
A semiconductor integrated circuit having an arrangement relationship crossing a source diffusion region. 3. An emitter and a collector of a first NPN transistor are connected between an input terminal of an integrated circuit and a power supply, and an emitter and a collector of a second NPN transistor are connected between the input terminal and ground. An input protection circuit connected to the base of the first and second transistors, and an N-type substrate bias N-type region and a source diffusion region of a P-channel transistor provided on the N-type substrate. A first NP between the N-type region, the source diffusion region and a second NPN-type transistor.
A semiconductor integrated circuit comprising an N-type transistor. 4. The semiconductor integrated circuit according to claim 1, wherein an emitter and a collector of said NPN transistor are a source and a drain of an N-channel transistor.