JP3141865B2 - Semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electrostatic protection device for a complementary field effect transistor (hereinafter abbreviated as CMOS).

[0002]

2. Description of the Related Art A conventional protection device for a CMOS semiconductor integrated circuit is generally a protection device directly connected to an input or output terminal as shown in Japanese Patent Publication No. 62-37819. That is, a path for discharging directly to a power supply while attenuating a surge voltage coming from a terminal by a resistance means is made.

[0003]

However, in the above-described prior art, as the processing dimensions of the semiconductor integrated circuit have become finer, there have been cases where the conventional method cannot provide sufficient protection. When the semiconductor integrated circuit is miniaturized, the channel length of the transistor becomes shorter than the distance between the P ⁺ and N ⁺ diffusions shown in FIG. For this reason, the diodes 4, 5, and 14 in FIG. 1 do not work, and even the output terminal having a relatively large drain area, which conventionally has a sufficient breakdown voltage, breaks down. The reason is that the punch-through voltage between the source and the drain of the output transistor is lower than the reverse withstand voltage of the drain PN junction, and the surge charge is discharged via the transistor which should be prevented. It is. As a result, there is a problem that the junction immediately below the drain diffusion gate of the output transistor is destroyed by a low surge voltage.

Accordingly, the present invention is to solve such a problem, and an object thereof is to provide a field effect transistor in parallel with a reverse junction between power supplies (Vcc-GND) of a CMOS integrated circuit. By increasing the discharge capability of the surge charge at the reverse junction, it is possible to provide a protection device that can withstand the same level of surge voltage as in the past even when an output transistor with a shorter channel length is used. is there.

[0005]

According to the protection device of the present invention, one end is connected to a wiring connecting an input or output terminal and a gate of an input transistor or a drain of an output transistor, and the other end is connected to a power supply or a ground. An insulated gate field-effect transistor is provided in which the first and second diodes, one of a source and a drain, are connected to the power supply, and the gate is connected to an off-side potential via a resistor.

[0006]

FIG. 1 shows a protection circuit according to an embodiment of the present invention, in which a CMOS inverter is used as an output circuit. FIG. 3 shows an example of a plan pattern diagram of an integrated circuit in a portion surrounded by a broken line frame 13 in FIG. FIG. 4 is a diagram showing the cross-sectional structure of FIG. 3 focusing on the diffusion portion. FIG. 2 is a diagram illustrating an example of a protection circuit when the concept of the present invention is applied to an input terminal.

In FIG. 1, terminal 1 is a power supply,
In a general circuit, a voltage of several volts is applied between the terminal 3 and the ground during operation. Terminal 2 is a P-channel MOS
An output terminal of the inverter including the transistor 11 and the N-channel transistor 12.

P channel MOS transistor 9 is a normally non-conductive transistor having a source and a gate connected to power supply Vcc and a drain connected to ground 3. The channel length of the transistor 9 is the same as the shortest channel length of the transistor in the integrated circuit. Transistor 1
The channel lengths of 1 and 12 are slightly longer than those of the transistor 9. When the channel length of the transistors 11 and 12 is not increased, a resistor larger than the resistors 4 and 5 is provided at the drains of the transistors 11 and 12 separately from the resistor 10.
By doing so, the discharge threshold voltage of the surge charge is minimized in the path A or B in FIG. A path through the opposite direction of the diodes 4 and 5 or through the channels of the transistors 11 and 12 does not form a discharge path unless the voltage is higher than the paths A and B. Therefore, the surge charge flows through the paths A and B with priority.

The resistors 8 and 10 are protection resistors and are formed by using a conductive material of a semiconductor integrated circuit such as diffusion or polycrystalline silicon. Diodes 4,5, P ⁺ n used in the conventional protection device ^-, N ⁺ P ^- at the junction, is connected between the terminal 2 and the power supply 1 and 3. The resistances 6, 7, 16 are P-well and N-well resistances which are usually formed when the diodes 4, 5, 14 are formed. When the surge charge flows, the surge voltage is divided by the resistors 6 and 7 and the transistor 9, and functions to increase the breakdown voltage of the transistor 9.
The resistance 10 is a resistance of 0 Ω to several 100 Ω added to increase the surge withstand voltage when the drain area of the output transistor is small. FIG. 3 shows a case where the resistor 10 is not provided. In the present invention, the surge charge applied to the OUT terminal 2 is discharged to the power supply terminals 1 and 3 following the path A or B in FIG. The path A is a case where the OUT terminal 2 receives a negative surge voltage with respect to the Vcc terminal 1. On the other hand, the path B is a case where the OUT terminal receives a positive surge with respect to the GND terminal 3. In this case, since the diodes 4 and 5 are biased in the forward direction, they are not easily broken. When a high-voltage surge is applied between the source and the drain, the non-conductive P-channel transistor 9 generates a punch-through, a parasitic PNP composed of a source, a drain and a sub
The bipolar transistor is turned on, and a surge current flows. At this time, since the resistors 6 and 7 limit the surge current and divide the surge voltage, the transistor 9 is less likely to be destroyed than when the surge current flows through the transistors 11 and 12. Therefore, the channel width of transistor 9 is
In order to reduce current concentration, it is desirable to make the length as long as possible. As shown in FIGS. 3 and 4, the transistor 9
Since the transistor can be formed in the sub-sub-region, a transistor having a long channel width can be manufactured without requiring a large integrated circuit area. Although not shown in FIG. 3, it is necessary to uniformly reduce the resistance of the diffusion portions forming the diodes 4 and 5 by metal wiring to minimize the impedance of the paths A and B.

According to the present invention, it is clear that the transistor corresponding to the transistor 9 may be an N-channel MOS transistor, or a P-channel MOS transistor and an N-channel MOS transistor may be provided in parallel. Further, as shown in FIG. 2, the protection circuit of the present invention can be applied to the input terminal based on the same concept.

[0011]

As described above, according to the present invention, the discharge path of the surge charge can be optimized according to the processing dimensions of the semiconductor integrated circuit. And a protective device with high reproducibility can be obtained. Transistor 9 is directly connected to OU
Since it is not connected to the T terminal, it does not affect the original circuit operation. Furthermore, the second using sub-sub area
Since a MOS transistor can be formed, it is advantageous for integration and has a high degree of freedom in application. Further, by arranging the second MOS transistor near the pad, the layout can be performed in the vicinity of the protection element, uniform discharge can be achieved, and the area around the pad can be used effectively.
An increase in chip area can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a protection device according to the present invention.

FIG. 2 is a diagram showing a configuration when the present invention is applied to an input terminal.

FIG. 3 is a schematic diagram showing an integrated circuit pattern of the protection device of the present invention.

FIG. 4 is a sectional view of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Power supply Vcc 2 ... Output terminal 3 ... Ground GND 4, 5 ... Protection diode 9 ... P-channel MOS transistor 8, 10 ... Protection resistor 11, 12 ... Output transistor

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8238 H01L 27/04 H01L 27 / 06 H01L 27/092 H01L 29/78

Claims (3)

(57) [Claims] An input terminal or an output terminal, a first MOS transistor connected from the input terminal or the output terminal via a wiring, and one end connected to the wiring and the other end connected to a first power supply. A first surge conducting means connected to a first power supply and a second surge conducting means having one end connected to the wiring and the other end connected to a second power supply; A second MOS transistor having a source connected to a power supply, a drain connected to the second power supply, and a gate connected to a potential which is normally non-conductive; and a channel length of the second MOS transistor is The first
The drain region of the second MOS transistor is set to be shorter than the channel length of the second MOS transistor and is connected to a first conductivity type semiconductor substrate constituting the semiconductor device and a second conductivity type well region formed on the semiconductor substrate. A semiconductor integrated device, which is a diffusion layer formed to extend over. 2. The semiconductor integrated device according to claim 1, wherein said second MOS transistor is arranged near a pad. 3. The semiconductor device according to claim 2, wherein a channel length of a MOS transistor other than said first MOS transistor and said second MOS transistor is equal to or longer than a channel length of said second MOS transistor. apparatus.