JPS5819137B2 - Complementary MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MO8I-transistor (hereinafter referred to as C-MOS).
This invention relates to prevention of the thyristor effect (referred to as latch-up phenomenon) due to a group of parasitic transistors in a transistor (referred to as a transistor).

Generally, as shown in FIG. 1, in a C-MOS transistor, a P-type head region 2 is formed on an N-type semiconductor substrate 1 having a relatively high resistance by diffusion or ion implantation.
:Inside N+ type source region 3 and N+ type drain region 4
are provided adjacent to each other, and a P+ type contact region 5 for leading out the P type head region 2 is further provided to form an N-channel MOS transistor.

A P + -type drain region 6 and a P -type source region 7 are provided in close proximity to the mature N-type semiconductor substrate 1 , and an N + -type liquid contact region 8 is further provided for leading out the N-type semiconductor substrate 1 .
A channel MOS transistor is formed.

On the other hand, 9 is a P+ type region forming a diode D for preventing electrostatic damage at the input, or a P+ type region for cross-under wiring.
Although it is a type region, it will be explained below as an input diode D for preventing electrostatic damage.

On the surface of the N-type semiconductor substrate 1 on which the above-mentioned N-channel MOS transistors, P-channel MOS transistors, etc. are formed, there is an insulating oxide film 10 having windows in each region.
An electrode is provided in each window, and an electrode is also provided on the channel, that is, on the oxide film 10 between the gate region and the drain region.

The source electrode 11 of the N-channel MOS transistor is P
It is connected to the electrode 12 of the + type contact area 5 and the power supply voltage VS
S is applied.

Also, the source electrode 13 of the P-channel MOS transistor
is connected to the N+ type liquid contact region 8 electrode 14 and the power supply voltage V
DD is applied.

Furthermore, the drain electrode 15 of the N-channel MO8 I-transistor and the drain electrode 16 of the P-channel MOS transistor are connected to become the output of the C-MOS transistor, and the N-type source region 3 and the N+-type drain region 4 of the N-channel MO8) transistor are connected. A gate electrode 17 provided on the oxide film 10 between the P channel MOS transistor and a gate electrode 18 provided on the oxide film 10 between the P+ type drain region 6 and the P type source region 7 of the P channel MOS transistor are connected.
Further, it is connected to an electrode 19 provided on the P-type region 9 forming a diode D for preventing electrostatic discharge damage, and serves as an input to a C-MOS transistor.

In the C-MOS transistor configured as described above, parasitic transistors and the like occur as shown in the equivalent circuit of FIG. 2, and a latch-up phenomenon, which will be described later, occurs.

To explain the equivalent circuit in Figure 2, the C-MOS transistor is formed by a P-MOS transistor and an N-MOS transistor, and a diode D for preventing electrostatic damage is provided at the input between it and the power supply voltage VDD. .

Trl is a PNP parasitic transistor having the P+ type source region 7 as the emitter, the N type semiconductor substrate 1 as the base, and the P type region 2 as the collector, and Tr2 has the N type semiconductor substrate 1 as the collector and the P type region 2 as the base. , is an NPN type parasitic transistor having the N++ source region 3 as an emitter.

Further, Trl and Tr2 form a parasitic thyristor with a PNPN junction as an equivalent circuit.

Further, the resistance R1 is an internal resistance of the N-type semiconductor substrate 1 from the N+ type liquid contact region 8 to the P-type region 2, and isometrically a bias resistance located between the emitter base of Trl.

On the other hand, the resistance R2 is an internal resistance of the P-type region 2 from the Vi-type contact region 5 to the N-type semiconductor substrate 1, and is a bias resistance located equimetrically between the base and emitter of the Tr2.

In addition, Tr3 has an N-type semiconductor substrate 1 as a collector and a P-type region 2 as a collector.
NP with base, N+ type drain region 4 emitter
It is an N-type parasitic transistor, and the resistor R3 is a P-type region 2.
is the internal resistance of

T r 4 is a PNP type parasitic transistor having the P type region 9 as the emitter, the N type semiconductor substrate 1 as the base, and the P type region 2 as the collector.

Next, the latch-up phenomenon will be explained with reference to FIGS. 1 and 2 mentioned above.

First, the cause of the latch-up phenomenon is thought to be noise at the input or output terminals.

In the case of noise applied to the input terminal in, when the input terminal voltage exceeds the power supply voltage VDD, the diode D for preventing electrostatic damage is forward biased, and the input terminal in
A current flows from the source voltage VDD to the power supply voltage VDD through the diode D, and the gate of the C-MOS transistor is protected.However, the current flowing through the diode D means that a constant current flows from the emitter to the base of Tr4. So Tr
4 becomes conductive, and a collector current flows from the input terminal in through the emitter and collector of Tr4 and the resistor R2 to the power supply voltage EV88, which has a lower voltage than the power supply voltage VDD.

Then, a voltage drop occurs across the resistor R2 due to the collector current, and Tr2 is biased and the base current flows and becomes conductive, so a collector current flows from the power supply voltage 'vDD through the resistor R1 to Tr2. .

This collector current causes a voltage drop across the resistor R1, biasing Trl and making it conductive.
A collector current flows from the power supply voltage DD to the power supply voltage V88 through the resistor R2.

This collector current makes the bias of Tr2 deeper.

Therefore, the current flowing from VDD to vss increases instantly due to the synergistic effect.

Next, in the case of noise applied to the output terminal out, when the output terminal becomes lower than the power supply voltage V, the power supply voltage V
Since base current flows from ps to Tr3 via resistor R3, Tr3 becomes conductive, and collector current flows from power supply voltage VDD to Tr3 via resistor R1.

A voltage drop occurs across the resistor R0 due to the collector current, biasing Trl, and the collector current R2
The current flows to the power supply voltage VSS through the power supply voltage VSS.

Therefore, Tr2 is also biased, and as in the case described above, the current flowing from the power supply voltage VDD to the power supply voltage VSS increases instantly due to the synergistic effect.

The phenomenon explained above is the latch-up phenomenon, and this latch-up phenomenon easily occurs in conventional C-MOS transistors, which prevents the C-MOS transistor from operating normally and can lead to destruction of the C-MOS transistor. I had certain concerns.

The present invention has been made in view of the above-mentioned points, and provides a C-MOS transistor that completely eliminates the conventional concerns.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a sectional view showing an embodiment of the present invention.

This embodiment includes an N++ semiconductor substrate 20 and an N-type semiconductor layer 21.
, P type region 2, N++ source region 3, N0 type drain region 4, P+ type contact region 5, P0 type drain region 6, P+ type source region 7, N0 type contact region 8. and P
Green mold region 9, oxide film 10, electrodes 11 to 19 and 22
It consists of

In FIG. 3, except for the N++ semiconductor substrate 20, the N-type semiconductor layer 21, and the electrode 22, the rest is the same as the conventional example, so the drawing numbers are the same and detailed explanation is omitted.

The N type semiconductor substrate 20 is an N0 type semiconductor with high impurity concentration and low resistance.

On this N0-type semiconductor substrate 20, an N
A type semiconductor layer 21 is provided, for example, by an epitaxial layer or the like.

This N-type semiconductor layer 21 includes a P image region 2, an N++ source region 3, an N-type drain region 4, a P+-type contact region 5, a P+-type drain region 6, a P+-type source region 7, an N-type contact region 8, and a P+-type contact region 5. A mold region 9 is formed.

Further, the electrode 22 is connected to the N-type semiconductor substrate 20 at a power supply voltage vDD.
The C-MOS transistor is fixed to a fixed pad (not shown), and this fixed pad is used as an electrode to apply P+ of the P-channel MOS transistor.
The N+ type source electrode 7 and the N+ type liquid contact region 8 are in contact with each other.

Therefore, the internal resistance of the N-type semiconductor layer 21 between the N-type contact region 8 and the P+ type source region 7 becomes extremely small.

An equivalent circuit diagram of this embodiment formed as described above is shown in FIG.

Parasitic transistors, etc. occur in the same way as in the conventional case, and the equivalent circuit diagram is the same. However, by providing the N-type semiconductor substrate 20 and applying the power supply voltage DD to it, the N-type contact region 8 and the P+ As mentioned above, the internal resistance between the type source regions 7 is extremely small, and when this is expressed in an equivalent circuit, the P+ type source region 7 is the emitter, the N type semiconductor layer 21 is the base, and the P image region 2 is the collector. The internal resistance R1 inserted between the base and emitter of the parasitic transistor Tr1 is
and R4, which has a very low resistance, are connected in parallel.

Therefore, the input terminal voltage exceeds the power supply voltage VDD and Tr2
Even if it becomes conductive, the collector current flowing through Tr2 flows from the N-type semiconductor substrate 20 to the N++ source region 3.

That is, since the current flows through R4, which has a very low resistance, no bias voltage is generated that would make Trl conductive.

Also, when the output terminal voltage becomes lower than the power supply voltage VS S, the collector current flowing through Tr3 is similarly
Since the current flows through Trl, a bias voltage that makes Trl conductive is not generated.

Therefore, the latch-up phenomenon due to the synergistic effect of Trl and Tr2 does not occur.

Furthermore, in the embodiment shown in FIG.
A green contact region 8 is provided and is electrically connected to the P+ type source region 7, but according to the structure of this embodiment, the electrical connection to the N type semiconductor layer 21 is made through the N type semiconductor substrate. 2
0 is electrically connected to the P+ type source region 7.

Therefore, the N-type contact area 8 is unnecessary and can be deleted.

In this case, the resistor R1 is no longer connected to the power supply voltage VDD, and there is no flow path for the current that generates the bias voltage of Trl, so that the latch-up phenomenon can be more effectively prevented.

In the above explanation, the present invention has been explained using an N0 type semiconductor substrate, but even if the structure of the C-MOS transistor is completely reversed and a P+ type semiconductor substrate is used, the effect of the present invention will not be affected. Needless to say, nothing has changed.

As described above, according to the present invention, by using a highly impurity and concentration semiconductor substrate of one conductivity type and applying the power supply voltage VDD to it, the internal resistance that becomes the bias resistance of the parasitic transistor can be significantly reduced. This is beneficial because it reduces and completely prevents the latch-up phenomenon caused by input/output terminal noise.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a C-MOS transistor showing a conventional example, FIG. 2 is an equivalent circuit diagram of the C-MOS transistor shown in FIG. 1, and FIG. 3 is a sectional view showing an embodiment of the present invention. 4
This figure is an equivalent circuit diagram of the embodiment shown in FIG. 3. 2...P-type region, 3...N-type source region, 4...N-type drain region, 5...
...P+ type contact region, 6...P+ type drain region, 7...P+ type source region, 8...
N+ type liquid contact area 9...P+ type area, 10...
... Oxide film, 11-19 ... Electrode, 20.
. . . N++ semiconductor substrate, 21 . . . N-type semiconductor layer, 22 . . . electrode.

Claims (1)

[Claims] 1- A semiconductor substrate of a conductivity type with a high impurity concentration, a semiconductor layer of the same conductivity type and a low impurity concentration provided on the semiconductor substrate, and a semiconductor layer provided on the semiconductor layer with a low impurity concentration. A region of opposite conductivity type is provided within the region. A MOS transistor having a contact region of the same conductivity type and a source region and a drain region of opposite conductivity types, and a MOS transistor having a contact region of the same conductivity type and a source region and a drain region of opposite conductivity types provided in the semiconductor layer. A complementary type M comprising a contact region and a source region provided in the semiconductor layer and the semiconductor substrate are electrically connected to each other.
OS transistor.