JPH01208860A - Latching-up preventing structure of cmos transistor - Google Patents

Abstract

PURPOSE:To prevent lathing-up from occurring by connecting to an external power supply a conductive layer connected to a substrate formed on the bottom of a separating groove provided between conductive wells. CONSTITUTION:The title transistor includes an insulating layer 21 of about 5000Angstrom thickness composed of SiO2 for example, intervened between a semiconductor substrate 1 and a conductive layer 22, and disposed around a heavy metal implantation region 12, the conductive layer 22 in which polycrystalline silicon is buried, and a substrate contact layer of Al for example connected to the upper end surface of the conductive layer 22. The polycrystalline silicon buried in the conductive layer 22 includes a high concentration impurity of the same P-type as that of the substrate 1. The region 12 is connected to the substrate contact layer through the layer 22 and to the external power supply. Holes, which recombine with minority carriers through a life time killer, flow into the power supply VSS as a current As through the layer 22. Hereby, parasitic NPN transistors Q2, Q1 formed between wells 2, 3 are not operated, thus preventing latching-up from occurring.

Description

[Detailed Description of the Invention] [Summary] A CM having a lifetime killer formed by injecting heavy metals into wells of different conductivity types formed in a semiconductor substrate with a low impurity concentration and a region of the semiconductor substrate between the wells.
Regarding OS transistors.

The purpose of this is to prevent latch-up caused by a current caused by majority carriers flowing through a low concentration substrate when minority carriers injected into the semiconductor substrate are recombined by an after-time killer.

A CMOS I comprising a first well containing a high concentration of one conductivity type impurity and a second well containing a high concentration of the opposite conductivity type impurity formed in a semiconductor substrate containing a low concentration of one conductivity type impurity. - in the run risk, a groove formed in the semiconductor substrate region between the first and second wells to separate the first and second wells; a heavy metal implanted region; and connection means provided within the groove for connecting the heavy metal implanted region to an external power source.

[Industrial application field]

The present invention relates to a CMOS run risk structure, and particularly to a structure for preventing latch-up in a CMOS run risk formed using a low concentration substrate.

[Conventional technology]

It is well known that latch-up occurs in CMOS transistors due to parasitic silicon risk. (
For example, “Analysis of CMOS run risk latch-up phenomenon”: Kyomasu et al., IEICE Transactions.

'7B/2 Vol, J61-CNo, 2. pp, 1
06 (197B)) For this purpose, the p-channel MO3) which constitutes the CMOS) run risk (hereinafter p
-MO5) and an n-channel MOS transistor (hereinafter abbreviated as n-MO5), a means for isolating these transistors is provided.

For the purpose of high speed, as shown in FIG. 2, there is a risk of CMOS l-run using a substrate containing a low concentration of impurities and failing to form wells of different conductivity types.

That is, in a semiconductor substrate l such as silicon containing a p-type impurity at a low concentration of, for example, 1.5xlO cm-, a p-type well 2 and an n-type well 3 containing impurities at a higher concentration than the substrate are formed. ing. The impurity concentration in p-type well 2 and n-type well 3 is +5xlO1h, respectively.
cm-' and IxlOI&cn+-'.

In the well 2, there are also a source region 5 and a drain region 6 into which n-type impurities are selectively implanted, and a well contact 14 into which p-type impurities are selectively implanted.

In the n-type well 3, a source region 7 and a drain region 8 into which p-type impurities are selectively implanted, and a well contact 15 into which n-type impurities are selectively implanted are formed.

Roughly, gate electrodes 10 and 11 are formed on the semiconductor substrate 1 between the pair of source/drain regions in each well with a gate insulating layer 9 interposed therebetween. In this way, the p-type well 2 contains an n-MOS, and
A p-MOS is formed in each of the n-type wells 3,
These transistors constitute the CMOS run risk.

In the CMOS run risk shown in FIG. 2, if minority gears (electrons) are injected into the low concentration semiconductor substrate 1, latch-up may occur. As a countermeasure for this, the semiconductor substrate 1 between the p-type well 2 and the n-type well 3
A groove 4 is formed in the region, and the semiconductor substrate 1 immediately below the bottom of the groove 4 is
A heavy metal injection region 12 is provided in which a heavy metal such as gold or platinum, which serves as a lifetime killer, is injected.

Groove 4 is.

The depth is equal to or deeper than wells 2 and 3.

With the above structure, electrons injected into the p-type semiconductor substrate 1 from the n-type source region 5, for example, are transferred to the heavy metal injection region 12.
It recombines with holes, which are majority carriers, through the lifetime killer in Well 2, resulting in a short lifetime.
Latch-up of the CMOS transistor consisting of and 3 is prevented.

[Problem to be solved by the invention]

However, when electrons, which are minority carriers, injected into the semiconductor substrate l are recombined by a lifetime killer, a current is generated by majority carriers, and this current causes a problem of latch-up. This will be explained with reference to FIG. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals.

In FIG. 3, the p-type source region 7, the n-type well 3 and the p-type
Parasitic PNP consisting of type semiconductor substrate 1) Run risk Q
, and a parasitic NPN transistor Q2 consisting of an n-type well 3, a p-type semiconductor substrate 1, and an n-type source region 5. In addition.

The p-type source region 7 is connected to a high voltage power source (Von), and the n-type source region is connected to a low voltage power source (Vss).

Generally, when minority carriers are injected into the base region of a bipolar transistor, the majority carriers recombined with the minority carriers lift to the base electrode, but at this time, since there is resistance in the base region, this creates a potential difference.

In the case of FIG. 3, from the n-type source region 5 to the semiconductor substrate 1
If an electron is injected into the parasitic NPN
The lifetime killer present in the heavy metal implanted region 12 forming the base region of the transistor 2 recombines with holes, which are majority carriers.

The recombined holes flow into the nearest contact 14 (corresponding to the base electrode) of the p-type well 2 as a drift current.

However, since the parasitic resistance (R8; equivalent to the base resistance) caused by the low concentration semiconductor substrate 1, which is the path of this drift current A, is high, a potential drop occurs at +RI. Therefore, the base-emitter of the parasitic NPN run risk Q2 is forward biased, and the current A2 injected from the emitter to the base increases.

As a result, parasitic NP is generated from the contact 15 of the n-type well 3.
N) To the current flowing to the collector with run risk 0□, increases and a voltage drop occurs due to resistor R6.

The parasitic PNP I-run risk Q becomes active and latch-up occurs.

An object of the present invention is to prevent the ruff lump caused by the current generated due to the recombination of minority carriers as described above.

[Means to solve the problem]

The above purpose is to provide a first well containing a high concentration of one conductivity type impurity and a second well containing a high concentration of opposite conductivity type impurity formed in a semiconductor substrate containing a low concentration of one conductivity type impurity. , a source/drain region of opposite conductivity type formed in the first well and a well contact of the one conductivity type, and a source/drain region of the one conductivity type formed in the second well and the opposite conductivity type. type well contact and the first well contact to separate the first and second wells.
and a groove formed in the semiconductor substrate region between the second wells, a heavy metal implantation region formed in the semiconductor substrate region directly below the poem, and a groove formed in the semiconductor substrate region for connecting the heavy metal implantation region to an external power source. A latch-up prevention structure of a CMOS l-run risk according to the present invention is achieved, characterized in that it has a connecting means provided.

[Function] MOS) which constitutes CMOS) run risk was formed. A conductive layer (22) connected to the substrate is formed at the bottom of the isolation groove provided between the wells (2 and 3) of different conductivity.
) to an external power source, the base vi directly under the groove can be
, 'A current caused by majority carriers that flows due to the recombination of minority carriers via the lifetime killer in the pH range is taken out to the outside through this conductive layer (22), so there is a gap between the wells (2 and 3). The parasitic NPN l-run risk Q2 that is formed does not operate and latch-up is prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following drawings, the same parts as in the existing drawings are designated by the same reference numerals.

FIGS. 1(a) and 1(b) are a sectional view and a plan view, respectively, showing essential parts of a CMOS run risk having a latch-up prevention structure according to the present invention.

The illustrated CMOS I-run lister is similar to the conventional CMOS +-run lister shown in FIG.
contain a low concentration of p-type impurity, and are formed in an n-type well 2 and an n-type well 3 . formed in a predetermined region of the semiconductor substrate 1 . n-type source region 5 and drain region 6 formed in well 2 and p-type well contact 14; p-type source region 7 and drain region 8 formed in well 3 and n-type well contact 15; Gate electrodes 10 and 11 are formed on a semiconductor substrate l between each pair of source/drain regions with a gate insulating layer 9 interposed therebetween.

and.

A groove is formed in a region of the semiconductor substrate 1 between the wells 2 and 3, and a heavy metal implantation region 1 in which gold or platinum is implanted is further formed in the v:4 region of the semiconductor substrate 1 directly under the groove.
2 is formed. The width of this groove is about 1 μm,
Its depth is equal to or deeper than that of wells 2 and 3.

Unlike the conventional structure, the CMOS (CMOS) run lister of the present invention has a conductive layer 22. An insulating layer 21 having a thickness of approximately 500 nm and consisting of 9, for example Sing, is interposed between the semiconductor substrate 1 and the conductive layer 22 around the heavy metal implanted region 12.
．． It was connected to the upper end surface of the conductive layer 22.

It has a substrate contact 7123 made of aluminum, for example. Polycrystalline silicon forms the conductive layer 22.

The same p-type impurity as the semiconductor substrate 1 is doped at a high concentration.

With the above structure, the nine heavy metal implanted regions 12 are connected to the substrate contact layer 23 through the conductive layer 22 and connected to a predetermined external power source.

The anti-ruff stubble mechanism according to the structure of the present invention will be explained with reference to FIG. A low voltage power supply (V, . . .
) flows into. The current due to this hole is indicated by A4. Therefore, the current flowing through the parasitic base resistor R8 of the parasitic NPN transistor 2 is small, as in the conventional structure.

Parasitic transistor Q2 does not operate and no latch-up occurs.

In the above embodiments, the case where the semiconductor substrate 1 is p-type has been described; however, the latch-up prevention structure of the present invention can be applied to a CMOS (CMOS) formed using a semiconductor substrate containing a low concentration of n-type impurities. It goes without saying that the same applies to run listers.

Further, although the structure in which the conductive layer 22 fills the trench 4 has been shown.

Since the purpose of the conductive layer 22 is to connect the heavy metal implanted region 12 to an external electrode, it is sufficient that the conductive layer 22 is in contact with the heavy metal implanted region 12 at the bottom of the groove 4.
may be connected to an external power source by a thin wire laid in the hollow groove 4 or by forming another conductive layer insulated from the semiconductor substrate l on the side wall surface of the hollow groove 4. .

〔Effect of the invention〕

According to the present invention, latch-up in a CMOS l-run lister constructed using a semiconductor substrate with a low impurity concentration is prevented, and a high-speed CMOS l-run lister can be provided.

[Brief explanation of the drawing]

Figures 1 (al and b) are a cross-sectional view and a plan view of essential parts showing an embodiment of the rough stubble prevention structure of the present invention. Figure 2 is a schematic diagram showing the structure of a conventional CMOS transistor using a low impurity concentration substrate. Partial sectional view. Figure 3 is a diagram for explaining the mechanism by which latch stub occurs in the CMOS transistor having the structure shown in Figure 2. Figure 4 is a diagram for explaining the mechanism by which latch amplifier is prevented by the structure shown in Figure 1. In the figure. 1 is a half-quad substrate. 2 is a p-type well. 3 is an n-type well. 4 is a trench. 5 and 7 are source regions. 6 and 8 are drain regions. 9 is a gate 1 color edge. layers. IO and 11 are gate electrodes. 12 is a heavy metal injection region. 14 and 15 are well contacts. 21 is an insulating layer. 22 is a conductive layer. 23 is a substrate contact layer. - Strategy 1 The structure of the 254th Kanmon 7cModelta transition desk, Naa, 79 design machine lecture 3 The structure of Fig.

Claims (2)

[Claims] (1) A first well containing a high concentration of one conductivity type impurity and a second well containing a high concentration of the opposite conductivity type impurity, formed in a semiconductor substrate containing a low concentration of one conductivity type impurity; a source/drain region of opposite conductivity type formed in the first well and a well contact of the one conductivity type; a source/drain region of the one conductivity type formed in the second well and the opposite conductivity type; a well contact formed in the semiconductor substrate region between the first and second wells to separate the first and second wells; and a trench formed in the semiconductor substrate region directly below the trench. 1. A latch-up prevention structure for a CMOS transistor, comprising: a heavy metal implanted region; and a connection means provided in the groove for connecting the heavy metal implanted region to an external power source. (2) The connecting means includes a conductive layer formed to fill the groove, and an insulating layer interposed between the semiconductor substrate and the conductive layer above the periphery of the heavy metal implantation region. The latch-up prevention structure for a CMOS transistor according to claim 1, comprising: and a substrate contact layer formed on the conductive layer.