JP2778062B2 - Buffer circuit - Google Patents
Buffer circuitInfo
- Publication number
- JP2778062B2 JP2778062B2 JP63298546A JP29854688A JP2778062B2 JP 2778062 B2 JP2778062 B2 JP 2778062B2 JP 63298546 A JP63298546 A JP 63298546A JP 29854688 A JP29854688 A JP 29854688A JP 2778062 B2 JP2778062 B2 JP 2778062B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- semiconductor substrate
- mos transistor
- well
- buffer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバッファ回路に関し、特に出力電流を制御す
るためのバイポーラ・トランジスタを同一基板に設けた
CMOSバッファ回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit, and more particularly to a buffer circuit in which a bipolar transistor for controlling an output current is provided on the same substrate.
It relates to a CMOS buffer circuit.
従来のCMOS型バッファ回路を図面を参照して説明す
る。A conventional CMOS buffer circuit will be described with reference to the drawings.
第２図は従来のバッファ回路を形成した半導体チップ
の断面図である。FIG. 2 is a sectional view of a semiconductor chip on which a conventional buffer circuit is formed.
Ｎ型半導体基板１にＰウェル２を設け、Ｐウェル２の
表面に絶縁膜を介してゲート12を設け、これをマスクに
してＮ型層4,5を形成し、ＮチャネルMOSトランジスタを
構成する。Ｐウェル２内のＰ型層は接地電源に接続す
る。A P-well 2 is provided on an N-type semiconductor substrate 1, a gate 12 is provided on the surface of the P-well 2 via an insulating film, and N-type layers 4 and 5 are formed using this as a mask to form an N-channel MOS transistor. . The P-type layer in the P well 2 is connected to a ground power supply.
Ｐウェル２以外の基板領域に、ゲート13とＰ型層9,10
を設けてＰチャネルMOSトランジスタを構成し、Ｎ型層
６はVDD電源14に接続する。A gate 13 and P-type layers 9 and 10
Are provided to form a P-channel MOS transistor, and the N-type layer 6 is connected to the VDD power supply 14.
ゲート12と13を接続して入力端子21へ接続し、Ｎ型層
５とＰ型層９とを出力端子22に接続する。Gates 12 and 13 are connected to input terminal 21, and N-type layer 5 and P-type layer 9 are connected to output terminal 22.
上述した従来のバッファ回路は、CMOSトランジスタで
構成されているので、例えば、外部の負荷が何らかの原
因で接地側に短絡すると、Ｐチャネルトランジスタが導
通すると同時に自身の電源からＰチャネルトランジスタ
のオン抵抗によってのみで定められる電流が出力される
事となり、消費電流の増大、電流系の負担大等の状態と
なってしまう。また、能動負荷を駆動する場合において
は、必要十分以上の電流供給を防止する為、出力バッフ
ァ回路出力に制限抵抗を必要とする等の欠点がある。Since the above-mentioned conventional buffer circuit is constituted by a CMOS transistor, for example, when an external load is short-circuited to the ground side for some reason, the P-channel transistor is turned on and at the same time, its own power supply is turned on by the ON resistance of the P-channel transistor. A current determined only by this is output, resulting in an increase in current consumption and a heavy load on the current system. Further, when driving an active load, there is a drawback such that a limiting resistor is required for the output of the output buffer circuit in order to prevent current supply more than necessary and sufficient.
本発明のバッファ回路は、一導電型半導体基板に設け
られた逆導電型のウェルと、前記ウェルに形成されゲー
トが信号入力端子に接続されドレインが出力端子に接続
される一導電型MOSトランジスタと、前記ウェル以外の
前記半導体基板領域に形成されゲートが前記信号入力端
子に接続されドレインが前記出力端子に接続される逆導
電型MOSトランジスタと、前記半導体基板に形成された
逆導電型のベースと該ベース内に形成され前記逆導電型
MOSトランジスタのソースと接続される一導電型エミッ
タと前記半導体基板とで構成されるバイポーラトランジ
スタとを含むバッファ回路において、前記出力端子が外
部の演算増幅器の一方の入力端子に接続され、前記演算
増幅器の他方の入力端子に基準電圧が入力され、前記演
算増幅器の出力端子が前記ベースに接続されて前記バイ
ポーラトランジスタに流れるコレクタ電流を制御するこ
とを特徴とする。The buffer circuit according to the present invention comprises a well of the opposite conductivity type provided in the semiconductor substrate of one conductivity type, a MOS transistor formed in the well and having a gate connected to the signal input terminal and a drain connected to the output terminal. A reverse conductivity type MOS transistor formed in the semiconductor substrate region other than the well and having a gate connected to the signal input terminal and a drain connected to the output terminal; and a reverse conductivity type base formed on the semiconductor substrate. The reverse conductivity type formed in the base;
In a buffer circuit including a bipolar transistor composed of one conductivity type emitter connected to the source of a MOS transistor and the semiconductor substrate, the output terminal is connected to one input terminal of an external operational amplifier, and the operational amplifier A reference voltage is input to the other input terminal of the first amplifier, and an output terminal of the operational amplifier is connected to the base to control a collector current flowing through the bipolar transistor.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。 FIG. 1 is a sectional view of one embodiment of the present invention.
この実施例のバッファ回路は、Ｎ型半導体基板１に設
けられたＰウェル２と、このＰウェル２に形成されゲー
ト12が信号入力端子21に接続されドレインとなるＮ型層
５が出力端子22に接続されるＮチャネルMOSトランジス
タと、このウェル２以外の半導体基板領域に形成されゲ
ート13が信号入力端子21に接続されドレインとなるＰ型
層９が出力端子22に接続されるＰチャネルMOSトランジ
スタと、半導体基板１に形成さＰウェル３をベースと
し、このベース内に形成されＰチャネルMOSトランジス
タのソースとなるＰ型層10と接続されエミッタとなるＮ
型層７と半導体基板をコレクタとして構成されるNPNト
ランジスタとを含んで構成される。In the buffer circuit of this embodiment, a P-well 2 provided in an N-type semiconductor substrate 1 and an N-type layer 5 formed in the P-well 2 and having a gate 12 connected to a signal input terminal 21 and serving as a drain are connected to an output terminal 22. And a P-channel MOS transistor formed in a semiconductor substrate region other than the well 2 and having a gate 13 connected to a signal input terminal 21 and a P-type layer 9 serving as a drain connected to an output terminal 22 And a P-type layer 10 formed in the semiconductor substrate 1 as a base, connected to a P-type layer 10 formed in the base and serving as a source of a P-channel MOS transistor, and N as an emitter.
It comprises a mold layer 7 and an NPN transistor having a semiconductor substrate as a collector.
Ｎ型半導体基板にはVDD電源14によって電位が与えら
れ、Ｐウェル２には接地電位が与えられる。ベース電位
は演算増幅器15によって与えられる。A potential is applied to the N-type semiconductor substrate by the VDD power supply 14, and a ground potential is applied to the P well 2. The base potential is provided by the operational amplifier 15.
演算増幅器15は最大出力電流値によって決められた基
準電源23の電圧とCMOSドレイン出力電圧を比較し、何ら
かの原因で出力端子22の外部に負荷13が付いた場合に起
こる電圧降下を検出し、NPNトランジスタのベース電圧
を下げてエミッタ・コレクタ間電流量を減少させる役割
がある。演算増幅器23により操作されたNPNトランジス
タからの出力電流は、つまりＰチャネルトランジスタの
ソース４への供給電流であり、これにより膨大な電流が
出力端子22に流れ出すのを防止している。The operational amplifier 15 compares the voltage of the reference power supply 23 determined by the maximum output current value with the CMOS drain output voltage, detects a voltage drop that occurs when the load 13 is externally attached to the output terminal 22 for some reason, and detects the NPN. It has the role of lowering the base voltage of the transistor to reduce the amount of current between the emitter and collector. The output current from the NPN transistor operated by the operational amplifier 23, that is, the supply current to the source 4 of the P-channel transistor, prevents an enormous current from flowing to the output terminal 22.
NPNトランジスタのベースはＰウェル２と同時に形成
でき、エミッタはＮチャネルMOSトランジスタのソース
・ドレイン領域と同時に形成できるので、製造工程数が
増加することはない。Since the base of the NPN transistor can be formed simultaneously with the P-well 2 and the emitter can be formed simultaneously with the source / drain regions of the N-channel MOS transistor, the number of manufacturing steps does not increase.
上記実施例では、Ｎ型半導体基板にCMOSトランジスタ
とNPNトランジスタを形成した場合を説明したが、すべ
ての極性を逆にしてＰ型半導体基板を用いても本発明を
実施できることは明らかである。In the above embodiment, the case where the CMOS transistor and the NPN transistor are formed on the N-type semiconductor substrate has been described. However, it is obvious that the present invention can be implemented by using the P-type semiconductor substrate with all the polarities reversed.
以上説明したように、本発明は従来のCMOSプロセスで
基板構造を変更する事なく、基板をコレクタに、基板電
位から分離されたウェルをベースとし、分離されたその
ウェル電位から更に分離された拡散層をエミッタするバ
イポーラ構造トランジスタを設ける事により、エミッタ
・コレクタ間電流を供給電流源とする出力電流制御機能
付きのCMOSバッファ回路を実現する事が出来るという効
果を有する。As described above, according to the present invention, the conventional CMOS process does not change the substrate structure, the substrate is used as the collector, the base is separated from the substrate potential, and the diffusion is further separated from the well potential. Providing a bipolar transistor having a layer as an emitter has the effect of realizing a CMOS buffer circuit having an output current control function using an emitter-collector current as a supply current source.
第１図は本発明の一実施例の断面図、第２図は従来のバ
ッファ回路を形成した半導体チップの断面図である。 １……Ｎ型半導体基板、2,3……Ｐウェル、4,5,6,7……
Ｎ型層、8,9,10,11……Ｐ型層、12,13……ゲート、14…
…VDD電源、15……演算増幅器、16……外部負荷、21…
…信号入力端子、22……出力端子、23……基準電源。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip on which a conventional buffer circuit is formed. 1 ... N-type semiconductor substrate, 2,3 ... P well, 4,5,6,7 ...
N-type layer, 8, 9, 10, 11 ... P-type layer, 12, 13, ... gate, 14 ...
... V DD power supply, 15 ... Operational amplifier, 16 ... External load, 21 ...
... Signal input terminal, 22 ... Output terminal, 23 ... Reference power supply.
Claims (1)
のウェルと、前記ウェルに形成されゲートが信号入力端
子に接続されドレインが出力端子に接続される一導電型
MOSトランジスタと、前記ウェル以外の前記半導体基板
領域に形成されゲートが前記信号入力端子に接続されド
レインが前記出力端子に接続される逆導電型MOSトラン
ジスタと、前記半導体基板に形成された逆導電型のベー
スと該ベース内に形成され前記逆導電型MOSトランジス
タのソースと接続される一導電型エミッタと前記半導体
基板とで構成されるバイポーラトランジスタとを含むバ
ッファ回路において、前記出力端子が外部の演算増幅器
の一方の入力端子に接続され、前記演算増幅器の他方の
入力端子に基準電圧が入力され、前記演算増幅器の出力
端子が前記ベースに接続されて前記バイポーラトランジ
スタに流れるコレクタ電流を制御することを特徴とする
バッファ回路。1. A well of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, and one conductivity type formed in the well and having a gate connected to a signal input terminal and a drain connected to an output terminal.
A MOS transistor, a reverse conductivity type MOS transistor formed in the semiconductor substrate region other than the well and having a gate connected to the signal input terminal and a drain connected to the output terminal; and a reverse conductivity type MOS transistor formed in the semiconductor substrate. And a bipolar transistor formed in the base and formed in the base and connected to the source of the reverse conductivity type MOS transistor and connected to the source of the reverse conductivity type MOS transistor, and the bipolar transistor including the semiconductor substrate. Connected to one input terminal of an amplifier, a reference voltage is input to the other input terminal of the operational amplifier, and an output terminal of the operational amplifier is connected to the base to control a collector current flowing through the bipolar transistor. Characteristic buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298546A JP2778062B2 (en) | 1988-11-25 | 1988-11-25 | Buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298546A JP2778062B2 (en) | 1988-11-25 | 1988-11-25 | Buffer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02143556A JPH02143556A (en) | 1990-06-01 |
| JP2778062B2 true JP2778062B2 (en) | 1998-07-23 |
Family
ID=17861130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63298546A Expired - Lifetime JP2778062B2 (en) | 1988-11-25 | 1988-11-25 | Buffer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2778062B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59178763A (en) * | 1983-03-29 | 1984-10-11 | Toshiba Corp | Semiconductor integrated circuit |
| JPS61173416A (en) * | 1985-01-28 | 1986-08-05 | 日立化成工業株式会社 | Insulating material for refrigerating machine motor |
-
1988
- 1988-11-25 JP JP63298546A patent/JP2778062B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02143556A (en) | 1990-06-01 |
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