JPS60225459A - Semiconductor ic - Google Patents
Semiconductor icInfo
- Publication number
- JPS60225459A JPS60225459A JP59081346A JP8134684A JPS60225459A JP S60225459 A JPS60225459 A JP S60225459A JP 59081346 A JP59081346 A JP 59081346A JP 8134684 A JP8134684 A JP 8134684A JP S60225459 A JPS60225459 A JP S60225459A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type region
- transistor
- terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、相補型ＭＯ８）ランジスタと、バイポーラト
ランジスタ及び拡散層によって形成された抵抗が混在す
る形の半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit in which complementary MO8 transistors, bipolar transistors, and resistors formed by diffusion layers coexist.
（従来技術）
近年、相補型ＭＯ８）ランジスタ（以下、０ＭＯ８とい
う。）ｔ−用い＆０ＭＯ８０ＭＯ８集積その低消費電力
並びに高速性、高集積性等の優れた性能を有することに
よって、増々広範囲に用いられつつある。但し、更に高
性能化するためには、０ＭＯ８集積回路の有する次の２
つの欠点を克復する必要があるとされている。１つはう
、チア゛、プ現象であシ、他の１つは、バイボー２集積
回路等に比較して外部負荷の駆動能力が低いということ
である。(Prior art) In recent years, complementary MO8) transistors (hereinafter referred to as 0MO8) are being used more and more widely due to their excellent performance such as low power consumption, high speed, and high integration. be. However, in order to further improve the performance, the following two features of the 0MO8 integrated circuit are required.
It is believed that it is necessary to overcome these shortcomings. One is the chirp phenomenon, and the other is that the external load driving ability is lower than that of a Bibo 2 integrated circuit or the like.
以下この２点について順次説明する。These two points will be sequentially explained below.
第１図、第２図、第３図を用いて０ＭＯ８出力回路のう
、チア、プ現象を説明する。第１図は通常の０ＭＯ８出
力回路の回路図を示す。第１図において端子１をソース
、端子２をゲート、端子３をドレインとしてＰチャンネ
ルトランジスタＱＰが、また端子４をソース、端子２ｔ
−ゲート、端子３をドレインとしてＮチャンネルトラン
ジスタ勃が構成されている。端子２及び端子３は各々入
力及び出力端子となり、端子１は最高電位電源（以下、
ＶＤＤという。）に、端子４は接地電源（以下ＧＮＤと
いう。）に接続される。The drop, drop, and drop phenomena of the 0MO8 output circuit will be explained using FIGS. 1, 2, and 3. FIG. 1 shows a circuit diagram of a conventional 0MO8 output circuit. In FIG. 1, a P-channel transistor QP is constructed with terminal 1 as the source, terminal 2 as the gate, and terminal 3 as the drain, and terminal 4 as the source and terminal 2t as the source.
- An N-channel transistor is constructed with the gate and terminal 3 as the drain. Terminal 2 and terminal 3 are input and output terminals, respectively, and terminal 1 is the highest potential power supply (hereinafter referred to as
It's called VDD. ), the terminal 4 is connected to a ground power source (hereinafter referred to as GND).
第２図は第１図に回路図で示したＣＭＯ８回路の断面図
である。Ｐ型基板５の一生面にＮ型領域６が形成され、
Ｎ型領域の中に高濃度のＰ型領域７゜８が各々Ｐチャン
ネルトランジスタＱｐのソース。FIG. 2 is a cross-sectional view of the CMO8 circuit shown in the circuit diagram in FIG. An N-type region 6 is formed on the whole surface of the P-type substrate 5,
A heavily doped P-type region 7.8 within the N-type region is a source of a P-channel transistor Qp.
ドレインとして形成されている。一方、Ｎチャンネルト
ランジスタ拳のソース、ドレイ／としてはＰ型基板５の
一生面にＮ型領域９．１０が作られている。各トランジ
スタＱＰ、ＱＮのソース。It is formed as a drain. On the other hand, N-type regions 9 and 10 are formed on the whole surface of the P-type substrate 5 as the source and drain of the N-channel transistor. Source of each transistor QP, QN.
ドレイン領域には、基板表面上に形成された絶縁膜１１
に設けられた開口部を介してＰチャンネルトランジスタ
ＱＰのソース電極１２．ドレイン電極１３．Ｎチャンネ
ルトランジスタＱＮのソース電極１４．ドレイン電極１
５が金属等の配線層で形成されている。An insulating film 11 formed on the substrate surface is provided in the drain region.
The source electrode 12. of the P-channel transistor QP is connected through the opening provided in the source electrode 12. of the P-channel transistor QP. Drain electrode 13. Source electrode 14 of N-channel transistor QN. drain electrode 1
5 is formed of a wiring layer of metal or the like.
Ｐｆｉ基板５は、高濃度Ｐ型領域１６と電極１７を介し
て端子４（ＧＮＤ）に、Ｎ型領域６は高不純物濃度Ｎ型
領域１８と電極１９ｔ−介して端子１（ＶＤＤ ）に接
続されている。ＰチャンネルトランジスタＱｐのゲート
電極２０としては配線層が、Ｎチャンネルトランジスタ
ＱＮのゲート電極２１としては配線層が基板表面上に形
成された絶縁膜１１上に各トランジスタＱＰＴ ＱＮの
ソース及びドレイン領域をまたがる形で形成されている
。各トランジスタＱｐとＱＮ間は漏れ電流が流れないよ
うに厚い絶縁層２２で隔てられている。The Pfi substrate 5 is connected to the terminal 4 (GND) through the high concentration P type region 16 and the electrode 17, and the N type region 6 is connected to the terminal 1 (VDD) through the high impurity concentration N type region 18 and the electrode 19t. ing. A wiring layer serves as the gate electrode 20 of the P-channel transistor Qp, and a wiring layer serves as the gate electrode 21 of the N-channel transistor QN on the insulating film 11 formed on the substrate surface, spanning the source and drain regions of each transistor QPTQN. formed in the shape. Each transistor Qp and QN are separated by a thick insulating layer 22 to prevent leakage current from flowing.
以上説明した第２図のＯＭＯＳ集積口゛路構造において
は、必然的に第３図で示すう、チアツブ回路が組み込ま
れることになる。すなわち第３図においてＰチャンネル
トランジスタＱｐのソース領域７をエミ、り、Ｎチャン
ネルトランジスタＱＮの基板としてのＮ型領域６をベー
ス、Ｐ型基板５をコレクタとしてＰＮＰ ）ランジスタ
Ｐ１が、ＮチャンネルトランジスタＱＮのソース領域９
ｔ−エミ、り、Ｐ型基板５をベース、Ｎ型領域６ｔ″コ
レクタとしてＮＰＮ ）ランジスタＮ１が等測的に形成
されている。In the OMOS integrated circuit structure of FIG. 2 described above, a chip subcircuit as shown in FIG. 3 is necessarily incorporated. That is, in FIG. 3, the source region 7 of the P-channel transistor Qp is used as the emitter, the N-type region 6 as the substrate of the N-channel transistor QN is used as the base, and the P-type substrate 5 is used as the collector. source area 9
An NPN (NPN) transistor N1 is isometrically formed using the T-emitter, P-type substrate 5 as a base and the N-type region 6t'' collector.
この回路において、ＰＮＰトランジスタＰ１のベース電
流としての電子がＮ型領域６に１またはＮＰＮトランジ
スタＮ１のベース電流としての正孔がＰ型基板５に、各
々あるしきい位置以上に注入された時に、それがトリガ
ーとなム トランジスタＰ１とＮｌが正帰還回路として
動作し、端子１（ＶＤＤ）と端子４（ＧＮＤ）間に大電
流が流れる。一旦このう、チア、プ回路が動作するメ。In this circuit, when electrons serving as the base current of the PNP transistor P1 are injected into the N-type region 6, or holes serving as the base current of the NPN transistor N1 are injected into the P-type substrate 5 above a certain threshold position, respectively, This is the trigger. Transistors P1 and Nl operate as a positive feedback circuit, and a large current flows between terminal 1 (VDD) and terminal 4 (GND). Once the chia/pu circuit is activated.
トリガーとなった現象が塩９除かれても電源間に電流が
流れ続け、ひいては集積回路が破壊される。Even if the triggering phenomenon is removed, current continues to flow between the power supplies, eventually destroying the integrated circuit.
以上が０ＭＯ８回路におけるう、チア、プ現象のメカニ
ズムであるが、対策としては、う、チアツブ回路が動作
するためのトリガー電流のしきい値を高くするか、また
はラッチアップ回路にトリガー電流が流入することを防
ぐことの２つの方法が考えられる。第１のトリガー電流
のしきい値を高くする方法についてはう、チアツブ回路
のＮＰＮ。The above is the mechanism of the chirp phenomenon in the 0MO8 circuit.As a countermeasure, either raise the threshold of the trigger current for the chirp circuit to operate, or cause the trigger current to flow into the latch-up circuit. There are two possible ways to prevent this from happening. Regarding the method of increasing the threshold of the first trigger current, please refer to the NPN of the Chiatubu circuit.
ＰＮＰＩ−ランジスタの電流増幅率を下げる等の各種の
努力がなされているが、０Ｍ０８）ランジスタの正常動
作における性能向上方策と相反する面等が６４１＋容易
ではない。一方、第２のう、チア、プ回路にトリガー電
流が流れることを防ぐことに関してＪ、）’Ｊガー電流
として最も重大なものが人。Although various efforts have been made to lower the current amplification factor of the PNPI transistor, it is not easy to do so because it conflicts with measures to improve performance in normal operation of the transistor. On the other hand, regarding preventing the trigger current from flowing into the second circuit, the most important current is the human.
出力端子における雑音電流であることを考え合わせると
、第１図で示し九〇ＭＯ８出力回路を用いる限９不可能
である。Considering that it is a noise current at the output terminal, this is not possible as long as the MO8 output circuit shown in FIG. 1 is used.
次に外部負荷駆動能力について述べる。０ＭＯ８回路の
負荷駆動能力がバイポーラ回路のそれに比較し小さいの
はバイポーラトランジスタとＭＯ８トランジスタの相互
コンダクタンスＣ’９ｍ）の差ニよる。現在市場に流布
しているＴＴＬ集積回路においては、５０ＰＦの負荷を
ｌ Ｑ ｎｓ以下の速さで駆動出来るが、０ＭＯ８集積
回路においては同様の負荷を駆動するのに２０ ｎｓ以
上を要する。Next, we will discuss the external load driving capacity. The reason why the load driving capability of the 0MO8 circuit is smaller than that of the bipolar circuit is due to the difference in mutual conductance C'9m) between the bipolar transistor and the MO8 transistor. TTL integrated circuits currently available on the market can drive a 50PF load at a speed of less than l Q ns, but a 0MO8 integrated circuit requires more than 20 ns to drive a similar load.
近年、この０ＭＯ８集積回路の外部負荷駆動能力を向上
させる手段として、０ＭＯ８集積回路の外部々の回路が
提唱されている。In recent years, circuits external to the 0MO8 integrated circuit have been proposed as means for improving the external load driving capability of the 0MO8 integrated circuit.
第４図は特願昭５８−１９８５８５号に提唱されている
、０Ｍ０８）ランジスタとバイポーラトランジスタの混
成形の出力バッ７アーの回路例である。FIG. 4 shows an example of a circuit of an output buffer which is a hybrid of an 0M08) transistor and a bipolar transistor, as proposed in Japanese Patent Application No. 198585/1985.
第４図において、２３は出カバ、７アの入力端子を示し
、集積回路の内部回路に接続される。２４は出力端子を
示し、集積回路の外部に接続される。In FIG. 4, 23 indicates an output cover and an input terminal of 7A, which is connected to the internal circuit of the integrated circuit. 24 indicates an output terminal, which is connected to the outside of the integrated circuit.
同回路を用いることによシ出力が低レベルから高レベル
に切シ換る時には、バイポーラトランジスタＱ３．Ｑｌ
が、出力が高レベルから低レベルに切シ変る時はバイポ
ーラトランジスタＱ４．Ｑ２が各々動作することによシ
高い負荷駆動能力を得ることが可能となる。第４図は出
カバ、ファー回路にバイポーラトランジスタを導入した
例であるが、出カバ、ファー回路に限らず、内部回路、
入カバ、ファー回路等にも０Ｍ０Ｓトランジスタとバイ
ポーラトランジスタを混在させ、集積回路の性能を更に
上げることはもちろん可能である。By using the same circuit, when the output is switched from a low level to a high level, the bipolar transistor Q3. Ql
However, when the output changes from high level to low level, bipolar transistor Q4. By operating each Q2, it is possible to obtain a high load driving capability. Figure 4 shows an example in which bipolar transistors are introduced in the output cover and far circuits, but they are not limited to the output cover and far circuits;
It is of course possible to further improve the performance of the integrated circuit by mixing 0M0S transistors and bipolar transistors in the input cover, far circuit, etc.
（発明の目的）
本発明の目的は上述したような０ＭＯ８，バイポーラ混
在型の半導体集積回路（以下、 Ｂｉ−ＣＭＯ８工０と
いう。）において、前述したう、チア、プを防止した半
導体集積回路を提供することにある。(Object of the Invention) The object of the present invention is to provide a semiconductor integrated circuit which prevents the above-mentioned chip and drop in the above-mentioned OMO8 and bipolar mixed type semiconductor integrated circuit (hereinafter referred to as Bi-CMO8-0). It is about providing.
（発明の構成）
本発明の半導体集積回路は、−導電型の半導体基板の一
生面に形成された０Ｍ０８） ５ンジスタ領域を有する
半導体集積回路において、外部端子に接続された反対導
電型領域（あるいは該反対導電型領域内に形成された一
導電型領域）からなる前記半導体基板の一生面に形成さ
れた第１の領域と、該第１の領域と前記０Ｍ０８）ラン
クる夕領域間に電源端子に接続された反対導電型領域（
あるいは高不純物濃度の一導電型領域）からなる前記半
導体基板の一生面に形成された第２の領域とを含むこと
から構成される。(Structure of the Invention) The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a 0M08) 5 transistor region formed on the whole surface of a -conductivity type semiconductor substrate, and an opposite conductivity type region (or a first region formed on the entire surface of the semiconductor substrate consisting of one conductivity type region formed in the opposite conductivity type region; and a power terminal between the first region and the 0M08) rank region. A region of opposite conductivity type connected to (
or a second region formed on the entire surface of the semiconductor substrate, which is formed of one conductivity type region with high impurity concentration.
（実施例）
以下、本発明の実施例について図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第５図は本発明の第１の実施例の要部を示す模式的断面
図で、第４図で示した出カバ、７７回路に本発明を適用
した場合を示す〇
第５図において、Ｎ型領域２５．Ｐｉｔ領域２６゜Ｎ型
領域２７が各々コレクタ、ペース、エミ、りとして、第
４図に示したトランジスタＱ２を構成している。Ｎ型領
域２５は配線層による電極２８を介して出力端子２４に
接続されている。Ｐ凰基板５．Ｎ型領域６．高濃度Ｐ型
領域７，８．高濃度Ｎ派領域９，１０で０Ｍ０８）９ン
ジスタが第２図と同様に構成されている。領域２９はＮ
型で配線層による電極３０ｆ：介して電源端子ＶＤＤに
接続されている。第５図において、ＮＪ領域２５が、上
記発明の詳細な説明で示した半導体基板の一生面に形成
された第１の領域、Ｎ型領域２９が、半導体基板の一生
面に形成された第２の領域に相当する。FIG. 5 is a schematic cross-sectional view showing the main parts of the first embodiment of the present invention, showing the case where the present invention is applied to the output cover and 77 circuit shown in FIG. Mold area 25. The pit region 26 and the N-type region 27 constitute the transistor Q2 shown in FIG. 4 as a collector, a paste, an emitter, and a resistor, respectively. The N-type region 25 is connected to the output terminal 24 via an electrode 28 formed of a wiring layer. P-o board 5. N-type region6. High concentration P type regions 7, 8. In the high concentration N group regions 9 and 10, 0M08)9 transistors are constructed in the same manner as shown in FIG. Area 29 is N
It is connected to the power supply terminal VDD through an electrode 30f formed by a wiring layer. In FIG. 5, an NJ region 25 is a first region formed on the whole surface of the semiconductor substrate shown in the detailed description of the invention, and an N-type region 29 is a second region formed on the whole surface of the semiconductor substrate. corresponds to the area of
第５図に示した構造において、出力端子２４にＧＮＤレ
ベルよシも十分に低い雑音信号が加わった場合を考えて
見る。もし、Ｎ型領域２９がない場合には、Ｎ型領域２
５をエミ、り、Ｐ型基板５をペース、Ｐチャンネルトラ
ンジスタＱｐのＮ型領域６會コレクタとして、ＮＰＮ）
ランジスタが動作し、第３図の２．チア、プ等価回路で
示した等価ＰＮＰ）ランジスタＰ１のペース領域６にト
リガーとしての電子の注入が起シ、う、チア、プを誘起
する。ところが第５図で示すようにＮ型領域２５と０Ｍ
Ｏ８トランジスタの中間にＮ型領域２９が置かれると、
雑音電流の大部分はＮ型領域２９をコレクタとして流れ
、０Ｍ０８）ランジスタ部分にう、チア、プのトリガー
電流として影響を及ぼさなくなる。In the structure shown in FIG. 5, consider the case where a noise signal that is sufficiently lower than the GND level is applied to the output terminal 24. If there is no N type region 29, the N type region 2
5 as an emitter, a P-type substrate 5 as a base, and an N-type region 6 of a P-channel transistor Qp as a collector, NPN)
The transistor operates, and 2. of FIG. (Equivalent PNP shown in the equivalent circuit) Injection of electrons as a trigger into the pace region 6 of the transistor P1 induces the trigger. However, as shown in FIG.
When an N-type region 29 is placed in the middle of the O8 transistor,
Most of the noise current flows through the N-type region 29 as a collector, and does not affect the transistor portion as a trigger current for the transistors 0M08).
第６図は本発明の第２の実施例の要部を示す模式的断面
図で、入力または出力端子がＰ型領域に接続している場
合に本発明を応用した場合を示す。FIG. 6 is a schematic sectional view showing a main part of a second embodiment of the present invention, and shows a case where the present invention is applied to a case where an input or output terminal is connected to a P-type region.
第６図において、ＣＭＯＳトランジスタ部分の構成は第
２図、第５図で示したものと同様である。In FIG. 6, the configuration of the CMOS transistor portion is the same as that shown in FIGS. 2 and 5.
Ｎ型領域３１内に形成された第１の領域としてのＰ属領
域３２は、配線層による電極３３を介して入力または出
力用の外部端子３４に接続している。A P region 32 as a first region formed within the N type region 31 is connected to an external terminal 34 for input or output via an electrode 33 formed of a wiring layer.
Ｐ属領域３２としては、ＮＰＮ）ランジスタのペースを
想定しても良いし、抵抗を想定しても良い。As the P region 32, a pace of an NPN transistor may be assumed, or a resistance may be assumed.
０Ｍ０８）ランジスタ領域とＰ属領域３２の中間には、
第２の領域としての高不純物濃度Ｐ層領域３５が置かれ
、このＰ型領域３５０表面に形成された配線層による電
極３６はＧＮＤ電位に接続されている。0M08) Between the transistor area and the P genus area 32,
A high impurity concentration P layer region 35 as a second region is placed, and an electrode 36 formed by a wiring layer formed on the surface of this P type region 350 is connected to the GND potential.
第６図に示した構造において、外部端子３４に、十分高
い電位レベルの雑音信号が加わった場合を考えて見る。In the structure shown in FIG. 6, consider a case where a noise signal of a sufficiently high potential level is applied to the external terminal 34.
もし、ＧＮＤ電位に接続されているＰｆｌｌ領域３５が
ない場合には、Ｐ減債域３２ｔ−エミ、り、Ｎ型領域３
１をベース、Ｐ型基板５を＝レクタとして動作するＰＮ
Ｐ ）ランジスタにおいて、その電流は０Ｍ０８）ラン
ジスタ領域にまで到達する。この電流は第３図のう、チ
ア、プ等価回路で示した等価ＮＰＮ）ランジスタＮｌの
ベース領域へのトリガー電流とな９、う、チア、グを誘
起する。ところが、第６図に示すように外部端子が接続
しているＦｉｌ領域３２とＣＭＯＳトランジスタ領域と
の間に置かれたＰ属領域３５をＧＮＤ電位に接続するこ
とによシ、雑音電流はＰｆｉ領域３５゜電極３６ｔ−介
して吸収され、０Ｍ０８）ランジスタ部分にう、チア、
プのトリガー電流として働らかなくなる。If there is no Pfll region 35 connected to the GND potential, the
1 as a base and P-type substrate 5 as a rector.
In the P) transistor, the current reaches the 0M08) transistor region. This current induces a trigger current to the base region of the equivalent NPN transistor Nl shown in the equivalent circuit of FIG. However, as shown in FIG. 6, by connecting the P region 35 placed between the Fil region 32 to which the external terminal is connected and the CMOS transistor region to the GND potential, the noise current can be reduced to the Pfi region. Absorbed through the 35° electrode 36t, 0M08)
It no longer works as a trigger current for the pump.
（発明の効果）
以上、詳細説明したとおシ、本発明によれば、上記の構
成によシ、入出力端子等の外部端子に加わった雑音電流
の大部分１ｋＯＭＯ８回路部に到達させることなく吸収
することが可能となシ、通常の０ＭＯ８入出力回路よシ
もう、チア、プが起シにくい入出力回路を有する０Ｍ０
８）ランジスタ、バイポーラトランジスタ混在の半導体
集積回路が得られる。(Effects of the Invention) As described in detail above, according to the present invention, the above structure absorbs most of the noise current applied to external terminals such as input/output terminals without allowing it to reach the 1kOMO8 circuit section. The 0M0 has an input/output circuit that is less likely to cause problems than the normal 0MO8 input/output circuit.
8) A semiconductor integrated circuit including transistors and bipolar transistors can be obtained.
第１図及び第２図はそれぞれ従来の０ＭＯ８出力回路の
一例の回路図及びその模式的断面図、第３図は従来の０
ＭＯ８回路におけるう、チア、プ現象を示す等価回路図
、第４図はバイボーットランジスタと０Ｍ０８）ランジ
スタによって構成され九出力回路の一例の回路図、第５
図及び第６図はそれぞれ本発明の第１．第２の実施例の
要部を示す模式的断面図である。
１．２，３．４・・・・・・端子、５・・・・・・Ｐ減
基板、６・・・・・・Ｎｌｌ領域、７，８・・・・・・
Ｐ属領域、９．１０・・・・・・Ｎ型領域、１１・・・
・・・絶縁膜、１２・・・・・・ソース電極、１３・・
・・・・ドレイン電極、１４・・・・・・ソース電極、
１５・・・・・・ドレイン電極、１６・・・・・・Ｐａ
ｌ領域、１７・・・・・・電極、１８・・・・・・高不
純物濃度Ｎ型領域、１９・・・・・・電極、２０．２１
・・・・・・ゲート電極、２２・・・・・・絶縁層、２
３・・・・・・入力端子、２４・・・・・・出力端子、
２５・・・・・・Ｎ型領域、２６・・・・・・Ｐ属領域
、２７・・・・・・Ｎｌｌ領域、２８・・・・・・電極
、２９・・・・・・Ｎ型領域、３０・・・・・・電極、
３１・・・・・・Ｎｍ領域、３２・・・・・・Ｐａｌ領
域、３３・・・・・・電極、３４・・・・・・外部端子
、３５・・・・・・高不純物濃度Ｐ属領域、３６・・・
・・・電極。1 and 2 are a circuit diagram and a schematic cross-sectional view of an example of a conventional 0MO8 output circuit, respectively, and FIG. 3 is a circuit diagram of an example of a conventional 0MO8 output circuit, and FIG.
Fig. 4 is an equivalent circuit diagram illustrating the chia-pu phenomenon in the MO8 circuit.
FIG. 1 and FIG. FIG. 7 is a schematic cross-sectional view showing main parts of a second embodiment. 1.2, 3.4...terminal, 5...P reduced substrate, 6...Nll region, 7,8...
P-genus region, 9.10...N-type region, 11...
... Insulating film, 12 ... Source electrode, 13 ...
...Drain electrode, 14...Source electrode,
15...Drain electrode, 16...Pa
l region, 17...electrode, 18...high impurity concentration N-type region, 19...electrode, 20.21
......Gate electrode, 22...Insulating layer, 2
3...Input terminal, 24...Output terminal,
25...N type region, 26...P region, 27...Nll region, 28...electrode, 29...N type Area, 30... Electrode,
31...Nm region, 32...Pal region, 33...electrode, 34...external terminal, 35...high impurity concentration P Genus area, 36...
···electrode.
Claims (1)
ランジスタ領域を有する半導体集積回路においてさ部端
子に接続された反対導電盤領域（あるいは該反対導電型
領域内に形成された一導電型領域）からなる前記半導体
基板の一生面に形成された第１の領域と、該第１の領域
と前記０Ｍ０Ｓトランジスタ領域間に電源端子に接続さ
れた反対導電型領（あるいは高不純物濃度の一導電型領
域）からなる前記半導体基板の〒主面に形成された第２
の領域とを含むことを特徴とする半導体集積回路０0M08) formed on the entire surface of a semiconductor substrate of one conductivity type.
In a semiconductor integrated circuit having a transistor region, a first semiconductor substrate formed on the entire surface of the semiconductor substrate is formed of an opposite conductivity region (or a region of one conductivity type formed within the region of the opposite conductivity type) connected to the rib terminal. and a region of an opposite conductivity type (or a region of one conductivity type with high impurity concentration) connected to a power supply terminal between the first region and the 0M0S transistor region. Second
A semiconductor integrated circuit 0 characterized in that it includes a region of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081346A JPS60225459A (en) | 1984-04-23 | 1984-04-23 | Semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081346A JPS60225459A (en) | 1984-04-23 | 1984-04-23 | Semiconductor ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60225459A true JPS60225459A (en) | 1985-11-09 |
Family
ID=13743802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59081346A Pending JPS60225459A (en) | 1984-04-23 | 1984-04-23 | Semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60225459A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7773442B2 (en) * | 2004-06-25 | 2010-08-10 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
| US9842629B2 (en) | 2004-06-25 | 2017-12-12 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56162860A (en) * | 1980-05-19 | 1981-12-15 | Toshiba Corp | Semiconductor device |
| JPS5848960A (en) * | 1982-09-03 | 1983-03-23 | Hitachi Ltd | Semiconductor device |
-
1984
- 1984-04-23 JP JP59081346A patent/JPS60225459A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56162860A (en) * | 1980-05-19 | 1981-12-15 | Toshiba Corp | Semiconductor device |
| JPS5848960A (en) * | 1982-09-03 | 1983-03-23 | Hitachi Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7773442B2 (en) * | 2004-06-25 | 2010-08-10 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
| US8493804B2 (en) | 2004-06-25 | 2013-07-23 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
| US8837245B2 (en) | 2004-06-25 | 2014-09-16 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
| US9842629B2 (en) | 2004-06-25 | 2017-12-12 | Cypress Semiconductor Corporation | Memory cell array latchup prevention |
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