JP3034531B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] The present invention relates to a CMOS type semiconductor integrated circuit, and more particularly to a structure of a transmission gate transistor thereof.
Providing a frame-shaped first substrate contact region around a transistor of a transmission of a semiconductor integrated circuit, and a second substrate contact region crossing the frame, dividing the transistor, Is surrounded by a plurality of contacts included in the first and second substrate contact regions.

[Industrial applications]

The present invention relates to a CMOS type semiconductor integrated circuit, and particularly to a structure of a transistor of a transmission gate thereof.

Since a CMOS type semiconductor integrated circuit has a PNPN parasitic thyristor in its structure, destruction of elements due to latch-up becomes a problem. Therefore, a semiconductor integrated circuit having a high latch-up strength is required.

[Conventional technology]

FIG. 5 shows the structure of a conventional transmission gate. In the circuit diagram of FIG. (C) is a transmission gate, Q _A P-channel MOS transistor, Q _B is N-channel M
OS transistor. The sources and drains of these transistors are connected in parallel, and the complementary signals Gc,
Add ▲ ▼. Signal Gc is at H (high) level, ▲
When ▼ is at the L (low) level, the transistors Q _A and Q _B are off, when the signal Gc is at the L level, and when ▲ is at the H level.
Q _A and Q _B are turned on, and thus terminals A and B are turned on / off.

The transmission gate is configured in a CMOS integrated circuit, for example, P-channel transistor Q _A is FIG. 5 (b)
(Qa to Qd) are connected in parallel as follows (If the width of the transistor becomes large, it will be too elongated before that, so it is divided and juxtaposed, and it is said that it is close to a square Therefore, the configuration on the semiconductor substrate is as shown in FIG. 5 (a). FIG. 5A is a cross-sectional view of a transmission gate P-channel transistor and another N-channel transistor. An N-type well N-well is formed on a P-type substrate Psub, and a P ⁺ region forming the source / drain of the transistors Qa to Qd is formed in the N-type well Nwell, and connected together with a gate electrode therebetween as shown in the figure. A substrate contact region N ⁺ is also formed in the N-type well, and the power supply voltage V
cc is added so that the N-type well is at the power supply potential. N
Channel transistor Q is formed on substrate Psub. N ⁺
Are the source / drain regions, P ⁺ is a substrate contact region, and applies a low-potential-side power supply Vss to the substrate Psub.

In a CMOS IC having such a structure, a PNPN structure, that is, a thyristor occurs parasitically. Q _1, Q ₂ of FIG. 5 (a), ...... is a P-channel or N-channel transistor constituting the thyristor. P-channel transistor Q ₁ is a P ⁺ region which is the source and the drain of the transistor Qa, and an N-type well, is formed of a P-type substrate, N-channel transistor Q ₂ is, N ⁺ regions are the source and drain of the transistor Q , A P-type substrate and an N-type well, and the P-channel transistors Q ₃ , Q _{4, and the} like also conform to this. Resistance R ₁ , R ₂ ,…
… Is the resistance of the N-well between the substrate contact N ⁺ (C ₁ ) and the base of Q ₁ , the P between the substrate contact P ⁺ and the base of Q ₂
The resistance of the sub, ....

When these transistors Q _{1 to} Q ₃ and resistors R _{1 to} R ₇ are drawn in a circuit diagram, they are as shown in FIG. This is nothing but an equivalent circuit of a thyristor.

When a negative noise is applied to the point in FIG. 6, that is, N ⁺ -X in FIG. 5A, a current flows through the path of R ₂ -Q _2- , and the transistor Q ₂ is turned on. Then V cc-R ₁ -R ₃ -Q current flows through a ₂ -V ss pathway, transistors Q _1, Q ₃ base current down.
If this exceeds the base-emitter voltage, the transistor
Q ₁ and Q ₃ are turned on, and V cc −Q ₁ −R ₄ −R ₂ , V cc −Q ₃ −R ₆ −R ₄ −
Current flows through a path of the R _2. This also becomes the base current of the transistor Q _2, so that transistor Q ₁ to Q ₃ also gone negative noise of points continues to turn on, current continues to flow from V cc to V ss. This is the latch-up phenomenon of a CMOS IC. Be focused on Q _B of FIG. 5 (c) said the same thing.

In a CMOS IC, it is inevitable that a parasitic PNPN element is generated, and the circuit configuration shown in FIG. 6 is inevitably made. However the resistance R ₁ is small, even if the collector current flows through the transistor Q ₂ in the negative noise, transistor Q ₁ if the voltage drop R ₁ is V _BE below due to it is not turned on. The transistors Q _3, since the voltage drop R ₃ only lower by dividing by R _5, R _7, easily turned from Q _1.

Substrate contact the person who made is brought closer to the source and the drain of the transistor is small and the resistance of the corresponding R _1, difficult to latch-up. At the transmission gate, if a plurality of transmission gates are arranged side by side, the substrate contact C ₁ (R ₁
N ⁺ ), the bulk resistance (such as R ₅ ) increases, making it easier to latch up.

[Problems to be solved by the invention]

In CMOS IC Thus transmission gate included in the circuit, as the width of the transistor in the transmission gate becomes large, such as the resistance of R ₅ structural Q ₃ becomes large, the voltage drop increases, latch-up Is easy to cause.

An object of the present invention is to improve such a point and make it difficult for latch-up to occur.

[Means for solving the problem]

In order to solve the above-mentioned problems, the present invention provides a frame-shaped first substrate contact region around a transistor of a transmission gate of a CMOS type semiconductor integrated circuit and a second substrate contact region crossing the region. And the transistor is divided, and the divided transistor is surrounded by a plurality of contacts included in the first and second substrate contact regions.

As shown in FIG. 1, in the present invention, a P-channel transistor constituting a transmission gate is surrounded by a frame-shaped substrate contact region (C ₃ ), and Qa, Qb, and Qc are further surrounded by another substrate contact region (C ₂ ). Divide into Qd for 2 minutes. Or,
A substrate contact region N (C ₂ ,...) Is provided between the parallel P-channel transistors Qa and Qb and between Qc and Qd.

By doing so, the parasitic P and N channel transistors Q _{1 to} Q
The equivalent circuit of FIG. ₃ is as shown in FIG. _{2 and} does not change for the transistors Q ₁ and Q ₂ , but for the transistor Q ₃ , its base resistance R ₅ becomes a resistance between Vcc and the base of Q _3. .
The same applies to the N-channel transistor with the P and N characteristics reversed.

(Operation)

In FIG. 2 as well, when negative noise enters the point, R ₂ −Q ₂ −
Path transistor Q ₂ is turned on and current flows in the, V
cc-R ₁ -R ₃ -Q current flows through a path of ₂ -V ss. Thus the voltage drop R ₁ is generated downlink base potential of the transistor Q _1, Q ₁ is turned on and becomes equal to or less than the V _BE. But the transistor Q ₃ are not affected by the voltage drop R _1. Since one end of the resistor R ₅ is connected to the power supply V cc, V cc-R ₅ if Q ₂ is turned on -
A current flows through the path of R ₇ −Q ₂ −V ss and a voltage drop occurs in R _5. However, when the substrate contact N ⁺ (R ₅ ) is close to the transistor Qb, the resistance R ₅ is small, and the voltage drop due to this is small. Te may be hard to turn on the transistor Q _3. The same is true with transistor Q _1, thus in the negative noise
Q ₂ is not turned on Q _1, Q ₃ also turned on, thus it is possible to hardly cause latchup.

For N-channel transmission gates,
The same can be considered by reversing the P and N characteristics.

〔Example〕

FIG. 3 shows an embodiment of the present invention. S / D is transistor Q
Source / drain regions a, Qb,..., G is a gate electrode, and a small black square is a contact window. C ₁ -C ₃ in the substrate contact region, a rectangular frame formed by C _1, comprising a which was vertical in two places within the framework of C _2, C ₃ portions of thirds. Figure 4 is due to the conventional method, the substrate contact region is only rectangular frame by C _1.

Thus a large number of transistors are formed for a rectangular frame near the transistor has a small resistance of the corresponding R ₅ stick to the base, the base of the potential drop is small when the current due to the negative noise flows, turned Although it is difficult, the resistance increases as the distance from the square frame increases, and the potential drop of the base is large, so that the base is easily turned on. If the substrate contact region is also provided in a rectangular frame as shown in FIG. 3 and these C ₂ and C ₃ are pulled up to Vcc, it is possible to suppress the decrease in the base potential and to reach latch-up.

〔The invention's effect〕

As described above, according to the present invention, a CMOS IC having a transmission gate formed by a relatively simple means of dividing a transistor by a substrate contact region or providing a substrate contact region among a plurality of transistors is provided. , Latch-up hardly occurs, and the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is an equivalent circuit diagram of the parasitic PNPN element of FIG. 1, FIG. 3 is a plan view of a main part showing an embodiment of the present invention, and FIG. FIG. 5 is an explanatory view of a conventional example, and FIG. 6 is an equivalent circuit diagram of the parasitic PNPN element of FIG. Qa~Qd in Figure 1 is P-channel transistor, C ₁ -C ₃ is a substrate contact region.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-12533 (JP, A) JP-A-63-23363 (JP, A) JP-A-62-71248 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 27/088 H01L 27/08 331

Claims (1)

(57) [Claims] A frame-shaped first substrate contact region is provided around a transmission gate transistor of a CMOS type semiconductor integrated circuit, and a second substrate contact region crossing the frame is provided. A semiconductor integrated circuit, wherein a plurality of contacts included in the second substrate contact region surround a periphery of the transistor divided by the second substrate contact region.