JPS61208863A - Cmos semiconductor device - Google Patents

Abstract

PURPOSE:To improve the resistance to latch-up by providing a guard ring which is formed in a reverse conductivity type at least either on the semiconductor device side near the boundary between a semiconductor device and a first region, or on the first region side, and on which a prescribed bias is impressed through a resistor. CONSTITUTION:The base of an N-P-N transistor 45 is connected to the base of an N-P-N transistor 31 through the intermediary of the base series resistance 43 of the N-P-N transistor 45, and the base of the N-P-N transistor 31 is connected to a Vss terminal 49 through the intermediary of a parasitic substrate resistance 35, while the emitter of the N-P-N transistor 31 is connected directly to the Vss terminal 49. When a current flows out from a terminal A due to noise or the like from the outside, in a circuit construction as described above, the collector current of the N-P-N transistor 45 turns to be the base current of an N-P-N transistor 71, and it can not drive a P-N-P transistor 29 whose emitter series resistance is small enough to supply a current necessary for causing latch-up, the thus the resistance to latch-up can be enhanced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a CMO with improved resistance to so-called latch-up.
S related to semiconductor devices.

[Technical background of the invention and its problems] With the recent development of semiconductor technology, as the degree of integration of integrated circuits increases, the power consumption within the chip tends to increase. For this reason, CMOS with the lowest power consumption has recently become available.
Integrated circuits are constructed using circuits to reduce power consumption. However, in a normal CMOS circuit that does not have an SO structure, a PNPN junction exists structurally, forming a parasitic thyristor, and when an overcurrent is applied to the input terminal due to power supply noise, etc. There was an opening angle in which the parasitic thyristor turned on and overcurrent continued to flow, causing so-called latch-up and causing device destruction. In order to prevent this latch-up, a CMOS semiconductor device has been proposed in which, for example, a substrate contact called a guard ring or a well conductor is formed around a MoS transistor constituting a CMOS circuit.

FIG. 9 is a pattern plan view showing a conventional example of a CMOS inverter circuit in which a guard ring is formed. In the figure, 101 is a P-type silicon substrate (hereinafter referred to as "substrate"), and a P-channel MO8 type transistor (hereinafter referred to as "PMOS transistor") is disposed on this substrate 101.

) 103 and an N-channel MO8 type transistor (hereinafter referred to as rNMOS transistor) 105 are formed, and these two transistors constitute a CMOS inverter circuit.

An N-type well (hereinafter referred to as "n-well") 107 is formed in the substrate 101, and a pair of P-type regions 109.11 are formed within the O-well 107 at a predetermined distance apart.
1 is formed to constitute the source and drain of the PMOS transistor 103 (hereinafter referred to as rPMOS 109).
Source area 1iiJ.

111 is called rPMOS drain region J. 〉.

The PMOS source region 109 is connected to V by the aluminum wiring 113.
connected to the DD terminal 145 and connected to the PMOS drain region 11
1 is connected to the output terminal 151 by an aluminum wiring 113. Then, the PMOS source region 109 and the PMOS
A gate electrode 115 common to an NMOS transistor 105 (described later) is formed of polysilicon on the surface of the substrate 101 between the drain region 111 and the gate electrode 1
115 is connected to an input terminal 149 by an aluminum wiring 113. Note that a well contact 117 is provided in the n-well 107, and the well contact 117 and the VDD terminal 145 are connected by an aluminum wiring 113.

Further, a pair of N-type regions 119 and 121 are formed on the substrate 101 at a predetermined distance apart.
1 constitutes the drain and source of the NMOS transistor 105 (hereinafter, 119 is referred to as the rNMOS drain region J, and 121 is referred to as the rNMoS source region), and NM
The OS drain region 119 is connected to the output terminal 151 by an aluminum wiring 113, and the NMOS source region 121 is connected to the Vssl terminal 147 by an aluminum wiring 113. Then, the NMOS drain region 119 and the NMOS
A gate electrode 115 is formed of polysilicon on the surface of the substrate 101 between the source region 121 and the gate electrode 115 is connected to an input terminal 149 by an aluminum wiring 113. Note that a substrate contact 123 is formed on the substrate 101, and this substrate contact 123 and Vss
A terminal 147 is connected to the aluminum wiring 113.

Further, on the substrate 101 side at the boundary between the region where the PMOS transistor 103 is formed and the region where the NMOS transistor 105 is formed, a guard ring 127 is formed by a diffusion layer of the same conductivity type as the substrate 101, that is, P type. This guard link 127 is connected to the aluminum wiring 11.
3 to the VSS terminal 147.

FIG. 10 is a schematic cross-sectional view of FIG. 9, and shows an approximate equivalent circuit of a parasitic thyristor constituted by a parasitic transistor and a parasitic resistance existing in the 0MO8 structure. In the same figure, 129 is a vertical parasitic pnρ bipolar transistor (hereinafter referred to as an rpnp transistor), and this pnp transistor 129 is a P-type PM bipolar transistor.
The P-type substrate 10 has the OS source region 109 as an emitter and the n-well 107 formed in the substrate 101 as a base.
1 as a collector. Further, 131 is a lateral parasitic npn bipolar transistor (hereinafter referred to as "npn transistor"), and this npn transistor 13
1 has an N-type NMOS source region as an emitter, a P-type substrate 101 as a base, and an nMOS transistor formed on the substrate 101.
The well 107 is formed as a collector. The emitter of the pnp transistor 129 is connected to the VDD terminal 145, and the base of the pnp transistor 129 is connected to the VDD terminal 145 via the parasitic well resistance 133, and the parasitic collector resistance 141 of the npn transistor 131. npn transistor 1
31 collectors. Further, the collector of the pnp transistor 129 is connected to the base of the npn transistor 131 via the collector parasitic resistance 143 of the pnp transistor 129, and the base of the npn transistor 131 is connected to the parasitic substrate resistance 135 connected in parallel to the parasitic guard ring. Vss via resistor 139
It is connected to the terminal 147 and the npn transistor 13
The emitter of 1 is directly connected to the VSS terminal 147.

FIG. 11 is a diagram showing only an approximate circuit of the parasitic thyristor shown in FIG. 10. In such a circuit configuration, the latch-up phenomenon occurs when the terminal A
This occurs because a current 1trg flows from the transistor 1trg to turn on the pnp transistor 129, a collector current flows, and the npn transistor 131 turns on, turning on the parasitic thyristor. In this circuit, if the resistance value of the parasitic substrate resistance 135 is Rp and the resistance value of the parasitic guard ring resistance 139 is rg, the guard ring resistance 139 is connected in parallel to the parasitic substrate resistance 135, and no guard ring is provided. Compared to the case, the parasitic substrate resistance 135 is substantially reduced from Rp to Rp-ra/(Rp+rg). Therefore, for example, a current I trg flows from the terminal A due to power supply noise, etc., and the pnp transistor 129
The collector current of the pnph run raster 129 required to turn on and cause a latch-up due to collector current flowing is approximately (Rp + rg) / r (J times as much as when no guard ring is provided. will increase.

That is, the following difference occurs between the current Jtrg when the guard ring is provided and the current 1trg when the guard ring is not provided. Letting Ith be the value of the current Itrg that causes latch-up when no guard ring is provided,
Ith is expressed by the following formula.

Ith=VF /RN +VF /Rp"RpHere,
VF is the forward voltage between the base and emitter of the pnp transistor 129, RN is the resistance value of the strange well resistor 133, and Rp is the common emitter current amplification factor of the pnp transistor 129. Furthermore, if the value of the current 1 trg that causes latch-up when a card ring is provided is I thQ, the substrate resistance decreases from Rp to R1)-rM (Rp+rg) as described above.
tha is expressed by the following formula.

hty = (+/&t I#doPt”Xi
)/! 'p・)j・/1As a result, from the above formula,
When a guard ring is provided, the current I tho required to cause latch-up increases by VF/rg·Rp compared to the case where no guard ring is provided.

Therefore, as described above, this substrate 10
By providing a guard ring region of the same conductivity type as 1, the current required to cause latch-up 1 thc)
It increases and causes latch-up. However, as the degree of integration of CMO3 semiconductor devices increases and the region where the P-channel MOS transistor is formed approaches the region where the N-channel MOS transistor is formed, the current amplification factor of the parasitic bipolar transistor increases.

Therefore, the increase in current 1th that causes latch-up VF/r(1·Rp becomes smaller, and the problem is that the effect of preventing latch-up by providing a guard ring is reduced. Note that n The same thing as described above can be said when a guard ring is provided in the area of the well 107.

UObject of the invention This invention was made in view of the above, and its object is to relate to a CMO3 semiconductor device that improves latch-up resistance by using a guard ring.

[Summary of the Invention] In order to achieve the above object, a second conductivity type M O,S transistor is formed in a first conductivity type semiconductor substrate, and a second conductivity type M O,S transistor formed in a part of the semiconductor substrate is formed. The present invention provides a semiconductor device in which a CMOS circuit is formed on a semiconductor substrate by forming a first conductivity type MOS t-transistor in a first conductivity type region.
The gist is to have a guard ring formed of an opposite conductivity type on at least one of the semiconductor substrate side or the first region side near the boundary with the region, and to which a predetermined bias is applied via a resistor.

[Effects of the Invention] According to the present invention, a MOS transistor of the second conductivity type is formed on the semiconductor substrate side of the first conductivity type, and the first region of the second conductivity type formed in a part of the semiconductor substrate In a semiconductor device in which a CMOS circuit is configured on a semiconductor substrate by forming a MOS transistor of the first conductivity type on the semiconductor substrate side or the first region side near the boundary between the semiconductor substrate and the first region, A guard ring of the opposite conductivity type is formed on at least one of them, and a predetermined bias is applied to this guard ring via a resistor, so 0M
It is possible to prevent the parasitic thyristor present in the O8 structure from turning on, thereby improving latch-up resistance. Furthermore, since the guard ring is connected via a resistor to a contact formed in the region where the guard ring is formed and connected to a predetermined bias, latch-up resistance can be further improved. . Furthermore, since the surface impurity concentration between the contact and the surface of the region where the contact is formed is set lower than that of the surrounding area, latch-up resistance can be further improved.

[Embodiments of the invention” Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a pattern plan view showing the structure of a CMOS semiconductor device according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a P-type silicon substrate (hereinafter referred to as the "substrate"), and an N-channel MO8 type transistor (referred to as g, lower fNMOs transistor) 5 is formed on this substrate 1. A P-channel MO8 type transistor (hereinafter referred to as "PMOS transistor") 3 is formed in the n-well formed in the transistor 3, and a CMOS inverter circuit is formed by these two transistors.

The substrate 1 has an N-type well (hereinafter referred to as "n-well").
) 7 is formed, and a pair of P-type regions 9°11 are formed in this n-well 7 at a predetermined distance apart.
It constitutes the source and drain of the MOS transistor 3 (hereinafter 9 is the "PMOS source region", 11 is the rPM
It is called the "OS drain region". ), PMOS source region 9
Aluminum arrangement! 13 to a VDD terminal 47, and the PMOS drain region 11 is connected to an output terminal 51 by an aluminum wiring 13. A gate electrode 15 of the PMOS transistor 3, which is common to the NMOS transistor 5, is formed of polysilicon on the surface of the substrate 1 between the PMOS source region 9 and the PMOS drain region 11, and this gate electrode 15 is connected to an input via an aluminum wiring 13. It is connected to the terminal 53 and constitutes the PMOS transistor 3. Note that a well contact 17 is provided in the n-well 7 and connected to the VDD terminal 47 by an aluminum wiring 13, and the n-well 7 is fixed at the VDD level.

Further, a pair of N-type regions 19.21 are formed on the substrate 1 at a predetermined distance apart, and constitute the drain and source of the NMO transistor 5 (hereinafter referred to as 19).
OS drain region", 21 as rNMO8'/-s drain region"
It is called. ), the NMo5 drain region 19 is connected to the output terminal 51 by the aluminum wiring 13, and the NMOS source region 21 is connected to the Vssm terminal 49 by the aluminum wiring 13. Then, the NMOS drain region 19 and N
The gate electrode 15 of the NMOS transistor 5 is formed by polysilicon on the surface of the substrate 1 between the MOS source region 21 and the MOS source region 21.
is formed, and this gate electrode 15 is connected to the aluminum wiring 1.
3 to an input terminal 53, and constitutes an NMo5 transistor 5.

Note that a substrate contact 23 is provided on the substrate 1 and connected to the Vss terminal 49 by an aluminum wiring 13.
is fixed at the Vss level.

and fi where the PMOS transistor 3 is formed.
A guard link 25 is formed on the substrate 1 side at the boundary between the region and the region where the NMO8 transistor 5 is formed, by a diffusion layer of the opposite conductivity type to that of the substrate 1, that is, the N type. It is connected to a substrate contact 55 by a polysilicon wiring 27, and is connected to a Vss terminal 49 via the substrate 1. Note that, as described above, the guard link 25 is connected to the substrate contact 55 using polysilicon, but a wiring material such as aluminum may also be used in a multilayer wiring process.

FIG. 2 is a schematic cross-sectional view of FIG. 1, and shows an approximate equivalent circuit of a parasitic thyristor constituted by a parasitic transistor and a parasitic resistance existing in the 0MO8 structure. Further, FIG. 3 is a circuit diagram showing only an approximate equivalent circuit of the parasitic thyristor shown in FIG. 2. In FIG. 2, 29 is a vertical parasitic pnp bipolar transistor (hereinafter referred to as an rpnp transistor).
The MOS source region 9 is used as an emitter, the n-well 7 formed in the substrate 1 is used as a base, and the P-type substrate 1 is used as a collector. 31 is a lateral parasitic npn bipolar transistor (hereinafter referred to as "npn transistor").
The npn transistor 31 is an N-type NMOS.
The source region 21 is used as an emitter, the P-type substrate 1 is used as a base, and the n-well 7 formed in the substrate 1 is used as a collector.

45 is a vertical parasitic npn bipolar transistor (hereinafter referred to as "npn transistor") formed by providing a guard ring on the substrate 1;
The transistor 45 is formed with the guard ring 25 formed by an N-type diffusion layer as an emitter, the P-type substrate 1 as a base, and the n-well 7 formed in the substrate 1 as a collector.

And the emitter of pnp transistor 2.9 is Voo
It is connected to the terminal 47, and the base is an npn transistor 4.
It is connected to the collector of transistor 5, and is connected to Voo@47 via the parasitic well resistance 33, and is connected to the collector of npn transistor 31 via the collector parasitic resistance 39.
It is connected to the collector of transistor 31. Also p
The collector of the np transistor 29 is connected to the base of the npn transistor 45 via a collector parasitic resistance 41 of the pnp transistor 29, and the base of the npn transistor 45 is connected to the base of the npn transistor 31 via a base series resistance 43 of the npn transistor 31.
The base of this npn transistor 31 is connected to the Vss terminal 49 via a parasitic substrate resistor 35. Further, the emitter of the npn transistor 31 is directly connected to the Vss terminal 49, and the emitter of the npn transistor 45 is connected to the emitter series resistor 37 of this npn transistor 45, specifically the guard link 25, by the polysilicon wiring 27. This is a spreading resistance between the substrate contact 55 that is connected to the substrate contact 55 and the substrate contact 23 that is connected to the VSS terminal 49 by the aluminum wiring 13, and is connected to the VSS terminal 49 via this resistance.

Next, the operation of this embodiment will be explained using FIG. 3.

Here, the resistance value of the strange well resistance 33 is RN.

When the forward voltage of the transistor is set to VF, and a current exceeding VF/RN flows from terminal A due to external noise, etc., the base-emitter voltage of the pnp transistor 29 becomes VFF1a, and the pnp transistor 29
turns on, and the collector current is the collector parasitic resistance 41 of the pnp transistor 29, the npn transistor 4
5 flows into the Vss terminal 49 via the base series resistor 43 and the parasitic substrate resistor 35. And guard link 25
Since the npn transistor 45 is provided closer to the n-well 7 region than the NMOS source region 21, the npn transistor 45
The base series resistance 43 and the parasitic substrate resistance 35 of npn
The effective base series resistance of the transistor 45 is n
The base-emitter voltage of the pn transistor 45 is
The voltage between the base and emitter of the npn transistor 31 reaches <VF earlier, and the npn transistor 45 turns on.
state. However, the npn transistor 45 is ON.
Even in this state, the voltage drop across the emitter series resistor 37 makes it impossible to obtain a sufficient voltage between the base and emitter of the NPN transistor 45, which is necessary to cause latch-up. As a result, latch-up is less likely to occur.

FIG. 4 is a pattern plan view showing the structure of a CMOS semiconductor device according to a second embodiment of the invention. Its feature is that, in the CMOS semiconductor device shown in FIG. 1, a region 57 is provided around the substrate contact 55 in which ions are not implanted for preventing field inversion.

With this configuration, the impurity concentration on the surface of the substrate between the substrate contact 55 to which the guard ring 25 is connected by the polysilicon wiring 27 and the substrate contact 23 to which the aluminum wiring 13 is connected to the Vss terminal 49 is reduced. can be made lower than the surrounding area, and the emitter series resistance 37 can be made larger. As a result, latch-up resistance can be further improved. In FIG. 4, the same reference numerals as in FIG. 1 indicate the same components, and the explanation thereof will be omitted.

FIG. 5 is a pattern plan view showing the structure of a CMOS semiconductor device according to a third embodiment of the present invention. Its characteristics include the region where the PMOS transistor 3 is formed and the N region of the CMOS semiconductor device shown in FIG.
A guard link 61 is formed in the n-well 7 at the boundary with the region where the MOS transistor 5 is formed by a diffusion layer of a conductivity type opposite to that of the n-well 7, that is, a P-type, and this guard ring 61 is made of polysilicon. It is connected to the well contact 65 through the wiring 63 and connected to the VOO terminal 47 via the n-well 7.

FIG. 6 is a schematic cross-sectional view of FIG. 5, and shows an approximate equivalent circuit of a parasitic thyristor constituted by a parasitic transistor and a parasitic resistance existing in the 0MO8 structure. Further, FIG. 7 is a circuit diagram showing only an approximate equivalent circuit of the parasitic thyristor shown in FIG. 6.

In FIG. 6, in addition to the parasitic transistor shown in FIG.
A pnp transistor 69 is formed, which has 1 as an emitter, an n-well 7 as a base, and a P-type substrate 1 as a collector. The emitter of the ONO transistor 29 is connected to the VDD terminal 47, the base of the PNP transistor 29 is connected to the VDD terminal 47 via the odd well resistor 33, and the base of the PNP transistor 71 is connected to the VDD terminal 47 via the base series resistor 73 of the PNP transistor 71. Connected to the base of the transistor. This pnp transistor 71
The base of is connected to the collector of the npn transistor 45 and the collector of the npn transistor 31 via the collector parasitic resistor 39 of the npn transistor 31. Also, the collector of the pnp transistor 29 is p
It is connected to the collector of the np transistor 71 and to the base of the npn transistor 45 via the collector parasitic resistance 41 of the pnp transistor 29 . The base of this 0p0 transistor 45 is
The base of the npn transistor 45 is connected to the base of the npn i-transistor 31 through the series resistor 43, the base of the npn transistor 31 is connected to the VSS terminal 49 through the parasitic substrate resistor 35, and the emitter of the npn transistor 31 is It is directly connected to VSS terminal 49. Further, the emitter of the pnp transistor 71 is connected to the emitter series resistor 6 of this pnp transistor 71.
7 to the VDD terminal 47, and the emitter of the npn transistor 45 is connected to the npn transistor 4
It is connected to the Vss terminal 49 via the emitter series resistor 37 of No. 5.

In such a circuit configuration, when a current flows from terminal A due to external noise, etc., the collector current of the NPN transistor 45 becomes the base current of the PNP transistor 71, and becomes large enough to supply the current necessary to cause latch-up. PNP with low emitter series resistance
Transistor 29 cannot be driven. As a result, the latch-up prevention effect can be further improved.

As shown in FIG. 8, an NMOS transistor 87 is formed on a substrate 81, a PMO8 transistor 85 is formed in an n-well 83 formed on the substrate 81, and a PM
The region where the OS transistor 85 is formed and the NMOS
A well contact 89 is formed in the n-well 83 at the boundary with the region where the transistor 87 is formed, and a guard ring is formed by a diffusion layer of the conductivity type opposite to that of the n-well 83, that is, the p-type, adjacent to the well contact 89. 91 and connect this guard ring 91 and well contact 8.
9 is electrically connected. Further, a substrate contact 93 is formed on the substrate 81 side of the boundary, and this substrate contact 93 is formed on the substrate 81 side of the boundary.
A guard ring 95 is formed by a diffusion layer of a conductivity type opposite to that of the substrate 81, that is, an N type, and the guard ring 95 and the substrate contact 93 are electrically connected. Even in such a configuration, as described in the third embodiment,
You can get a similar effect.

Note that by forming a plurality of guard rings described in the above three embodiments around one MOS transistor, latch-up resistance can be further strengthened. Furthermore, it goes without saying that latch-up resistance can be further strengthened by using the guard rings described in the above three embodiments together with a guard ring of the same conductivity type as the commonly used substrate or well. .

[Brief explanation of drawings]

FIG. 1 is a pattern plan view of a CMOS semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view schematically showing FIG. 1, and FIG. 3 is an equivalent of the parasitic thyristor shown in FIG. 4 is a pattern plan view of a CMOS semiconductor device according to a second embodiment of the present invention, FIG. 5 is a pattern plan view of a CMOS semiconductor device according to a third embodiment of the present invention, and FIG. 6 is a circuit diagram. is a cross-sectional view showing the outline of FIG. 5, FIG. 7 is an equivalent circuit diagram of the parasitic thyristor shown in FIG. 6,
FIG. 8 is a pattern plan view of a CMOS semiconductor device showing an example of a case where a guard ring and a substrate contact and a guard ring and a well contact are formed next to each other. FIG. 9 is a conventional CMOS semiconductor device in which a guard ring is formed. FIG. 10 is a cross-sectional view showing the outline of FIG. 9, and FIG. 11 is an equivalent circuit diagram of the parasitic thyristor shown in FIG. 10. (Explanation of symbols representing main parts in the figure) 1...P-type silicon substrate 3...P-channel MO8 type transistor 5...N
Channel MO8 type transistor 7...N well 25...Guard ring Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 1 OrIA

Claims (3)

[Claims] (1) The semiconductor substrate of the first conductivity type has M of the second conductivity type.
An OS transistor is formed, and a first conductive type M is formed in a first region of a second conductive type formed in a part of the semiconductor substrate.
By forming an OS transistor, in a semiconductor device in which a CMOS circuit is configured on the semiconductor substrate, the semiconductor substrate side or the first region side near the boundary between the semiconductor substrate and the first region is reversed. A CMO characterized by having a guard ring formed of a conductivity type and to which a predetermined bias is applied via a resistor.
S semiconductor device. (2) In the CMOS semiconductor device according to claim 1, the guard ring is formed on the semiconductor substrate side and has a predetermined position with respect to a contact formed on the semiconductor substrate that is connected to a predetermined bias. A contact formed in a first region that is connected to a surface of the semiconductor substrate separated by a distance via a resistor formed on the semiconductor substrate, and a contact formed on the first region side is connected to a predetermined bias. A CMOS semiconductor device characterized in that the CMOS semiconductor device is connected to a first region surface separated by a predetermined distance from the semiconductor device through a resistor formed on the first region. (3) In the CMOS semiconductor device according to claim 2, there is an impurity concentration between the contact and the semiconductor substrate surface to which the guard ring is connected via the resistor, and the guard ring is connected via the resistor. A CMOS semiconductor device characterized in that impurity concentrations between a first region and a contact are both set to be low.