JP3184168B2 - Semiconductor device protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to protection of a semiconductor device.
More particularly, the present invention relates to a semiconductor device protection device that suppresses occurrence of crosstalk and latch-up.

[0002]

2. Description of the Related Art As shown in FIG. 10, a semiconductor device includes an electrostatic protection device 42 for preventing a circuit (internal circuit) 41 to be protected from being electrostatically damaged by noise applied to an input terminal. . The electrostatic protection device 42 prevents the positive polarity noise applied to the input terminal from being input to the internal circuit, and the electrostatic protection device 42a prevents the negative polarity noise from being input to the internal circuit. For protection from static electricity.

As shown in FIG. 11, for example, the electrostatic protection device 42a is formed near the drain N well 11 with the drain N well 11 formed on the upper surface of the P-type semiconductor substrate 1 as a drain. An N-channel MOS transistor having the N-type diffusion layer 13 as a source is provided.

In the drain N well 11, an N type diffusion layer 12 connected to the input terminals T (T1, T2) of the internal circuit is formed. The N-type diffusion layer 13 is a P-type diffusion layer 14 for back gate bias of an N-channel MOS transistor.
Together with the P-type diffusion layer 1
4 and the N-type diffusion layer 13 are both ground voltage (ground voltage) V
GD is applied.

The P-wells 15 in which the P-type diffusion layers 14 and the N-type diffusion layers 13 are formed are formed in the vicinity of the drain N-well 11 at a ratio of two per one drain N-well 11.

A guard ring N-well 17 having an N-type diffusion layer 16 is formed around the NMOS transistor having the above structure. The power supply voltage VDD is applied to the guard ring N well 17.

In the electrostatic protection device 42a having the above structure,
When a positive voltage due to noise is applied to the input terminals T (T1, T2), the potential of the drain N well 11 functioning as the drain of the N-channel MOS transistor is higher than the potential of the N-type diffusion layer 13 functioning as the source. Become. Thus, a current flows in the forward direction of the NMOS transistor, and a positive polarity noise current can be prevented from flowing to the internal circuit.

On the other hand, when a negative polarity voltage due to noise is applied to the input terminal T (eg, T1), the electrostatic protection device 42b operates and a negative polarity noise current flows from the input terminal T1 to the internal circuit. Can be prevented.

However, in this case, a negative voltage is input to the electrostatic protection device 42a until the electrostatic protection device 42b operates and the potential of the input terminal T1 returns to an appropriate value. Therefore, a parasitic NPN transistor Q12 having the drain N well 11 connected to the input terminal T2 as a collector, the drain N well connected to the input terminal T1 as an emitter, and the region 18 as a base is formed.
In some cases, current was drawn from the input terminal T2. Therefore, crosstalk noise may occur at the input terminal T2.

Note that the guard ring N-well 17 is provided in the electrostatic protection device 42a having the above configuration. As a result, a parasitic NPN transistor Q11 having the P well 15 as a base, the drain N well 11 connected to the input terminal T1 as an emitter, and the guard ring N well 17 as a collector is formed. Therefore, the input terminal T
When a negative polarity noise voltage is applied to 1, a combined current obtained by combining the current from the parasitic NPN transistor Q11 and the current from the parasitic NPN transistor Q12 substantially flows from the drain N well 11 to the input terminal T1.

The current drawn from the input terminal T2 by the parasitic NPN transistor Q12 corresponds to the difference between the combined current and the current from the parasitic NPN transistor Q12.
It is reduced by increasing the current amplification factor of N transistor Q11.

[0012]

However, in the electrostatic protection device 42 having the above-described structure, a back gate bias P is provided between the collector and the emitter of the parasitic NPN transistor Q11.
Since the N-type diffusion layer 14 and the N-type diffusion layer 13 functioning as the source of the NMOS transistor are arranged, the parasitic NP
The current amplification factor of N transistor Q11 cannot be made sufficiently large. Therefore, the parasitic NPN transistor Q1
It is difficult to sufficiently reduce the current drawn from the input terminal T2 by the collector of the input terminal T2, and it is difficult to reduce the crosstalk noise generated at the input terminal T2.

Further, by increasing the base width of the parasitic NPN transistor Q12 (enlarging the formation area of the P region 18 ), the current amplification factor of the parasitic NPN transistor Q12 is sufficiently reduced, and the crosstalk generated at the input terminal T2 is reduced. It is possible to reduce noise. But,
Increasing the base width of the parasitic NPN transistor Q12 increases the area used for the base, so that the electrostatic protection circuit
In some cases, the road 42 becomes large and the cost increases.

In addition, since the current amplification factor of the parasitic NPN transistor Q11 cannot be increased, the occurrence of problems such as latch-up and malfunction may not be suppressed.

The present invention has been made in view of the above situation, and has as its object to provide a semiconductor device that reduces crosstalk without increasing the area of the semiconductor device itself.

Another object of the present invention is to provide a semiconductor device having improved latch-up capability without increasing the area of the semiconductor device itself.

[0017]

Means for Solving the Problems To achieve the above object,
The semiconductor device according to the first aspect of the present inventionProtective equipment
Is a semiconductor substrate of the first conductivity type, and one surface of the semiconductor substrate
A first conductivity type well formed in the well;
Of the second conductivity type connected to the terminal of the circuit to be protected.
A first region, formed in the well and having a first voltage applied thereto;
And surrounds the second region of the second conductivity type and the well.
And a second conductive type guard ring formed as described above.
It is formed in a conductive substrate and contacts the deep part of the guard ring.
Formed adjacent to the first region without touching the first region
A deep region of the second conductivity type.
The first region is formed at a depth equal to or greater than the depth of the well.
It is characterized by being.

According to this configuration, there is provided a deep region of the second conductivity type formed in contact with the deep portion of the guard ring and without being in contact with the first region. Therefore, a parasitic bipolar transistor in which the well, the first region, and the deep region form a base, an emitter, and a collector, respectively, has a sufficiently large current amplification factor and a sufficiently large outflow of current. For this reason, for example, when there is another parasitic bipolar transistor having the first region as an emitter, the outflow amount of the current flowing through the other parasitic bipolar transistor becomes relatively small. Therefore, for example, when the collector of another parasitic bipolar transistor is connected to another terminal of the circuit to be protected, the amount of current drawn from the collector by the other transistor is reduced, and cross-current generated at the other terminal is reduced. Talk noise can be reduced. Also,
The rate at which other parasitic bipolar transistors are turned on is reduced, and defects such as latch-up and malfunction can be reduced.

Further, a protection device for a semiconductor device according to a second aspect of the present invention includes a semiconductor substrate of a first conductivity type, a well of a first conductivity type formed on one surface of the semiconductor substrate, A first region of a second conductivity type formed and connected to a terminal of a circuit to be protected, and a second region of a second conductivity type formed in the well and applied with a first voltage; A second conductivity type guard ring formed so as to surround a well; and a second conductivity type guard ring formed in the semiconductor substrate, in contact with a deep portion of the guard ring, and formed adjacently without contacting the first region. A second conductive type deep region, wherein the first region and the second region respectively form a source or a drain of a field effect transistor , and the first region
Is formed at a depth equal to or greater than the depth of the well .

Further, the well, the first region, and the deep region include a base of a parasitic bipolar transistor,
Preferably, an emitter and a collector are formed, and the emitter and the collector of the parasitic transistor are preferably formed adjacent to each other.

According to this configuration, since the distance between the emitter and the collector of the parasitic transistor is substantially short, the current amplification factor of the parasitic transistor increases.

It is preferable that the first region and the second region respectively form a source or a drain of a field effect transistor. In this case, when a voltage of the first polarity is applied to the input terminal of the circuit to be protected, the voltage may be reduced by flowing a current through the field-effect transistor. When a voltage is applied, a current flows through a parasitic transistor having the deep region and the guard ring as a collector, the well as a base, and the first region as an emitter, thereby lowering the voltage. Is also good.

The semiconductor device may further include a third region of the first conductivity type formed in the well and to which a second voltage for biasing the well is applied.

A plurality of circuits to be protected and a plurality of protection devices may be formed on the semiconductor substrate. Each of the protection devices is connected to the circuit to be protected in the first region. Is also good. The deep region and the guard ring, for example,
Form the collector of the parasitic bipolar transistor. Further, the protective device more than one place, when the first region to the positive voltage of one of the protection device, the noise of the first negative voltage to the region of the other protective device is applied, the the parasitic bipolar transistor, a first one of the protective device
It may be configured to suppress a current flowing from the area of the other protection device to the first area of the other protection device . Further, a protection device for a semiconductor device according to a third aspect of the present invention includes a semiconductor substrate of a first conductivity type, a well of a first conductivity type formed in the semiconductor substrate, and a protection substrate formed in the well . A drain formed of a first region of a second conductivity type connected to a terminal , a source formed in the well and formed of a second region of a second conductivity type, formed in the well, A first conductivity type diffusion layer having a well as a reference level; a second conductivity type guard ring formed in the well so as to surround the well; a deep portion in the well or deeper than the well A second conductive type deep region formed in a portion, in contact with a deep portion of the guard ring, and formed in non-contact and close proximity to the drain region ;
The drain is formed deeper than the well, for example.
That, characterized in that. The well, the drain, the guard ring and the deep region, for example,
A base, an emitter and a collector of the parasitic bipolar transistor are formed, respectively, and the emitter and the collector of the parasitic transistor are formed adjacent to each other. In addition,
The protective device is more disposed, a voltage of positive polarity is applied to the protective terminal of one protective device, when a negative voltage to the protective terminal of another protective device is applied, and the well, and the drain The deep region and the guard ring are a base,
Emitter, by the parasitic bipolar transistor formed by a collector is turned on, the protection of one protective device
The current flowing from the use terminal protecting terminals of other protective devices may be suppressed.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electrostatic protection device for a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a protection diode of an electrostatic protection device according to an embodiment of the present invention, and FIG.
It is sectional drawing in the -A line. As shown in FIG. 2, the electrostatic protection device according to the embodiment of the present invention includes a deep portion N well 10 formed in contact with a deep portion of guard ring N well 17 of the electrostatic protection device shown in FIG. Is provided. The deep portion N well 10 is arranged adjacent to and not in contact with the corresponding drain N well 11. Also, the drain N well 1
1 is formed at a depth equal to or greater than the depth of the P well 15.

In the electrostatic protection device having the above configuration, as shown in FIG. 2, the drain N connected to the input terminal T1
A parasitic NPN transistor Q1 having the well 11 as an emitter, the P well 15 as a base, and the deep N well 10 connected to the guard ring N well 17 as a collector.
Is formed. Further, a parasitic NPN transistor Q2 is formed in which the drain N well 11 connected to the input terminal T2 is a collector, the P region 18 is a base, and the drain N well 11 connected to the input terminal T1 is a collector. The drain N well 11 and the P well 1
Each of the N-type diffusion layers 13 formed in the
The drain and the source of the MOS transistor are formed.

Next, the operation of the electrostatic protection device having the above configuration will be described. First, when a positive polarity voltage due to noise is applied to the input terminal T1, the drain N well 1 functioning as the drain of the NMOS transistor of the electrostatic protection device is provided.
The potential of 1 is higher than the potential of the N-type diffusion layer 13 functioning as a source. This allows a current to flow in the forward direction of the NMOS transistor, lowering the voltage (reducing the absolute value of the voltage), and preventing a noise current from flowing to the internal circuit.

On the other hand, when a negative polarity voltage due to noise is applied to the input terminal T1, an electrostatic protection device for negative polarity (not shown) operates to cancel the application of the noise voltage to the input terminal T1. In the meantime, the parasitic NPN transistors Q1 and Q2 formed in the electrostatic protection device operate.

At this time, the distance between the collector and the emitter of the parasitic NPN transistor Q1 is equal to the parasitic NP shown in FIG.
It is shorter than the distance between the collector and the emitter of the N transistor Q11. Therefore, the current amplification factor of the parasitic NPN transistor Q1 is larger than the current amplification factor of the parasitic NPN transistor Q11. For this reason, when a negative polarity voltage is applied to the input terminal T1, the proportion of the current flowing through the parasitic NPN transistor Q1 to the current flowing through the drain N well 11 connected to the input terminal T1 increases, so that Therefore, the ratio of the current due to the parasitic NPN transistor Q2 decreases. Therefore, the current drawn by the parasitic NPN transistor Q2 from the input terminal T2 decreases, and the crosstalk of the input terminal T2 due to the noise current generated at the input terminal T1 decreases.

FIG. 3 is a graph showing the relationship between the distance between the guard ring N well 17 and the drain N well 11 and the magnitude of the crosstalk current in the embodiment of the present invention and the conventional electrostatic protection device. As shown in FIG. 3, at the same distance, the magnitude of the crosstalk current of the electrostatic protection device according to the embodiment of the present invention is less than half that of the conventional configuration. .

As described above, the electrostatic protection device according to the embodiment of the present invention includes the deep portion N well 10 formed in contact with the deep portion of the guard ring N well 17. The deep N-well 10 is arranged adjacent to and not in contact with the drain N-well 11. Thereby, the input terminal T1
When a negative polarity voltage due to noise is applied to
The current flowing from the parasitic transistor Q1 to the drain N well 11 connected to the input terminal T1 reduces the current drawn by the parasitic transistor Q2 from the input terminal T2. Therefore, crosstalk noise generated at the input terminal T2 can be reduced.

The deep N-well 10 is formed from the surface of the P-type semiconductor substrate 1 to about 0.7 to
Impurities (for example, phosphorus (P), arsenic (As), antimony (S
b) etc.).

In the above description, the electrostatic protection device according to the embodiment of the present invention is applied to measures against crosstalk. However, the electrostatic protection device according to the embodiment of the present invention can also be applied to measures against latch-up. It is. FIG. 4 shows an example of the configuration of an electrostatic protection device when the electrostatic protection device according to the embodiment of the present invention is applied to latch-up measures. As shown in the drawing, an N-well 21 is formed in the vicinity of an NMOS transistor surrounded by a guard ring 17 in the electrostatic protection device for preventing latch-up. P-type diffusion layers 22, 23 and an N-type diffusion layer 24 are formed in the N-well 21, and a P-channel MOS transistor having the P-type diffusion layer 22 as a drain and the P-type diffusion layer 23 as a source is formed. ing.
The N-type diffusion layer 24 has a function of back gate biasing the P-type diffusion layer 23 of the P-channel MOS transistor.

In this case, a parasitic NPN transistor Q3 having the drain N well 11 as an emitter, the P well 15 as a base and the N well 21 as a collector, the P type diffusion layer 23 as an emitter, the N well 21 as a base, P
Parasitic PNP transistor Q with well 15 as collector
4 are formed. Further, the N well 21 and the N type diffusion layer 24
Is formed. A parasitic NPN transistor Q1 having a P-well 15 as a base, a deep N-well 10 as a collector, and a drain N-well 11 as an emitter is also formed similarly to the electrostatic protection device for preventing crosstalk.

FIG. 5 is an equivalent circuit diagram of the above-structured electrostatic protection device for preventing latch-up. As shown in FIG.
When a negative voltage due to noise is applied to the terminal, a current flows through the parasitic resistance R1. Deep part N well 10
In the conventional electrostatic protection device not provided with the above, the parasitic PNP transistor Q4 is turned on by the current flowing through the parasitic resistor R1, the thyristor composed of the parasitic NPN transistor Q3 and the parasitic PNP transistor Q4 operates, and latch-up occurs.

On the other hand, in the electrostatic protection device provided with the deep N-well 10 shown in FIG. 4, the parasitic transistor Q1 has a sufficiently larger current amplification factor than the conventional parasitic Q11.
The amount of current flowing into the N-transistor Q3 is reduced, and a current large enough to turn on the parasitic PNP transistor Q4 does not flow through the parasitic resistor R1. That is, the latch-up resistance is improved.

FIG. 6 is a graph showing the latch-up tolerance of the conventional electrostatic protection device and the latch-up tolerance of the electrostatic protection device according to the embodiment of the present invention. As shown in FIG.
The latch-up resistance of the electrostatic protection device according to the embodiment of the present invention is remarkably improved as compared with the conventional one.

The electrostatic protection device according to the embodiment of the present invention has a guard ring N well 1 as shown in FIG.
7 can be applied to an electrostatic protection device including an N-type MOS transistor in the vicinity. In this case, the N-type diffusion layer 31 functioning as the drain of the N-type MOS transistor is used as a collector, the P-well 15 is used as a base, and the drain N
Parasitic NPN transistor Q having well 11 as emitter
5 and the parasitic NPN transistor Q1 shown in FIG. Since the distance between the collector and the emitter of the parasitic NPN transistor Q1 is sufficiently shorter than the distance between the collector and the emitter of the parasitic NPN transistor Q5, the current amplification factor of the parasitic NPN transistor Q1 is sufficiently larger than the current amplification factor of the parasitic NPN transistor Q5. .

For this reason, when a negative polarity voltage is applied to the input terminal T1, the parasitic NPN of the current flowing through the drain N well 11 connected to the input terminal T1.
Since the ratio of the current by the transistor Q1 increases, the ratio of the current by the parasitic NPN transistor Q5 relatively decreases. Therefore, the parasitic NPN transistor Q5 becomes N
The current drawn from the N-type diffusion layer 31 of the N-type MOS transistor decreases, and the crosstalk to the N-type diffusion layer 31 of the N-type MOS transistor due to the noise current generated at the input terminal T1 decreases.

The electrostatic protection device according to the embodiment of the present invention can be applied to a logic inverter circuit as shown in FIG. In this case, by forming the protection diode near the inverter circuit, the equivalent circuit shown in FIG. 8 can be obtained. Deep part N well 10
In the conventional electrostatic protection device in which is not formed, the parasitic NPN transistor Q6 of the inverter operates, and a malfunction occurs in which the output of the inverter shown in FIG. 8 goes low when the output is high. However, in the electrostatic protection device according to the embodiment of the present invention, the current flowing through the parasitic transistor Q6 is reduced because the current amplification factor of the parasitic transistor Q1 is large. Therefore, malfunction does not occur.

Further, the electrostatic protection device according to the embodiment of the present invention can be applied to a current mirror circuit as shown in FIG. In this case, by forming the protection diode near the current mirror circuit, the equivalent circuit shown in FIG. 9 can be obtained. In the conventional electrostatic protection device in which the deep-layer N-well 10 is not formed, the output current value increases by the amount flowing through the parasitic transistor Q7, which causes a problem that circuit characteristics deteriorate. However, in the electrostatic protection device according to the embodiment of the present invention, the current flowing through the parasitic transistor Q7 is small because the current amplification factor of the parasitic transistor Q1 is large. For this reason, deterioration of the circuit characteristics can be prevented.

As described above, an exceptional effect of preventing malfunctions and deterioration of characteristics due to noise from the input terminal is obtained in both analog and logic LSIs and in an LSI in which analog and logic are mixed.

[0043]

As described above , according to the present invention ,
A second conductive type deep region formed in contact with the deep portion of the second conductive type guard ring and not adjacent to the second conductive type first region but adjacent to the first region; Therefore, when a negative polarity voltage is applied from the terminal to the first region, a deep region serves as a collector, the first region serves as an emitter, and a well-based parasitic transistor causes a large current to flow through the input terminal. Therefore, the collector is connected to the other input terminal, and the current drawn from the other input terminal by the parasitic transistor having the first region as the emitter is reduced. For this reason, crosstalk noise generated at other input terminals can be reduced without increasing the size of the device.

In addition, since the deep region serves as a collector, the first region serves as an emitter, and a well-based parasitic transistor has a large current amplification factor, the occurrence of problems such as latch-up and malfunction can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of an electrostatic protection device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 shows the relationship between the parasitic NPN transistor Q1 of the electrostatic protection device according to the embodiment of the present invention and the magnitude of crosstalk noise, and the relationship between the parasitic NPN transistor Q11 of the conventional electrostatic protection device and the magnitude of crosstalk noise. It is a figure showing a relation.

FIG. 4 is a modified example of the configuration of the electrostatic protection device in the case where the electrostatic protection device according to the embodiment of the present invention is applied to latch-up measures.

FIG. 5 is an equivalent circuit diagram of the electrostatic protection device shown in FIG.

6 is a diagram showing a latch-up tolerance of the electrostatic protection device of FIG. 4 and a latch-up tolerance of a conventional electrostatic protection device.

FIG. 7 is a modification of the configuration of the electrostatic protection device.

FIG. 8 is an equivalent circuit diagram when the electrostatic protection device of the present invention is applied to a logic inverter circuit.

FIG. 9 is an equivalent circuit diagram when the electrostatic protection device of the present invention is applied to a current mirror circuit.

FIG. 10 is a diagram illustrating a configuration of a semiconductor device.

FIG. 11 is a diagram illustrating a configuration of a conventional electrostatic protection device.

[Explanation of symbols]

Reference Signs List 11 drain N well 12, 13 , 16 N type diffusion layer 14 P type diffusion layer 15 P well 17 guard ring N well Q1 to Q12 parasitic NPN transistor 41 circuit to be protected

Continuation of front page (56) References JP-A-5-206387 (JP, A) JP-A-9-191080 (JP, A) JP-A-3-157968 (JP, A) JP-A-7-66370 (JP) , A) JP-A-10-41469 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/8249 H01L 27/06

Claims (11)

(57) [Claims] A first conductive type semiconductor substrate; a first conductive type well formed on one surface of the semiconductor substrate; and a second conductive type formed in the well and connected to a terminal of a circuit to be protected. A first region of the mold; and a second region formed in the well and to which a first voltage is applied.
A second region of a conductivity type; a guard ring of a second conductivity type formed so as to surround the well; and a first region formed in the semiconductor substrate and in contact with a deep portion of the guard ring. And a deep region of the second conductivity type formed adjacently without contacting the first region. The first region of the second conductivity type is formed at a depth equal to or greater than the depth of the well. Of a semiconductor device characterized by the following:
Protective equipment . 2. A semiconductor substrate of a first conductivity type, a well of a first conductivity type formed on one surface of the semiconductor substrate, and a second conductivity formed in the well and connected to a terminal of a circuit to be protected. A first region of a mold, a second region of a second conductivity type formed in the well and to which a first voltage is applied, and a guard ring of a second conductivity type formed to surround the well. A second conductivity type deep region formed in the semiconductor substrate, in contact with a deep portion of the guard ring, and formed adjacently without contacting the first region; region and the and the second region of each source or of the field effect transistor to form a drain, a first region of the second conductivity type, over the depth of the well
Of a semiconductor device characterized by being formed at a depth of
Protective equipment . 3. The well, the first region, and the deep region form a base, an emitter, and a collector of a parasitic bipolar transistor, and the emitter and the collector of the parasitic transistor are formed adjacent to each other. The semiconductor device according to claim 1 , wherein
Protective equipment . 4. When a voltage of a first polarity is applied to an input terminal of the circuit to be protected, a current flows through the field effect transistor to reduce the voltage, and a voltage of a second polarity is applied. Applying a current through a parasitic transistor having the deep region and the guard ring as a collector, the well as a base, and the first region as an emitter when the voltage is applied, thereby reducing the voltage. protection apparatus for a semiconductor device according to any one of claims 1 to 3, wherein. 5. The semiconductor device according to claim 1, further comprising a third region of a first conductivity type formed in said well and to which a second voltage for biasing said well is applied.
5. The protection device for a semiconductor device according to claim 4 . Wherein said circuit to be protected in the semiconductor substrate and the coercive
A plurality of protection devices are formed, and each protection device is provided with a first conductive type of the second conductivity type on a circuit to be protected.
They are connected by a region, that protection device of a semiconductor device according to any one of claims 1 to 5, characterized in. And wherein said deep region and the guard ring forms the collector of the parasitic bipolar transistor, it protective device for a semiconductor device according to any one of claims 1 to 6, wherein. Wherein said protection device are arranged two, positive voltage to the first region of one of the protective device, the other holding
When a negative voltage noise is applied to the first region of the protection device , the parasitic bipolar transistor suppresses a current flowing from the first region of one protection device to the first region of the other protection device . to the protection apparatus for a semiconductor device according to any one of claims 1 to 7, characterized in that. 9. A semiconductor substrate of a first conductivity type, a well of a first conductivity type formed in the semiconductor substrate, and a first conductivity type of a second conductivity type formed in the well and connected to a protection terminal . A drain formed of a region, a source formed in the well and formed of a second region of the second conductivity type, and a first conductivity type diffusion layer formed in the well and having the well as a reference level A second conductive type guard ring formed so as to surround the well; and a deeper part in the well or a part deeper than the well, which is in contact with a deeper part of the guard ring,
A deep region of the second conductivity type formed in non-contact proximity to the drain region , wherein the drain is formed deeper than the well.
That the protection device wherein a. 10. The well, the drain, the guard ring, and the deep region form a base, an emitter, and a collector of a parasitic bipolar transistor, respectively, and the emitter and the collector of the parasitic transistor are adjacent to each other. 10. The protection device for a semiconductor device according to claim 9 , wherein the protection device is formed.
Place . Wherein said protective device is more disposed, the protection one
A positive voltage of the protection pin of the device is applied, other protected
When a negative voltage is applied to the protection terminal of the device , a parasitic bipolar transistor formed by the well, the drain, the deep region and the guard ring serving as a base, an emitter, and a collector is turned on. the protection of other protective device from its protective terminal of one protective device
The protection device for a semiconductor device according to claim 9 , wherein a current flowing through the terminal for use is suppressed.