JP2000208712A - Electrostatic protection device of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce crosstalks of a semiconductor device and improve latchup durability amount. SOLUTION: A protective diode, wherein an N-well (drain N-well) 11 for protective measures is formed in the drain of an N-channel MOS transistor to be used for electrostatic breakdown measures of a semiconductor device, and a guard ring N-well 17 surrounding the protective diode are formed in a P-type semiconductor substrate. A deep layer part N-well 10 is formed being in contact with the deep layer part of the guard ring N-well 17 and being adjacent to the N-well 11 of the drain of the protective diode, without coming into contact with the well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection device for a semiconductor device, and more particularly to an electrostatic protection device for a semiconductor device that suppresses occurrence of crosstalk and latch-up.

[0002]

2. Description of the Related Art As shown in FIG. 10, a semiconductor device includes an electrostatic protection device 42 for preventing a circuit (internal circuit) 41 to be protected from being electrostatically damaged by noise applied to an input terminal. . The electrostatic protection device 42 includes a positive polarity electrostatic protection device 42a for preventing the positive polarity noise applied to the input terminal from being input to the internal circuit, and a negative polarity noise being input to the internal circuit. And a negative-polarity electrostatic protection device 42b for preventing the occurrence of the negative polarity.

As shown in FIG. 11, for example, as shown in FIG. 11, a positive polarity electrostatic protection device 42a has a drain N well 11 formed on the upper surface of a P-type semiconductor substrate 1 and a drain formed near the drain N well 11. An N-channel MOS transistor having the source of the N-type diffusion layer 13 is provided.

In the drain N well 11, an N type diffusion layer 12 connected to the input terminals T (T1, T2) of the internal circuit is formed. The N-type diffusion layer 13 is a P-type diffusion layer 14 for back gate bias of an N-channel MOS transistor.
Together with the P-type diffusion layer 1
4 and the N-type diffusion layer 13 are both ground voltage (ground voltage) V
GD is applied.

The P-wells 15 in which the P-type diffusion layers 14 and the N-type diffusion layers 13 are formed are formed in the vicinity of the drain N-well 11 at a ratio of two per one drain N-well 11.

A guard ring N-well 17 having an N-type diffusion layer 16 is formed around the NMOS transistor having the above structure. The power supply voltage VDD is applied to the guard ring N well 17. A ground P well 18 is formed between adjacent guard ring N wells 17.

[0007] The positive polarity electrostatic protection device 42 having the above configuration.
a, when a positive polarity voltage due to noise is applied to the input terminal T (T1, T2), the N-channel MOS
The potential of the drain N well 11 functioning as the drain of the transistor is higher than the potential of the N-type diffusion layer 13 functioning as the source. Thus, a current flows in the forward direction of the NMOS transistor, and a positive polarity noise current can be prevented from flowing to the internal circuit.

On the other hand, when a negative polarity voltage due to noise is applied to the input terminal T (eg, T1), a negative polarity electrostatic protection device 42b (not shown) operates, and the negative polarity is applied from the input terminal T1 to the internal circuit. Can be prevented from flowing.

However, in this case, a negative polarity voltage is input to the positive polarity electrostatic protection device until the negative polarity electrostatic protection device 42b operates and the potential of the input terminal T1 returns to an appropriate value. Would. Therefore, the input terminal T
The drain N well 11 connected to the drain 2 as a collector,
In some cases, a parasitic NPN transistor Q12 having the drain N well connected to the input terminal T1 as an emitter and the P well 118 as a base is formed, and current may be drawn from the input terminal T2. Therefore, crosstalk noise may occur at the input terminal T2.

The guard ring N-well 17 is provided in the positive polarity electrostatic protection device 42a having the above configuration. Thus, a parasitic N-type transistor having the P-well 15 as a base, the drain N-well 11 connected to the input terminal T1 as an emitter, and the guard ring N-well 17 as a collector.
A PN transistor Q11 is formed. For this reason,
When a negative polarity noise voltage is applied to the input terminal T1, the combined current obtained by combining the current from the parasitic NPN transistor Q11 and the current from the parasitic NPN transistor Q12 substantially flows from the drain N well 11 to the input terminal T.
Flow to 1.

The current drawn from the input terminal T2 by the parasitic NPN transistor Q12 corresponds to the difference between the combined current and the current from the parasitic NPN transistor Q12.
It is reduced by increasing the current amplification factor of N transistor Q11.

[0012]

However, in the electrostatic protection device 42 having the above-described structure, a back gate bias P is provided between the collector and the emitter of the parasitic NPN transistor Q11.
Since the N-type diffusion layer 14 and the N-type diffusion layer 13 functioning as the source of the NMOS transistor are arranged, the parasitic NP
The current amplification factor of N transistor Q11 cannot be made sufficiently large. Therefore, the parasitic NPN transistor Q1
It is difficult to sufficiently reduce the current drawn from the input terminal T2 by the collector of the input terminal T2, and it is difficult to reduce the crosstalk noise generated at the input terminal T2.

Further, by increasing the base width of the parasitic NPN transistor Q12 (enlarging the formation area of the ground P well 18), the parasitic NPN transistor Q12 is formed.
12, the crosstalk noise generated at the input terminal T2 can be reduced. However, when the base width of the parasitic NPN transistor Q12 is increased, the area used for the base increases, so that the electrostatic protection device 42 may become large and the cost may increase.

In addition, since the current amplification factor of the parasitic NPN transistor Q11 cannot be increased, the occurrence of problems such as latch-up and malfunction may not be suppressed.

The present invention has been made in view of the above situation, and has as its object to provide a semiconductor device that reduces crosstalk without increasing the area of the semiconductor device itself.

Another object of the present invention is to provide a semiconductor device having improved latch-up capability without increasing the area of the semiconductor device itself.

[0017]

To achieve the above object, an electrostatic protection device for a semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type and a first conductivity type formed on one surface of the semiconductor substrate. A first region of the second conductivity type formed in the well and connected to a terminal of a circuit to be protected;
A second region of a second conductivity type, formed in the well, to which a first voltage is applied, a guard ring of a second conductivity type formed to surround the well, and formed in the semiconductor substrate; Contacting the deep part of the guard ring,
And a deep region of the second conductivity type formed adjacently without contacting the region.

According to this configuration, there is provided a deep region of the second conductivity type formed in contact with the deep portion of the guard ring and without being in contact with the first region. Therefore, the parasitic bipolar transistor in which the well, the first region, and the deep region form a base, an emitter, and a collector, respectively, has a sufficiently large current amplification factor and a sufficiently large current outflow. For this reason, for example, when there is another parasitic bipolar transistor having the first region as an emitter, the outflow amount of the current flowing through the other parasitic bipolar transistor becomes relatively small. Therefore, for example, when the collector of another parasitic bipolar transistor is connected to another terminal of the circuit to be protected, the amount of current drawn from the collector by the other transistor is reduced, and cross-current generated at the other terminal is reduced. Talk noise can be reduced. Also,
The rate at which other parasitic bipolar transistors are turned on is reduced, and defects such as latch-up and malfunction can be reduced.

Note that, since the deep region is formed adjacent to the first region, the first region is preferably formed at a depth equal to or greater than the depth of the well.

Further, the well, the first region, and the deep region include a base of a parasitic bipolar transistor,
Preferably, an emitter and a collector are formed, and the emitter and the collector of the parasitic transistor are preferably formed adjacent to each other.

According to this configuration, since the distance between the emitter and the collector of the parasitic transistor is substantially short, the current amplification factor of the parasitic transistor increases.

It is preferable that the first region and the second region respectively form a source or a drain of a field effect transistor. In this case, when a voltage of the first polarity is applied to the input terminal of the circuit to be protected, the voltage may be reduced by flowing a current through the field-effect transistor. When a voltage is applied, a current flows through a parasitic transistor having the deep region and the guard ring as a collector, the well as a base, and the first region as an emitter, thereby lowering the voltage. Is also good.

The semiconductor device may further include a third region of the first conductivity type formed in the well and to which a second voltage for biasing the well is applied.

Further, a plurality of circuits to be protected and a plurality of electrostatic protection devices may be formed on the semiconductor substrate, and each of the electrostatic protection devices is connected to the circuit to be protected in the first region. Is also good.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electrostatic protection device for a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a protection diode of an electrostatic protection device according to an embodiment of the present invention, and FIG.
It is sectional drawing in the -A line. As shown in FIG. 2, the electrostatic protection device according to the embodiment of the present invention includes a deep portion N well 10 formed in contact with a deep portion of guard ring N well 17 of the electrostatic protection device shown in FIG. Is provided. The deep portion N well 10 is arranged adjacent to and not in contact with the corresponding drain N well 11. Also, the drain N well 1
1 is formed at a depth equal to or greater than the depth of the P well 15.

In the electrostatic protection device having the above configuration, as shown in FIG. 2, the drain N connected to the input terminal T1
A parasitic NPN transistor Q1 having the well 11 as an emitter, the P well 15 as a base, and the deep N well 10 connected to the guard ring N well 17 as a collector.
Is formed. In addition, a parasitic NPN transistor Q2 having the drain N well 11 connected to the input terminal T2 as a collector, the ground P well 18 as a base, and the drain N well 11 connected to the input terminal T1 as a collector is formed. . Note that the N-type diffusion layers 13 formed in the drain N well 11 and the P well 15 form the drain and source of the NMOS transistor, respectively.

Next, the operation of the electrostatic protection device having the above configuration will be described. First, when a positive polarity voltage due to noise is applied to the input terminal T1, the drain N well 1 functioning as the drain of the NMOS transistor of the electrostatic protection device is provided.
The potential of 1 is higher than the potential of the N-type diffusion layer 13 functioning as a source. This allows a current to flow in the forward direction of the NMOS transistor, lowering the voltage (reducing the absolute value of the voltage), and preventing a noise current from flowing to the internal circuit.

On the other hand, when a negative polarity voltage due to noise is applied to the input terminal T1, an electrostatic protection device for negative polarity (not shown) operates to cancel the application of the noise voltage to the input terminal T1. In the meantime, the parasitic NPN transistors Q1 and Q2 formed in the electrostatic protection device operate.

At this time, the distance between the collector and the emitter of the parasitic NPN transistor Q1 is equal to the parasitic NP shown in FIG.
It is shorter than the distance between the collector and the emitter of the N transistor Q11. Therefore, the current amplification factor of the parasitic NPN transistor Q1 is larger than the current amplification factor of the parasitic NPN transistor Q11. For this reason, when a negative polarity voltage is applied to the input terminal T1, the proportion of the current flowing through the parasitic NPN transistor Q1 to the current flowing through the drain N well 11 connected to the input terminal T1 increases, so that Therefore, the ratio of the current due to the parasitic NPN transistor Q2 decreases. Therefore, the current drawn by the parasitic NPN transistor Q2 from the input terminal T2 decreases, and the crosstalk of the input terminal T2 due to the noise current generated at the input terminal T1 decreases.

FIG. 3 is a graph showing the relationship between the distance between the guard ring N well 17 and the drain N well 11 and the magnitude of the crosstalk current in the embodiment of the present invention and the conventional electrostatic protection device. As shown in FIG. 3, at the same distance, the magnitude of the crosstalk current of the electrostatic protection device according to the embodiment of the present invention is less than half that of the conventional configuration. .

As described above, the electrostatic protection device according to the embodiment of the present invention includes the deep portion N well 10 formed in contact with the deep portion of the guard ring N well 17. The deep N-well 10 is arranged adjacent to and not in contact with the drain N-well 11. Thereby, the input terminal T1
When a negative polarity voltage due to noise is applied to
The current flowing from the parasitic transistor Q1 to the drain N well 11 connected to the input terminal T1 reduces the current drawn by the parasitic transistor Q2 from the input terminal T2. Therefore, crosstalk noise generated at the input terminal T2 can be reduced.

The deep N-well 10 is formed from the surface of the P-type semiconductor substrate 1 to about 0.7 to
Impurities (for example, phosphorus (P), arsenic (As), antimony (S
b) etc.).

In the above description, the electrostatic protection device according to the embodiment of the present invention is applied to measures against crosstalk. However, the electrostatic protection device according to the embodiment of the present invention can also be applied to measures against latch-up. It is. FIG. 4 shows an example of the configuration of an electrostatic protection device when the electrostatic protection device according to the embodiment of the present invention is applied to latch-up measures. As shown in the drawing, an N-well 21 is formed in the vicinity of an NMOS transistor surrounded by a guard ring 17 in the electrostatic protection device for preventing latch-up. P-type diffusion layers 22, 23 and an N-type diffusion layer 24 are formed in the N-well 21, and a P-channel MOS transistor having the P-type diffusion layer 22 as a drain and the P-type diffusion layer 23 as a source is formed. ing.
The N-type diffusion layer 24 has a function of back gate biasing the P-type diffusion layer 23 of the P-channel MOS transistor.

In this case, a parasitic NPN transistor Q3 having the drain N well 11 as an emitter, the P well 15 as a base and the N well 21 as a collector, the P type diffusion layer 23 as an emitter, the N well 21 as a base, P
Parasitic PNP transistor Q with well 15 as collector
4 are formed. Further, the N well 21 and the N type diffusion layer 24
Is formed. A parasitic NPN transistor Q1 having a P-well 15 as a base, a deep N-well 10 as a collector, and a drain N-well 11 as an emitter is also formed similarly to the electrostatic protection device for preventing crosstalk.

FIG. 5 is an equivalent circuit diagram of the above-structured electrostatic protection device for preventing latch-up. As shown in FIG.
When a negative voltage due to noise is applied to the terminal, a current flows through the parasitic resistance R1. Deep part N well 10
In the conventional electrostatic protection device not provided with the above, the parasitic PNP transistor Q4 is turned on by the current flowing through the parasitic resistor R1, the thyristor composed of the parasitic NPN transistor Q3 and the parasitic PNP transistor Q4 operates, and latch-up occurs.

On the other hand, in the electrostatic protection device provided with the deep N-well 10 shown in FIG. 4, the parasitic transistor Q1 has a sufficiently larger current amplification factor than the conventional parasitic Q11.
The amount of current flowing into the N-transistor Q3 is reduced, and a current large enough to turn on the parasitic PNP transistor Q4 does not flow through the parasitic resistor R1. That is, the latch-up resistance is improved.

FIG. 6 is a graph showing the latch-up tolerance of the conventional electrostatic protection device and the latch-up tolerance of the electrostatic protection device according to the embodiment of the present invention. As shown in FIG.
The latch-up resistance of the electrostatic protection device according to the embodiment of the present invention is remarkably improved as compared with the conventional one.

The electrostatic protection device according to the embodiment of the present invention has a guard ring N well 1 as shown in FIG.
7 can be applied to an electrostatic protection device including an N-type MOS transistor in the vicinity. In this case, the N-type diffusion layer 31 functioning as the drain of the N-type MOS transistor is used as a collector, the P-well 15 is used as a base, and the drain N
Parasitic NPN transistor Q having well 11 as emitter
5 and the parasitic NPN transistor Q1 shown in FIG. Since the distance between the collector and the emitter of the parasitic NPN transistor Q1 is sufficiently shorter than the distance between the collector and the emitter of the parasitic NPN transistor Q5, the current amplification factor of the parasitic NPN transistor Q1 is sufficiently larger than the current amplification factor of the parasitic NPN transistor Q5. .

For this reason, when a negative polarity voltage is applied to the input terminal T1, the parasitic NPN of the current flowing through the drain N well 11 connected to the input terminal T1.
Since the ratio of the current by the transistor Q1 increases, the ratio of the current by the parasitic NPN transistor Q5 relatively decreases. Therefore, the parasitic NPN transistor Q5 becomes N
The current drawn from the N-type diffusion layer 31 of the N-type MOS transistor decreases, and the crosstalk to the N-type diffusion layer 31 of the N-type MOS transistor due to the noise current generated at the input terminal T1 decreases.

The electrostatic protection device according to the embodiment of the present invention can be applied to a logic inverter circuit as shown in FIG. In this case, by forming the protection diode near the inverter circuit, the equivalent circuit shown in FIG. 8 can be obtained. Deep part N well 10
In the conventional electrostatic protection device in which is not formed, the parasitic NPN transistor Q6 of the inverter operates, and a malfunction occurs in which the output of the inverter shown in FIG. 8 goes low when the output is high. However, in the electrostatic protection device according to the embodiment of the present invention, the current flowing through the parasitic transistor Q6 is reduced because the current amplification factor of the parasitic transistor Q1 is large. Therefore, malfunction does not occur.

Further, the electrostatic protection device according to the embodiment of the present invention can be applied to a current mirror circuit as shown in FIG. In this case, by forming the protection diode near the current mirror circuit, the equivalent circuit shown in FIG. 9 can be obtained. In the conventional electrostatic protection device in which the deep-layer N-well 10 is not formed, the output current value increases by the amount flowing through the parasitic transistor Q7, which causes a problem that circuit characteristics deteriorate. However, in the electrostatic protection device according to the embodiment of the present invention, the current flowing through the parasitic transistor Q7 is small because the current amplification factor of the parasitic transistor Q1 is large. For this reason, deterioration of the circuit characteristics can be prevented.

As described above, an exceptional effect of preventing malfunctions and deterioration of characteristics due to noise from the input terminal is obtained in both analog and logic LSIs and in an LSI in which analog and logic are mixed.

[0043]

As described above, according to the electrostatic protection device of the present invention, it is possible to contact the deep portion of the guard ring of the second conductivity type without contacting the first region of the second conductivity type. A second conductive type deep region formed adjacent to the first region;
Therefore, when a negative polarity voltage is applied from the terminal to the first region, a deep region serves as a collector, the first region serves as an emitter, and a well-based parasitic transistor causes a large current to flow through the input terminal. Therefore, the collector is connected to the other input terminal, and the current drawn from the other input terminal by the parasitic transistor having the first region as the emitter is reduced. For this reason, crosstalk noise generated at other input terminals can be reduced without increasing the size of the device.

In addition, since the deep region serves as a collector, the first region serves as an emitter, and a well-based parasitic transistor has a large current amplification factor, the occurrence of problems such as latch-up and malfunction can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of an electrostatic protection device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 shows the relationship between the parasitic NPN transistor Q1 of the electrostatic protection device according to the embodiment of the present invention and the magnitude of crosstalk noise, and the relationship between the parasitic NPN transistor Q11 of the conventional electrostatic protection device and the magnitude of crosstalk noise. It is a figure showing a relation.

FIG. 4 is a modified example of the configuration of the electrostatic protection device in the case where the electrostatic protection device according to the embodiment of the present invention is applied to latch-up measures.

5 is an equivalent circuit diagram of the electrostatic protection device shown in FIG.

6 is a diagram showing a latch-up tolerance of the electrostatic protection device of FIG. 4 and a latch-up tolerance of a conventional electrostatic protection device.

FIG. 7 is a modification of the configuration of the electrostatic protection device.

FIG. 8 is an equivalent circuit diagram when the electrostatic protection device of the present invention is applied to a logic inverter circuit.

FIG. 9 is an equivalent circuit diagram when the electrostatic protection device of the present invention is applied to a current mirror circuit.

FIG. 10 is a diagram illustrating a configuration of a semiconductor device.

FIG. 11 is a diagram illustrating a configuration of a conventional electrostatic protection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Drain N well 12, 13, 14, 16 N type diffusion layer 15 P well 17 Guard ring N well 18 Ground N well Q1-Q12 Parasitic NPN transistor 41 Circuit to be protected 42a Positive polarity electrostatic protection circuit 42b Negative polarity static Protection circuit

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 15, 1999 (1999.11.
15)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

3. The electrostatic protection device according to claim 2 , wherein the first region of the second conductivity type is formed at a depth equal to or greater than the depth of the well.

Wherein said well and said first region and said deep region, the base of the parasitic bipolar transistor to form the emitter, a collector, the emitter and collector of the parasitic transistor, it is formed adjacent The electrostatic protection device for a semiconductor device according to claim 1, 2, or 3.

8. The device according to claim 8, wherein the deep region and the guard ring are close to each other.
8. The collector according to claim 1 , wherein the collector of the raw bipolar transistor is formed.
ESD protection device for semiconductor devices.

9. An electrostatic protection device comprising: two electrostatic protection devices; a positive voltage applied to a first region of one of the electrostatic protection devices;
Negative voltage noise in the first area of the electrostatic protection device
When applied, the parasitic bipolar transistor
From the first area of one electrostatic protection device to the other.
Suppressing the current flowing through the first region of the protection device, claimed in any one of claims 1 to 8, characterized in
ESD protection device for semiconductor devices.

13. A plurality of said electrostatic protection devices are arranged,
A positive voltage is applied to the electrostatic protection terminal of the electrostatic protection device.
The negative voltage is applied to the electrostatic protection terminal of another electrostatic protection device.
Is applied, the well, the drain, the deep region and the gar
The dring forms a base, emitter, and collector.
The resulting parasitic bipolar transistor turns on.
From the ESD protection terminal of one ESD protection device.
13. The device according to claim 10, 11 or 12, wherein a current flowing through an electrostatic protection terminal of the protection device is suppressed.
Electrostatic protection device for conductor devices.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0002

[Correction method] Change

[Correction contents]

[0002]

2. Description of the Related Art As shown in FIG. 10, a semiconductor device includes an electrostatic protection device 42 for preventing a circuit (internal circuit) 41 to be protected from being electrostatically damaged by noise applied to an input terminal. . The electrostatic protection device 42 prevents the positive polarity noise applied to the input terminal from being input to the internal circuit, and the electrostatic protection device 42a prevents the negative polarity noise from being input to the internal circuit. For protection from static electricity.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

As shown in FIG. 11, for example, the electrostatic protection device 42a is formed near the drain N well 11 with the drain N well 11 formed on the upper surface of the P-type semiconductor substrate 1 as a drain. An N-channel MOS transistor having the N-type diffusion layer 13 as a source is provided.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

A guard ring N-well 17 having an N-type diffusion layer 16 is formed around the NMOS transistor having the above structure. The power supply voltage VDD is applied to the guard ring N well 17.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

In the electrostatic protection device 42a having the above structure,
When a positive voltage due to noise is applied to the input terminals T (T1, T2), the potential of the drain N well 11 functioning as the drain of the N-channel MOS transistor is higher than the potential of the N-type diffusion layer 13 functioning as the source. Become. Thus, a current flows in the forward direction of the NMOS transistor, and a positive polarity noise current can be prevented from flowing to the internal circuit.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

On the other hand, when a negative polarity voltage due to noise is applied to the input terminal T (eg, T1), the electrostatic protection device 42b operates and a negative polarity noise current flows from the input terminal T1 to the internal circuit. Can be prevented.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

However, in this case, a negative voltage is input to the electrostatic protection device 42a until the electrostatic protection device 42b operates and the potential of the input terminal T1 returns to an appropriate value. Therefore, a parasitic NPN transistor Q12 having the drain N well 11 connected to the input terminal T2 as a collector, the drain N well connected to the input terminal T1 as an emitter, and the region 18 as a base is formed.
In some cases, current was drawn from the input terminal T2. Therefore, crosstalk noise may occur at the input terminal T2.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

Note that the guard ring N-well 17 is provided in the electrostatic protection device 42a having the above configuration. As a result, a parasitic NPN transistor Q11 having the P well 15 as a base, the drain N well 11 connected to the input terminal T1 as an emitter, and the guard ring N well 17 as a collector is formed. Therefore, the input terminal T
When a negative polarity noise voltage is applied to 1, a combined current obtained by combining the current from the parasitic NPN transistor Q11 and the current from the parasitic NPN transistor Q12 substantially flows from the drain N well 11 to the input terminal T1.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

Further, by increasing the base width of the parasitic NPN transistor Q12 (enlarging the formation area of the P region 18 ), the current amplification factor of the parasitic NPN transistor Q12 is sufficiently reduced, and the crosstalk generated at the input terminal T2 is reduced. It is possible to reduce noise. But,
Increasing the base width of the parasitic NPN transistor Q12 increases the area used for the base, so that the electrostatic protection circuit
In some cases, the road 42 becomes large and the cost increases.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

[0017]

In order to achieve the above object, an electrostatic protection device for a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate of a first conductivity type and a semiconductor substrate formed on one surface of the semiconductor substrate. A well of the first conductivity type, a first region of the second conductivity type formed in the well and connected to a terminal of a circuit to be protected, and a first voltage formed in the well and applied with the first voltage. A second region of a second conductivity type, a guard ring of a second conductivity type formed so as to surround the well, and formed in the semiconductor substrate, contacting a deep portion of the guard ring, And a deep region of the second conductivity type formed adjacently without contacting the region of the first conductivity type.
The first region is formed at a depth equal to or greater than the depth of the well.
It is characterized by having.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

According to this configuration, there is provided a deep region of the second conductivity type formed in contact with the deep portion of the guard ring and without being in contact with the first region. Therefore, a parasitic bipolar transistor in which the well, the first region, and the deep region form a base, an emitter, and a collector, respectively, has a sufficiently large current amplification factor and a sufficiently large outflow of current. For this reason, for example, when there is another parasitic bipolar transistor having the first region as an emitter, the outflow amount of the current flowing through the other parasitic bipolar transistor becomes relatively small. Therefore, for example, when the collector of another parasitic bipolar transistor is connected to another terminal of the circuit to be protected, the amount of current drawn from the collector by the other transistor is reduced, and cross-current generated at the other terminal is reduced. Talk noise can be reduced. Also,
The rate at which other parasitic bipolar transistors are turned on is reduced, and defects such as latch-up and malfunction can be reduced.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

A semiconductor device according to a second aspect of the present invention.
The static electricity protection device includes a first conductivity type semiconductor substrate,
A first conductivity type well formed on one surface of the semiconductor substrate;
Formed in the well and connected to the terminals of the circuit to be protected
A first region of a second conductivity type, formed in the well, and
And a first voltage is applied to the second region of the second conductivity type.
And a second conductivity type gas formed so as to surround the well.
And a guard ring formed in the semiconductor substrate.
Touching the deep part of the dring, not touching the first area
A deep region of the second conductivity type formed adjacent to
The first area and the second area are respectively
Form the source or drain of a field effect transistor
It is characterized by that. Note that, since the deep region is formed adjacent to the first region, the first region is desirably formed at a depth equal to or greater than the depth of the well.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

Further, a plurality of circuits to be protected and a plurality of electrostatic protection devices may be formed on the semiconductor substrate, and each of the electrostatic protection devices is connected to the circuit to be protected in the first region. Is also good. The deep region and the guard ring,
For example, forming the collector of a parasitic bipolar transistor
I do. Also, two or more electrostatic protection devices are arranged,
Voltage in the first region of the static electricity protection device of
Negative voltage noise is applied to the first area of the protection device
When done, by the parasitic bipolar transistor,
From the first area of one electrostatic protection device to the other electrostatic protection device
Is configured to suppress the current flowing through the first region of the device.
Is also good. Further, a semiconductor according to a third aspect of the present invention
The electrostatic protection device of the device includes a semiconductor substrate of the first conductivity type,
A first conductivity type well formed in the semiconductor substrate;
The second conductor formed in the well and connected to the electrostatic protection terminal
A drain comprising a first region of an electrical conductivity type;
Formed of a second region of the second conductivity type
A source and a well formed in the well,
A diffusion layer of a first conductivity type to be a bell;
Second conductive type guard ring formed to surround the well
And a deep part in the well or from the well
Is formed in a deep part and is in contact with the deep part of the guard ring.
Formed in contact with and in close contact with the drain region
A second conductive type deep region.
You. The drain is deeper than the well, for example.
Is done. The well, the drain, and the guard
The ring and the deep region are, for example, parasitic bipolar
Transistor base, emitter and collector
And forming an emitter and a collector of the parasitic transistor.
Are formed adjacent to each other. Further, the electrostatic protection device
Are placed on the ESD protection terminal of one ESD protection device.
Polarity voltage is applied to protect electrostatic protection of other electrostatic protection devices
When a negative voltage is applied to the terminal, the well and
The drain, the deep region and the guard ring,
Parasitic via formed as base, emitter and collector
When the polar transistor is turned on, one electrostatic protection
From the ESD protection terminal of the ESD protection device.
The current flowing to the protection terminal may be suppressed.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

In the electrostatic protection device having the above configuration, as shown in FIG. 2, the drain N connected to the input terminal T1
A parasitic NPN transistor Q1 having the well 11 as an emitter, the P well 15 as a base, and the deep N well 10 connected to the guard ring N well 17 as a collector.
Is formed. Further, a parasitic NPN transistor Q2 is formed in which the drain N well 11 connected to the input terminal T2 is a collector, the P region 18 is a base, and the drain N well 11 connected to the input terminal T1 is a collector. The drain N well 11 and the P well 1
Each of the N-type diffusion layers 13 formed in the
The drain and the source of the MOS transistor are formed.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] Explanation of sign

[Correction method] Change

[Correction contents]

[Description of Signs] 11 Drain N well 12, 13 , 16 N type diffusion layer 14 P type diffusion layer 15 P well 17 Guard ring N well Q1 to Q12 Parasitic NPN transistor 41 Circuit to be protected

[Procedure amendment 16]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

[Procedure amendment 17]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 10

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takayoshi Fujishiro 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term (reference) in NEC Ic Microcomputer System Co., Ltd. 5F038 BH04 BH06 BH07 BH09 BH13 BH18 CA09 EZ01 EZ13 EZ14 EZ20 5F048 AA03 AB04 BA01 BE02 BE03 BE05 BH05 CC06 CC08 CC10 CC13 CC19

Claims (7)

[Claims] A first conductive type semiconductor substrate; a first conductive type well formed on one surface of the semiconductor substrate; and a second conductive type formed in the well and connected to a terminal of a circuit to be protected. A first region of a mold, a second region of a second conductivity type formed in the well and to which a first voltage is applied, and a guard ring of a second conductivity type formed to surround the well. A second conductive type deep region formed in the semiconductor substrate, in contact with a deep portion of the guard ring, and formed adjacently without contacting the first region. Protection device for semiconductor devices. 2. The device according to claim 1, wherein the first region is formed at a depth equal to or greater than the depth of the well. 3. The well, the first region, and the deep region form a base, an emitter, and a collector of a parasitic bipolar transistor, and the emitter and the collector of the parasitic transistor are formed adjacent to each other. The electrostatic protection device for a semiconductor device according to claim 1, wherein: 4. The device according to claim 1, wherein the first region and the second region form a source or a drain of a field-effect transistor, respectively. . 5. When a voltage of a first polarity is applied to an input terminal of the circuit to be protected, a current is caused to flow through the field-effect transistor to reduce the voltage. Applying a current through a parasitic transistor having the deep region and the guard ring as a collector, the well as a base, and the first region as an emitter when the voltage is applied, thereby reducing the voltage. The electrostatic protection device for a semiconductor device according to claim 3, wherein: 6. The semiconductor device according to claim 1, further comprising a third region of a first conductivity type formed in said well and to which a second voltage for biasing said well is applied. The electrostatic protection device for a semiconductor device according to claim 1. 7. A plurality of circuits to be protected and a plurality of electrostatic protection devices are formed on the semiconductor substrate, and each of the plurality of electrostatic protection devices is connected to the circuit to be protected in the first region. The electrostatic protection device for a semiconductor device according to claim 1, wherein: