JPH08330431A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To shorten the test time of a semiconductor integrated circuit with digital and analog macrocells, by making the tests of all its digital circuits including its user logic possible. CONSTITUTION: The figure shows the connections of the whole of an IC when an analog-to-digital converter is used as its analog macrocell. In the IC comprising a plurality of digital macrocells 4, 5, a user logic 2 and an A/D converter macrocell 3, all the cells other than the A/D macrocell 3 are kept in ordinary operation states, and a test terminal (TEST3) of the A/D macrocell 3 is brought into a high level, and further, a digital-data outputting terminal 302 of the A/D macrocell 3 is set to the state wherein from a terminal (ATBUS) connected with the external terminal of the IC, digital data signals are inputted directly to the terminal 302. Thereby, the tests of all the digital circuits other than the A/D converter macrocell are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell-based IC equipped with an analog macro, and more particularly to a test method thereof.

[0002]

2. Description of the Related Art An IC 1 using a conventional macro cell has a user logic 2, an A / D macro cell 3, a macro cell 4 and a macro cell 5 as shown in FIG. The macro cells 4 and 5 are macros having digital functions such as cpu, memory, and multiplier.

An IC formed by combining several function blocks in this way is called a cell-based IC.
Generally, in such a cell-based IC, the operation of the entire IC is tested, and at the same time, the test is performed for each function block. As shown in FIG. 8, the microcells 4 and 5 include input / output signal terminals (BUS) 401 and 405, output dedicated terminals (OUT) 402 and 502, input dedicated terminals (IN) 403 and 503, and test input / output terminals (TBU).
S) 404, 504, test mode control terminal (TES
T1, TEST2) 405, 505, 406, 506. FIG. 9 shows a truth table of the test mode.

The test mode control terminal TEST1 is LO
When W, the macro cell is in a normal operation state, and all terminals other than those for testing are in a valid state. TEST1 is HIGH
At this time, the macro cell is switched to the test mode state, all the terminals other than those for the test are invalid, and are disconnected from other circuits (except the analog terminal). In this state, when the other test mode control signal TEST2 is LOW,
Although the macro cell is also disconnected from the test input / output bus, when TEST2 is HIGH, the test input / output bus (TBUS) is valid and the macro cell is connected to the external terminal 10
It is possible to test as a single unit through 4. Similarly, in the A / D macro cell 3, the A / D converter can input an analog signal from the external terminal 101 and test the A / D converter alone via the test input / output bus.

FIG. 10 shows an IC connection when the D / A converter macro 6 is used as an analog macro. When the analog macro is a D / A converter, the analog input AIN in the A / D converter is eliminated, but an analog output AO is used.
The UT is connected to the external terminal 101. Each test mode can be performed in exactly the same manner as the A / D macro.

[0006]

Since this conventional cell-based IC includes the analog macro cell, when a defect occurs, it is determined whether the defective portion is caused by the analog macro or the user logic. Could not be identified without the test. For this reason,
There is a problem that the time required for the test becomes very long. Further, when specifying a defective portion, there is a problem that analysis is difficult because an input or output signal includes an analog signal.

In order to solve this problem, the present invention makes it possible to test the entire digital section of the IC except the analog macro.

In the cell-based IC, the macrocells are combined to form the IC, but it is necessary to shorten the period from the design to the IC as much as possible. For this reason,
It was necessary to standardize the design flow by shortening the design period by making the test mode of the entire digital section excluding the above analog macro as standard in each macro.

[0009]

A semiconductor integrated circuit according to the present invention comprises a plurality of digital macro cells, a user logic circuit, and an analog-digital conversion macro cell,
The A / D conversion result output signal of the A / D conversion macro cell is directly input from an external input terminal without passing through the A / D conversion macro cell, and the plurality of digital macro cells except the A / D conversion macro cell and the user. It has a mode for testing the operation of the logic circuit.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 shows a cell base I of an embodiment of the present invention.
It is a block diagram of C.

The difference between this embodiment and the conventional example (FIG. 8) is A /
Since only the D macrocell 3 and the terminals 107 and 108 of the entire IC are provided, the description of the overlapping parts of the conventional example will be omitted. A /
The D macro cell 3 has a third test mode control terminal (TEST3) 307, which is different from the A / D macro cell of the conventional example.
And a second test input / output terminal (ATBUS) 308 is added. The input / output terminal 308 is an input-only terminal for the A / D macro.

FIG. 2 shows a truth table of the test mode.

There are four test modes in total (including the actual use state).

When both TEST1 and TEST3 are 0, it is in actual use, TBUS is high impedance, AT
BUS becomes invalid. When TEST1 is 1 and TEST2 is 1, all macro cells including the A / D macro are disconnected from the peripheral circuit, and the A / D converter macro unit is tested on the test bus (TB
It becomes possible to test using US).

When TEST1 is 1 and TEST2 is 0,
All the macro cells are separated from the surroundings, and the macro cells whose TEST2 is 1 can perform the macro unit test via the test bus (TBUS). The above mode is the conventional macro cell test mode.

When TEST1 is 0 and TEST3 is 1, A
All logic circuits except the / D converter macro cell are in the test state. At this time, all analog terminals of the A / D macro cell are invalid, and the ATB directly connected to the output of the A / D.
US and the digital input / output terminal normally used become effective.

3 to 6 show the connection states of the circuits in each mode.

FIG. 7 shows a second embodiment of the present invention. Figure 7
Is the case where the analog macro is a D / A converter in the first embodiment. In this case, the analog output terminal AOUT of the D / A macro cell 6 is A / A in the first embodiment.
Although it is in a state of being replaced with the analog input terminal AIN of the D macro cell 3, all the test modes can be performed in exactly the same manner except that point. However, in this case ATB
US is used not as an input terminal but as a terminal for directly outputting the input data of the D / A converter.

[0020]

As described above, according to the present invention, in the cell-based IC in which the analog macro cell is mounted in addition to the digital macro cell and the user logic, a mode for testing all digital circuits except the analog macro cell is realized. When a defect occurs in the IC, it is possible to identify whether the defective portion is in the digital circuit or the analog circuit.

As a result, the test, which has conventionally required the test including the analog test, is first performed only by the entire digital section to immediately determine whether the defect is digital or analog, thereby significantly reducing the test time. Can be performed. In addition, since the circuit including the user logic can be observed only in the digital section, the failure mode can be specified when the user logic has a failure by the digital test, which has an effect of simplifying the failure analysis.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a truth table of a test mode according to the first embodiment.

FIG. 3 is a connection diagram of the first embodiment in a normal operation state.

FIG. 4 is a connection diagram of an analog macro unit test state of the first embodiment.

FIG. 5 is a connection diagram of a digital macrocell unit test state of the first embodiment.

FIG. 6 is a connection diagram of the entire digital unit test state of the first embodiment.

FIG. 7 is a second embodiment of the present invention.

FIG. 8 is a conventional example 1.

FIG. 9 is a truth table of a test mode of a conventional example.

FIG. 10 shows Conventional Example 2.

[Explanation of symbols]

1 IC whole 2 User logic 3 A / D macro cell 4,5 Macro cell 6 D / A macro cell 101 to 108 IC external terminal 201 Input terminal to user logic circuit from outside IC (INEX) 202 IC external from user logic circuit Output terminal (OUTEXT) 203, 206, 208, 303, 403, 503
Digital input terminal of each block (IN, IN1, IN
2, IN3) 204, 207, 209, 302, 402, 502
Digital output terminals of each block (OUT, OUT1, O
UT2, OUT3) 205, 401, 501 Bus terminals normally used inside the IC (BUS) 301 A / D macrocell analog input signal terminals (AIN) 304, 404, 504 Test buses connected to the inside and outside of the IC Terminal (TBUS) 305, 306, 307.405, 505, 506
Test mode setting terminals (TEST1, TEST2, T
EST3) 308 Digital input or digital output terminal (ATBUS) 309 D / A macro analog signal output terminal when testing the entire logic circuit

Claims (4)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of digital macro cells, a user logic circuit, and an analog-digital conversion macro cell, wherein an A-D conversion result output signal of the A-D conversion macro cell is converted into the A-D conversion macro cell. A semiconductor integrated circuit having a mode in which an operation is performed by directly inputting from an external input terminal without passing through the user logic circuit and the plurality of digital macrocells except the A-D conversion macrocell. 2. The A-D conversion macro cell according to claim 1, wherein the D-A conversion macro cell is a D-A conversion macro cell, and a D-A conversion input signal of the D-A conversion macro cell does not pass through the D-A conversion macro cell but an external output terminal. A semiconductor integrated circuit having a mode of directly outputting to a plurality of digital macros and testing the operations of the plurality of digital macros and the user logic circuit except the DA conversion macrocell. 3. The semiconductor integrated circuit according to claim 1, wherein the A-D conversion macrocell is replaced with an analog macrocell having a function of inputting an analog signal, processing the analog signal, and then converting the analog signal into a digital signal. 4. The semiconductor integrated circuit according to claim 2, wherein the D-A conversion macro cell is replaced with an analog macro cell having a function of analog signal processing of an output signal obtained by converting a digital signal into an analog signal.