JP2939275B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when used in a complementary BiCMOS circuit included in a semiconductor integrated circuit device.

[Conventional technology]

BiCMOS circuits are designed to take advantage of the low power consumption of CMOS (complementary MOS) while using the high current drive capability of bipolar transistors to improve the delay time with large capacitance loads, which is a drawback of CMOS circuits. is there.

U.S. Pat. No. 3,541,353 discloses an example in which a bipolar transistor is constituted by a complementary push-pull circuit comprising an npn transistor and a pnp transistor. Japanese Patent Application Laid-Open No. 56-100461 discloses a MOSFET (insulated gate type field effect). An example is shown in which a transistor and a bipolar transistor are integrally formed.

[Problems to be solved by the invention]

In the above prior art, no consideration is given to speeding up the operation from a light load region to a heavy load region. For example, in the circuit described in U.S. Pat. No. 3,541,353, since a complementary push-pull circuit has an input offset, an area where a bipolar transistor cannot be driven occurs as described later, and the operation is delayed.

In the circuit described in JP-A-56-100461, the operation speed of the bipolar transistor is reduced because there is no circuit for extracting the base charge for turning off the bipolar transistor at high speed. Therefore, as shown in FIG. 7, when a totem-pole type output circuit is used, the base of the bipolar transistor on the power supply voltage side is connected to the base current supply path of the p-channel MOSFET and the current of the n-channel MOSFET. It is necessary to provide a drawing path. The bipolar transistor on the ground potential side has an n-channel MOSF for extraction between its base and emitter.
An ET is provided. When a totem-pole type output circuit is used as described above, a circuit for extracting the base charge of the bipolar transistor is required for high-speed operation, and the number of elements and the occupied area corresponding to the circuit are increased.

In general, when the load is large, the BiCMOS circuit can make use of the high driving capability of the bipolar transistor to increase the speed. However, since the BiCMOS circuit has a two-stage configuration including a CMOS circuit portion and a bipolar output circuit, the operation speed is lower than that of the CMOS circuit when the load is light.

An object of the present invention is to provide a semiconductor integrated circuit device including a BiCMOS circuit that achieves high-speed operation from a light load region to a heavy load region while achieving high integration.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

A typical embodiment of the invention disclosed in the present invention is a CMOS circuit including a p-channel MOSFET (Q2) receiving an input signal (IN) and an n-channel MOSFET (Q1); Level shift constant voltage elements (D2, D1) connected between the drain of the MOSFET (Q2) and the drain of the n-channel MOSFET (Q1)
And a complementary push-pull npn transistor (T2) having an emitter follower output type receiving at its base the drain output of the p-channel MOSFET (Q2) and the drain output of the n-channel MOSFET (Q1) of the CMOS circuit. And a pnp transistor (T1). The n-channel MOSFET (Q1) has an n-type source region formed on the p-type substrate with a p-type region forming a collector region of the pnp transistor (T1) as a p-type substrate. And an n-type drain region. The n-type drain region and the n-type base region of the pnp transistor are integrally formed. The p-channel MOSFET (Q2) forms the collector region of the npn transistor (T2). An n-type substrate to be formed has an n-type substrate, and has a p-type source region and a p-type drain region formed on the n-type substrate. The p-type drain region and the p-type base region of the npn transistor are integrally formed. Wherein the other (D2) of the level-shifting constant-voltage element is formed by a Schottky diode formed by contact between the p-type base region and a metal (see FIGS. 1 and 2). ).

[Action]

According to the above-described means, the input offset voltage in the complementary ripple-pull circuit using the bipolar transistor can be reduced by inserting the constant-voltage element for level shift, and the bipolar transistor can be quickly operated in response to a change in the output signal formed in the CMOS circuit. Can switch. Further, since the bipolar transistor, the MOSFET, and the Schottky diode as the constant current element can be integrally formed, high integration is possible.

〔Example〕

FIG. 1 is a circuit diagram showing a basic embodiment of a BiCMOS circuit according to the present invention. Each circuit element in FIG.
Although it is not particularly limited by a known semiconductor integrated circuit manufacturing technique, it is formed on one semiconductor substrate such as single crystal silicon.

In this embodiment, the pnp transistor T1 and the npn transistor T2 are connected in a complementary push-pull form,
It is used as an output circuit. That is, the collector of the pnp transistor T1 is connected to the ground potential point Vss of the circuit, and the emitter is connected to the emitter of the npn transistor T2. Then, the collector of the npn transistor T2 is connected to a power supply voltage Vdd such as about +5 V, although not particularly limited.

If such a complementary push-pull output circuit is directly driven by a CMOS circuit as in the past, the pn
The base-emitter voltage V _{BE of} each of the p-transistor T1 and the npn-transistor T2 becomes an input offset voltage, resulting in a region where the bipolar transistor cannot be driven, as shown in FIG.

Therefore, in this embodiment, between the bases of the pnp transistor T1 and the npn transistor T2, in other words, the CMOS
N-channel MOSFET Q1 and p-channel MO that make up the circuit
Diodes D1 and D2 are provided between the drains of SFET Q2 as constant current elements for performing a level shift operation. Although not particularly limited, as described later, in order to realize high integration of the circuit, the diodes D1 and D2 are Schottky diodes configured using the respective base regions of the pnp transistor T1 and the npn transistor T2. It can also be used.

In this configuration, the n-channel MOSFET Q1 and p-channel
The MOSFET Q2 also serves as a circuit for extracting the base charges of the bipolar transistors T1 and T2. That is, the input terminal
When the IN input signal changes from the low level to the high level, the n-channel MOSFET Q1 changes from the off state to the on state, extracts the base charge of the npn transistor T2 to be turned off, and allows the base current to flow through the pnp transistor T1 To do. Conversely, when the input signal at the input terminal IN changes from the high level to the low level, the p-channel MOSFET Q2 changes from the off state to the on state, and the base charge of the pnp transistor T1 to be turned off is extracted, and the npn transistor T2 The base current is allowed to flow through.

Further, by adopting the emitter follower output format, the parasitic capacitance at the output terminal OUT can be reduced. That is, in a complementary push-pull circuit that takes an emitter follower output format, the pnp transistor T1
Is connected to the collector ground, so that a relatively large collector parasitic capacitance generated between itself and the substrate as in the totem-pole type output circuit shown in FIG. 7 can be prevented from being connected to the output terminal.

FIG. 2 shows one of the BiCMOS circuits shown in FIG.
An element structure sectional view of an embodiment of the n-channel MOSFET Q1, the pnp transistor T1, and the diode D1 is shown, and FIG. 3 is a pattern diagram thereof.

An n-channel MOSFET Q1 is formed using a p-type region constituting a collector region of the pnp transistor T1. That is, the n-channel MOSFET Q1 has an n ⁺ -type source (source) and a drain (drai) on the surface of the collector region composed of a p-type epitaxial growth layer (epi layer).
n), and a gate electrode is formed on the surface of the channel region interposed between the source and the drain via a thin gate insulating film. The n ⁺ -type drain is integrally formed with the n-type base region forming the pnp transistor T1, and a connection is made between the drain of the MOSFET Q1 and the base of the transistor T1.

A Schottky diode D1 is formed on the surface of the base region of the pnp transistor T1 by contacting a metal that also serves as a base electrode. In this manner, the MOSFET Q1, the bipolar transistor T1, and the diode D1 can be configured with a composite device structure. Although not shown, the source of MOSFET Q1 and
The collector of transistor T1 is connected to ground potential Vss.

The p-channel MOSFET Q2, the npn transistor, and the diode D2 can be similarly formed by reversing the conductivity type of the composite device structure.

Next, the reason why it is possible to increase the speed to a low load in the circuit of this embodiment will be described.

When a complementary push-pull output circuit is driven directly by a CMOS circuit as in the prior art, the output voltage of the bipolar transistor at the high level is equal to the power supply voltage Vdd as shown in the operation waveform diagram of FIG. from the base, it is only lowered potential emitter voltage V _bE, the output voltage of the bipolar transistor at the time of the low level is the base with respect to the ground potential, it went up only emitter voltage V _bE potential. For this reason, when the output signal is changed from the high level to the low level, the lower (ground potential side) pn
In order to turn on the p-transistor T1, the potential of the base is further higher than the potential at the time of high level output (Vdd-V _BE ). When the output signal needs to be reduced from the low level to the high level by the emitter-to-emitter voltage V _BE voltage, the base potential is set to the low-level output potential (in order to turn on the upper (power supply voltage side) npn transistor T2). It is necessary to raise the base-emitter voltage V _BE voltage higher than V _BE ). As described above, in a circuit in which a complementary push-pull circuit is directly driven by a CMOS circuit, a region in which a bipolar transistor cannot be driven by an output signal of the CMOS circuit occurs, and a MOS transistor (MOS transistor)
A delay occurs between the drain-drain voltage of the FET and the output voltage of the bipolar transistor.

However, in the circuit in which the diodes D1 and D2 are added as in the circuit of the embodiment shown in FIG. 1, since there is no discharge path for the charges charged in the forward direction of the diodes D1 and D2, the bipolar transistors T1 and T2 The forward voltage of the diodes D1 and D2 is always applied as a forward bias voltage between the base and the emitter. Thus, the time required for the bipolar transistor to transition from the off state to the on state can be reduced. That is, as shown in FIG. 4 (b), the forward voltage of the diodes D1 and D2 greatly reduces the charge / discharge time between the base and the emitter of the transistors T1 and T2.
There is almost no delay between the drain voltage of the channel MOS transistor and the drain voltage of the n-channel MOS transistor and the output voltage of the bipolar transistor.

FIGS. 5 (a) and 5 (b) and FIGS. 6 (a) and 6 (b)
MOSFET having a gate length of 1 μm and a gate width of 1 μm and f _T =
Npn transistors 16 GHz, using a pnp transistor of f _T = 6 GHz, CMOS circuits, conventional Bi as shown in FIG. 7
CMOS circuit, complementary BiCMOS circuit without diode, complementary type with diode shown in Fig. 1.
The simulation results of each of the BiCMOS circuits are shown.

FIG. 5 (a) shows a load capacity-delay time characteristic diagram at a low load.

In the figure, x indicates a normal BiCMOS circuit, and o indicates CM.
Indicates OS circuit, □ is complementary type without diode
The figure shows a BiCMOS circuit, and the open square shows a complementary BiCMOS circuit when a diode is connected. As shown in the figure, it can be seen that the complementary BiCMOS circuit according to this embodiment has the highest speed even when the load capacitance is as low as 0 to 100 fF.

FIG. 5 (b) shows a load capacity-delay time characteristic diagram under a high load.

Also in the same figure, × indicates a normal BiCMOS circuit, ○ indicates a CMOS circuit, □ indicates a complementary BiCMOS circuit without a diode, and Δ indicates a complementary BiCMOS circuit with a diode connected. Is shown. As shown in the figure, even when the load capacity is as high as 0 to 4 pF, the speed of the complementary BiCMOS circuit according to this embodiment is the highest. As described above, the complementary BiCM according to the present invention is provided.
It can be seen that the OS circuit operates at high speed under any load from low load to high load.

FIG. 6 (a) shows a load capacity-energy consumption characteristic under a low load, and FIG. 6 (b) shows a load capacity-energy consumption characteristic under a high load.

In this figure, as in the case of FIG.
Indicates a BiCMOS circuit, ○ indicates a CMOS circuit, □ indicates a complementary BiCMOS circuit without a diode, and Δ indicates a complementary BiCMOS circuit with a diode connected. Energy (power multiplied by the operating frequency multiplied by this value) is examined in relation to load capacity. In the region where the load capacitance is small, the CMOS circuit has the lowest power consumption as shown in FIG. 4A, but in the region where the load capacitance is large about 0.2 pF or more, a diode is connected as shown in FIG. Complementary BiCMOS
The circuit has the lowest power consumption.

In this way, by using the composite structure for the BiCMOS circuit, it is possible to reduce the area increase compared to the CMOS circuit, and to add a diode to the base compared to the conventional BiCMOS circuit using a totem-pole type output circuit. 30%, 3.5fF at no load
Circuit simulations have shown that the delay time can be reduced by about 20% under load. In terms of power consumption, it became clear that when the load capacitance became 200 fF or more, it became lower than that of the CMOS circuit.

The operational effects obtained from the above embodiment are as follows. That is, (1) a level shift diode is provided between the drains of the p-channel MOSFET and the n-channel MOSFET constituting the CMOS circuit to drive the complementary push-pull npn and pnp transistors of the emitter follower output type. As a result, the input offset voltage in the complementary push-pull circuit using bipolar transistors can be reduced, and the bipolar transistors can be switched at high speed in response to changes in the output signal formed by the CMOS circuit, resulting in an effect that higher speed can be achieved. Can be

(2) The CMOS circuit also serves as a circuit for extracting complementary push-pull output transistors, so the number of circuit elements can be reduced, and bipolar transistors and MOSFETs can be used.
In addition, since the semiconductor device and the Schottky diode can be integrally formed as a composite device structure, an effect of enabling high integration can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. Nor. For example, the CMOS circuit side
It may have a NOR (Nor) gate configuration or a NAND (Nand) gate configuration. That is, in FIG.
n-channel MOSFET in parallel with n-channel MOSFET Q1
And a p-channel MOSFET may be connected in series with the p-channel MOSFET to form a NOR gate.
Connect n-channel MOSFET in series with p-channel MOSFET Q1 and p-channel in parallel with p-channel MOSFET
A MOSFET may be connected to form a NAND gate. Also,
Diodes are schottky diodes as described above, PN junction diodes and MOS connected in diode form
A transistor may be used. The type and number of diodes provided between the bases of the complementary push-pull transistors are determined so that both transistors are constantly turned on so that a steady DC current does not flow between the power supply voltage Vdd and the ground potential of the circuit. transistor base, as long as it forms a small bias voltage than the voltage of the sum of the emitter voltage V _bE.

The device structure for realizing the phase capture type BiCMOS circuit as shown in FIG. 1 can adopt various embodiments other than the composite device structure as shown in FIG. 2 and FIG. is there.

The present invention can be widely used for various semiconductor integrated circuit devices including a BiCMOS circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. In other words, the p-channel MOSFET that composes the CMOS circuit
By providing a diode for level shift between the drain of the NMOS and the n-channel MOSFET and driving the complementary push-pull type npn transistor and pnp transistor of the emitter follower output type, the input in the complementary push-pull circuit by the bipolar transistor is provided. Since the offset voltage can be reduced and the bipolar transistor can be switched at a high speed in response to a change in the output signal formed by the CMOS circuit, the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic embodiment of a complementary BiCMOS circuit according to the present invention. FIG. 2 is a circuit diagram showing an n-channel MOSFET Q1, a pnp transistor T1, and a diode of the BiCMOS circuit shown in FIG. D
1 is an element structure sectional view showing one embodiment, FIG. 3 is a corresponding pattern diagram, FIGS. 4 (a) and (b) are output waveform diagrams for explaining the present invention, FIG. 5 ( 6 (a) and 6 (b) are load capacitance and delay time characteristic diagrams for explaining the present invention; FIGS. 6 (a) and 6 (b) are load capacitance and energy consumption characteristic diagrams for explaining the present invention; FIG. 7 shows a Bi using a conventional totem-pole type output circuit.
FIG. 2 is a circuit diagram illustrating an example of a CMOS circuit. Q1, Q2 ... MOSFET, T1, T2 ... Bipolar transistor,
D1, D2: Diode, IN: Input terminal, OUT: Output terminal, source: Source, gate: Gate, drain: Drain, emitter: Collector, collector: Collector, base: Schottky diode …… Schottky diode

────────────────────────────────────────────────── (5) References JP-A-59-196625 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/06

Claims (1)

(57) [Claims] A p-channel MOSFET receiving an input signal and n
A CMOS circuit comprising a channel MOSFET; a level shift constant voltage element connected between a drain of the p-channel MOSFET and a drain of the n-channel MOSFET of the CMOS circuit; and the p-channel MOSFET of the CMOS circuit. Complementary push-pull npn transistor and pnp with emitter follower output type receiving the drain output of the n-channel MOSFET and the drain output of the n-channel MOSFET respectively at the base
Wherein the n-channel MOSFET has an n-type source region and an n-type drain region formed on the p-type substrate with a p-type region forming the collector region of the pnp transistor as a p-type substrate. n-type drain region and n of the pnp transistor
The n-type base region is integrally formed, and one of the level shift constant voltage elements is formed by a Schottky diode by contact of the n-type base region with a metal. The p-channel MOSFET is a collector region of the npn transistor. A p-type source region and a p-type drain region formed on the n-type substrate with the n-type region forming the n-type substrate as an n-type substrate.
A semiconductor integrated circuit device, wherein a mold base region is integrally formed, and the other of the level shift constant voltage elements is formed by a Schottky diode formed by contact of the p-type base region with a metal.