JPH0653450A - Master slice mode semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To allow response to a plurality of signal levels without substantially depending on a level conversion circuit by employing unit cells having specific structures. CONSTITUTION:Each of unit cells 101-104 arranged in lattice on a semiconductor substrate comprises a P-well 6 isolated electrically from a substrate and an n-well 2 isolated from the P-well 6. The P-well 6 and the n-well 2 in a unit cell are formed while being isolated from a corresponding well in an adjacent unit cell. A P-channel MOSFET and an n-channel MOSFET are formed in the n-well 2 and the P-well 6 of each of the unit cells 101-104. Power supply wirings 21, 24 and ground potential wirings 22, 23 are formed individually in the direction crossing perpendicularly with the gate electrodes 3, 7 each of the P-channel MOSFET and n-channel MOSFET. This constitution allows driving of each unit cell with a signal having different voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (IC).
More particularly, the present invention relates to a master slice-type large-scale IC device in which basic cells corresponding to memory cells such as NAND gates and NOR circuits and memory cells such as SRAMs are arranged in a grid pattern in both horizontal and vertical directions on a semiconductor substrate. .

[0002]

2. Description of the Related Art Large-scale I of the conventional master slice method
In the C device, a grid-like array of the basic cells, and an input / output (I / O) cell array arranged so as to surround the grid-like array so as to exchange signals with the basic cells,
Bonding pad arrays that surround the I / O cell arrays and are arranged in the peripheral portion of the semiconductor chip for connection with an external circuit are formed in advance on a mass production basis. A single wiring layer or several wiring layers that extend to selectively form the connection between the basic cells are appropriately formed according to demand. The power supply wiring and the ground potential wiring are formed in advance on a mass production basis in the same manner as the bonding pad array so that each of the basic cells satisfies the desired specifications.

Each of the above basic cells has a TTL or CMOS
It includes a bipolar transistor for forming a logic circuit or ECL, a CMOSFET, and the like. A circuit (hereinafter referred to as an internal circuit) obtained by selectively forming the connection between the active elements and the connection between the basic cells with each other by the wiring layer is generally an external circuit of the semiconductor chip (hereinafter referred to as an external circuit). ) Has a different signal level. That is,
The signal from the external circuit may be both the signal level of the TTL or CMOS logic circuit (hereinafter collectively referred to as CMOS level) and the signal level of ECL (hereinafter referred to as ECL level), whereas the internal circuit In many cases, the signals that can be responded to are limited to the CMOS level. In that case, it is necessary to convert an ECL level signal from an external circuit to a CMOS level by a level conversion circuit provided near the I / O cell in the semiconductor chip or as a part of the I / O cell. Similarly, the output signal to the external circuit is also CMO.
It is necessary to perform the inverse level conversion from the S level to the ECL level.

As the semiconductor technology advances, electrical isolation from the substrate of the n-channel MOSFET formed in the p-type well in the p-type semiconductor substrate becomes possible. In a semiconductor IC based on this technique, the above internal circuit is at the ECL level. Can be directly driven by the signal (see Institute of Electronics, Information and Communication Engineers Technical Research Report, pages 61-67, published on July 20, 1990). However, in this case EC
Connection with an external circuit operating at the L level does not require the above level conversion, but connection with an external circuit operating at the CMOS level requires level conversion.

[0005]

As described above, in the IC circuit of this type according to the prior art, the signal level to which the internal circuit can respond is limited, and the input signal from the external circuit which operates at a signal level other than the signal level is limited. You have to change the level. The above-mentioned level conversion circuit formed on the IC chip for this level conversion occupies an area which is the surface of the IC chip and impairs the effective use of the surface of the chip.
It increases the time required for signal transmission / reception between the IC chip and the external circuit, and increases power consumption. On the other hand, as the density and speed of master slice type IC devices, that is, gate arrays, are increasing, the types of external circuits to be connected with are also increasing. Therefore, there is a demand for flexibility that the gate array should have in connection with external circuits. It is rising.

Therefore, an object of the present invention is to provide a large-scale master-slice IC device capable of responding to a plurality of signal levels without substantially depending on the level conversion circuit.

Another object of the present invention is to provide a master slice type large-scale IC device capable of flexibly coping with connection with a plurality of external circuits having different signal levels.

[0008]

In a master slice type large-scale IC device according to the present invention, each of the basic cells arranged in a grid on a semiconductor substrate is electrically isolated from the substrate. It has a formed p-type well and an n-type well formed separately from the p-type well. The p-type well and the n-type well of one basic cell are formed separately from the corresponding wells of the basic cells adjacent to that cell. Each of the n-type well and p-type well of the basic cells has a p-channel MOSFET and an n-type well.
Channel MOSFETs are respectively formed. Those p
A power supply wiring and a ground potential wiring are separately formed in a direction perpendicular to the respective gate electrodes of the channel MOSFET and the n-channel MOSFET. A bipolar transistor is also formed in each of the basic cells. With the above configuration, each of the basic cells can be driven by signals having different voltages, so that the signal level of the drive signal of the internal circuit does not depend on the I / O interface circuit or the level conversion circuit described above. You can choose.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a layout diagram of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a broken line X in FIG.
It is a schematic sectional drawing in -Y.

As shown in FIGS. 1 and 2, basic cells 101 formed on a semiconductor substrate 1 in both horizontal and vertical directions,
102, 103 and 104 are provided. Although many of these basic cells are arranged in the horizontal and vertical directions on the surface of an actual large-scale IC chip, only four of them are shown for convenience of illustration. Each of these cells 101, 102, 103 and 104 has p
An n-type well 2 and a p-type well 6 are formed respectively on the surface of the type silicon substrate 1. The p-type well 6 is electrically isolated from the p-type silicon substrate 1 by the n-type buried layer 5 and the adjacent n-type well 2. A source / drain region 4 is formed in the n-type well 2 by p ⁺ -type impurity diffusion.
And a gate electrode 3 is formed between these regions 4 via a gate insulating film, and the p-channel MOSFET 20 is formed.
Make up 1. Source / drain regions 8 are formed in the p-type well 6 by n ⁺ -type impurity diffusion, and a gate electrode 7 is formed between these regions 8 via a gate insulating film to form an n-channel MOSFET 202. . On the other hand, a collector region 10 formed by n-type impurity diffusion, a base region 11 formed by p-type impurity diffusion, and an emitter region 12 formed by n ⁺ -type impurity diffusion are formed in regions separated by the n ⁺ -type buried layer 9 in the same cell. And a bipolar npn transistor 203 is formed. These areas 10, 11,
And 12 are connected to the collector electrode 13, the base electrode 14, and the emitter electrode 15, respectively.

As described above, each of the cells 101 to 104 is composed of a bipolar-CMOS circuit, and these cells as a whole constitute a biCMOS gate array.
The gate electrode 3 of the p-channel MOSFET 201 is arranged in parallel with the arrangement of the n-type wells 2 of the cells 101 and 102.
A first wiring 21 is formed that crosses the contactlessly.
The n-channel MOSFET parallel to the arrangement of the wells 6.
Second wiring 2 that crosses the gate electrode 7 of 202 in a non-contact manner
2 is formed. Similarly, n in cells 103 and 104
A third wiring 23 that crosses the gate electrode 3 of the p-channel MOSFET 201 in the type well 2 in a non-contact manner and a fourth wiring 24 that crosses the gate electrode 7 of the n-channel MOSFET 202 in the p-type well 6 in a non-contact manner are formed. To be done.

The above-mentioned second and third wirings 22 and 23
Is a ground potential point (not shown), and the first and fourth wirings 21 and 24 are a power supply (not shown) of the voltage V _CC (positive voltage) and the voltage V _EE (negative voltage). The p-channel MOSFETs 201 of the n-type wells 2 of the cells 101 and 102, which are respectively connected, are supplied with the voltage V _CC through the contact hole 16 and the first wiring 21. Similarly, the n-channel MOSFET 202 of the p-type well 6 is connected to the ground potential point through the contact hole 17 and the second wiring 22. Therefore, these MOSFETs in each of these cells 101 and 102 are
An internal circuit that operates at a level drive voltage is configured.

On the other hand, n of each of the cells 103 and 104
The p-channel MOSFET 201 of the p-type well 2 is connected to the ground potential point (not shown) through the contact hole 18 and the wiring 23, and the n-channel MOS of the p-type well 6 is formed.
The FET 202 is connected to the power source of the voltage V _EE through the contact hole 19 and the wiring 24. Therefore, these MOSFETs in each of these cells 103 and 104, respectively.
Constitutes an internal circuit that operates at the ECL level drive voltage.

In this embodiment, when the connection destinations of the wirings 21 and 22 are reversed to the ground potential point and the power source of the voltage V _EE , the cells 101 and 102 are an ECL level internal circuit, and the cells 103 and 104 are a CMOS level internal circuit. Are converted into

As mentioned above, cell 1 in this embodiment
Each of the wells 2 and 6 of 01 to 104 are not only independent of each other in each cell due to the above electrical isolation but also independent of the corresponding wells of the adjacent cells. The supply of the power supply voltage V _CC / V _EE by / 24 can be flexibly selected according to the signal level of the external circuit, whereby the internal circuit of each of these cells can be set to either the CMOS level or the ECL level. Can be flexibly adapted. If the signal level of the external circuit is known in advance, the wiring 21/22
IC is connected to a pair of external power supply of voltage V _CC / V _EE
Since the user can flexibly select the I / O cell on the IC chip, the level conversion circuit can be eliminated.

FIG. 3 is a layout diagram of a semiconductor chip for explaining the second embodiment of the present invention.

As shown in FIG. 3, the first electrode which crosses the gate electrode 3 of the p-channel MOSFET in a contactless manner in parallel with the arrangement of the n-type wells 2 of the cells 101 and 102 having the same structure as the first embodiment. The wiring 21 and the third wiring 23 parallel to the wiring 21 are formed. Similarly, cell 10
A second contactless crossing of the gate electrode 7 of the n-channel MOSFET in parallel with the arrangement of the p-type wells 1 and 102.
The wiring 22 and the fourth wiring 24 are formed in parallel with the wiring 22. The first and fourth wirings 21 and 24 are connected to an external power source (not shown) of the voltages V _CC and V _EE , and the second and third wirings 22 and 23 are connected to a ground potential point (not shown), respectively. Connected.

P channel F of n-type well 2 of cell 101
ET is supplied with the voltage V _CC through the contact hole 16 and the wiring 21, and the n-channel FET of the p-type well 6 of the same cell 101 has the contact hole 17 and the wiring 2.
2 receives the ground potential. By connecting these with the wirings 21 and 22, the signal level of the internal circuit of the cell 101 can be set to the CMOS level.

On the other hand, the p-channel MOSFET of the n-type well 2 of the cell 102 has the contact hole 18 and the wiring 2.
3, the n-channel MOSFET of the p-type well 6 of the same cell 102 receives the ground potential, and the contact hole 19
Also, V _EE is supplied through the wiring 24. Wiring 23
The signal level of the internal circuit of the cell 102 can be set to the ECL level by the above-described connection with 24 and 24.

As described above, in the second embodiment, the cells 101 and 102 adjacent to each other can be operated by the input signals having different signal levels, and the signal of the internal circuit according to the signal level of the external circuit can be operated. The flexibility of level selection can be further increased as compared with the first embodiment described above.

[0022]

As described above, according to the present invention, each p-type well of the basic cell is electrically isolated from the substrate, independently of the n-type well, and corresponding to the adjacent cell. P-channel / n-channel MOS formed inside the n-type / p-type well separately from the well
A plurality of wiring layers are formed in a direction that crosses the gate electrode of the FET in a non-contact manner, and the connection between the MOSFET and the wiring layers and the connection relationship between these wiring layers and the voltage V _CC / V _EE and the ground potential point are external. Since the flexibility can be selected according to the signal level of the circuit, the signal level of the internal circuit can be adapted to that of the external circuit without depending on the I / O cell on the IC chip or the level conversion circuit.

Therefore, not only the I / O cell on the semiconductor chip can be simplified, but also this type of IC of the prior art can be used.
The above-mentioned level conversion circuit which is indispensable for the device can be removed from the IC chip. That is, not only the effective use of the surface area of the semiconductor chip is enabled, but also an increase in signal processing time and an increase in power consumption due to the level conversion can be avoided.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along a broken line XY in FIG.

FIG. 3 is a layout diagram of a semiconductor chip for explaining a second embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 n-type well 3,7 gate electrode 4,8 source / drain region 5 n-type buried layer 6 p-type well 9 n ⁺ type buried layer 10 collector region 11 base region 12 emitter region 13 collector electrode 14 base Electrode 15 Emitter electrode 16, 17, 18, 19 Contact hole 21, 22, 23, 24 Wiring 101, 102, 103, 104 Cell 201 p-channel MOSFET 202 n-channel MOSFET 203 Bipolar transistor

Claims (3)

[Claims] 1. A large number of cells, each of which is arranged adjacent to each other in a horizontal and vertical direction in a grid pattern on a surface of a semiconductor substrate of one conductivity type, each cell including a plurality of MOSFETs and at least one bipolar transistor. In a master slice type semiconductor device including a wiring means for connecting a cell to a power source of a predetermined voltage and a reference potential point, each of the cells has a first opposite conductivity type formed on a surface of the semiconductor substrate. And a second well of one conductivity type that is electrically isolated from the semiconductor substrate by a buried layer of opposite conductivity type formed on the surface of the semiconductor substrate and separated from the first well. And at least one pair of p-channel MOSFET and n-channel MOSFET formed inside each of the first and second wells, respectively.
And at least one bipolar transistor formed separately from the first and second wells, the p-channel MOSFET and the n-channel MO
In order to supply the predetermined voltage to the SFET, these M
A master-slice semiconductor integrated circuit further comprising a plurality of wiring means extending in parallel to each other across the gate electrode of the OSFET in a non-contact manner and selectively connected to desired electrodes of these MOSFETs through contact holes. Circuit device. 2. A first wiring, wherein the plurality of wiring means are arranged across the gate electrode of the p-channel MOSFET formed in the cell in a non-contact manner and connected to a power supply of a first external voltage. 2. The member according to claim 1, further comprising: a member and a second wiring member that is arranged so as to cross the gate electrode of the n-channel MOSFET formed in the cell in a non-contact manner and is connected to an external power source having a second voltage. Master slice type semiconductor integrated circuit device. 3. The plurality of wiring means are arranged in parallel adjacent to each other across the gate electrode of the p-channel MOSFET formed in the cell in a contactless manner, and an external power source of a first voltage and a reference. The first and third wiring members respectively connected to the potential point and the external power source and the reference potential of the second voltage arranged across the gate electrode of the n-channel MOSFET formed in the cell in a non-contact manner. The master slice semiconductor integrated circuit device according to claim 1, further comprising second and fourth wiring members connected to the respective points.