JPH05343985A - Exclusive or/exclusive nor logic circuit - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a semiconductor integrated circuit by reducing the number of circuit components. CONSTITUTION:An input A is imparted to an input terminal of a CMIS inverter 20 comprising a PMIS transistor(TR) TP1 and an NMIS TR TN1, gates of an NMIS TR TN2 and a PMIS TR TP2 are connected in common and an input B is fed to the connecting point. Then an input terminal and an output terminal of the CMIS inverter 20 are connected in common respectively via the PMIS TR TP2 and the NMIS TR TN2 and an output X is extracted from the connecting point. With the input B set to a level, the TN2 is turned on and the TP2 is turned off, the output X is equal to the inverted input A by the CMIS inverter 20 and when the input B is set to 0, the TN2 is turned off and the TP2 is turned on and the output X equal to the input A. Thus, the output X is exclusive OR of the inputs A, B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive OR / exclusive NOR circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional exclusive OR of this kind.
An exclusive NOR circuit is shown.

This circuit includes a pMIS transistor TP1.
Is connected to the high potential side power supply line VCC via the pMIS transistor TP2, the nMIS transistor TN1 is connected to the low potential side power supply line VSS via the nMIS transistor TN2, and the pMIS transistors TP1 and n are connected.
CMIS inverter 10 with MIS transistor TN1
Is configured. Also, the pMIS transistor TP3
Is connected to the high potential side power supply line VCC via the pMIS transistor TP4, the nMIS transistor TN3 is connected to the low potential side power supply line VSS via the nMIS transistor TN4, and the pMIS transistors TP3 and n are connected.
CMIS inverter 12 with MIS transistor TN3
Is configured.

The input A is supplied to the input end of the CMIS inverter 10, and the input * A which is the inverted input A is supplied to the input end of the CMIS inverter 12. The gate of the pMIS transistor TP2 and the gate of the nMIS transistor TN4 are connected in common, the input B is supplied to this, and n
The gate of the MIS transistor TN2 and the gate of the pMIS transistor TP4 are connected in common, and the input * B which is the inverted input B is supplied to this. Further, the output end of the CMIS inverter 10 and the output end of the CMIS inverter 12 are commonly connected, and the output X is taken out from this.

In the above configuration, when the input B is "1" (high level) and the input * B is "0" (low level), pMI
S transistor TP2 and nMIS transistor TN2
Is turned off, and the pMIS transistor TP4 and the nMIS transistor TN4 are turned on.
Is the input * A inverted by the CMIS inverter 12,
That is, it becomes equal to the input A.

Input B is "0" and input * B is "1".
At this time, since the pMIS transistor TP2 and the nMIS transistor TN2 are turned on and the pMIS transistor TP4 and the nMIS transistor TN4 are turned off, the output X is equal to the input A inverted by the CMIS inverter 10, that is, the input * A. Become.

Therefore, the output X is the input * A and the input * B.
And the exclusive OR of the inputs A and B.

[0008]

However, in order to use the circuit of FIG. 7 as a two-input exclusive OR circuit for inputs * A and * B, not only inputs * A and * B but also inputs A and Since B is required, if there is only one set of inputs * A, * B or one of inputs A, B, then two CMIS inverters are required to produce the other set of signals.
Similarly, in order to use the circuit of FIG. 7 as a 2-input exclusive NOR circuit for inputs A and B, not only inputs A and B but also inputs * A and * B are required. , B or only one set of inputs * A, * B, two CMIS inverters are required to produce the other set of signals.

Therefore, in a semiconductor integrated circuit having various exclusive OR circuits or exclusive NOR circuits,
When the circuit of FIG. 7 is used, the circuit becomes large in scale, which hinders the improvement of the degree of integration.

In view of such problems, an object of the present invention is to provide an exclusive OR / exclusive NOR circuit capable of reducing the number of circuit elements and improving the integration degree of a semiconductor integrated circuit. Especially.

[0011]

Means for Solving the Problem and Its Action The exclusive OR / exclusive NOR circuit according to the present invention will be described with reference to the reference numerals of the corresponding constituent elements in the embodiments.

In the exclusive OR circuit of the first invention, for example, as shown in FIG. 1, the source of the first pMIS transistor TP1 is connected to the high potential side power supply line, and the source of the first nMIS transistor TN1 is supplied with the low potential side power supply. Connected to a line, and connected to the gate of the first pMIS transistor TP1 and the first n-th transistor.
The gates of the MIS transistors TN1 are commonly connected to serve as an input terminal, the drain of the first pMIS transistor TP1 and the drain of the first nMIS transistor TN1 are commonly connected to serve as an output terminal, and the source is the first CMIS inverter 20. A second input connected to the input terminal of the inverter 20 and having the first input A supplied to the source;
The pMIS transistor TP2 and the drain are the first CMI
It is connected to the output terminal of the S inverter 20, and the source is the second
A second nMIS that is connected to the drain of the pMIS transistor TP2, has its gate connected to the gate of the second pMIS transistor TP2, and is supplied with the second input B at its gate.
A transistor TN2, and a drain of the second pMIS transistor TP2 and a second nMIS transistor TN2.
The exclusive OR X of the first input A and the second input B is output from the connection point with the source of the.

The exclusive OR circuit of the first invention has four circuit elements, which is half the number of elements in the circuit of FIG.
Moreover, since the negative signal * A of the first input A and the negative signal * B of the second input B are not required, it is not necessary to add two new CMIS inverters when there are no inputs * A and * B. .. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

In the exclusive NOR circuit of the second invention, for example, as shown in FIG. 2, the source of the first pMIS transistor TP1 is connected to the high potential side power supply line, and the first nMIS is provided.
The source of the transistor TN1 is connected to the low potential side power supply line, the gate of the first pMIS transistor TP1 and the gate of the first nMIS transistor TN1 are commonly connected to serve as an input terminal, and the drain of the first pMIS transistor TP1 and the first nMIS transistor TN1 are connected. Of the first CMIS inverter 20 whose drains are connected in common to serve as an output end, the drain thereof is connected to the input end of the first CMIS inverter 20, the first input A is supplied to the drain, and the second nMIS transistor TN2 and the source Is the first C
The second p that is connected to the output terminal of the MIS inverter 20, the drain is connected to the source of the second nMIS transistor TN2, the gate is connected to the gate of the second nMIS transistor TN2, and the second input B is supplied to the gate
A first input A and a second input B from a connection point between the drain of the second pMIS transistor TP2 and the source of the second nMIS transistor TN2.
An exclusive-NOR * X of is output.

The exclusive NOR circuit of the second invention is
There are four circuit elements, which is half the number of elements in the circuit of FIG. Moreover, since the negative signal * A of the first input A and the negative signal * B of the second input B are not required, the inputs * A and * B
There is no need to add two new CMIS inverters. Therefore, if this exclusive NOR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

The exclusive OR circuit of the third invention is, for example, as shown in FIG. 3, the exclusive NOR X circuit of the second invention and the source of the third pMIS transistor TP3 are connected to the high potential side power supply line. And the third nMIS transistor T
The source of N3 is connected to the low potential side power supply line,
The gate of the MIS transistor TP3 and the gate of the third nMIS transistor TN3 are commonly connected to serve as an input terminal, the output terminal of the exclusive-NOR circuit is connected to the input terminal, and the drain of the third pMIS transistor TP3 and the third
The nMIS transistor TN3 has a second CMIS inverter 22 whose drain is commonly connected to serve as an output terminal, and an exclusive OR X of the first input A and the second input B from the output terminal of the second CMIS inverter 22. Is output.

The exclusive OR circuit according to the third aspect of the invention has six circuit elements, which is less than the number of elements in the circuit of FIG. 7 of 8, and the negative signal * A of the first input A and the second input. Since the negative signal * B of B is not required, the inputs * A and * B
There is no need to add two new CMIS inverters. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved. The exclusive OR circuit of the third aspect of the invention is superior to the exclusive OR circuit of the first aspect of the invention in terms of output drive capability.

In the exclusive-NOR circuit of the fourth invention, for example, as shown in FIG. 4, the exclusive-OR circuit of the first invention and the source of the third pMIS transistor TP3 are connected to the high potential side power supply line. , The third nMIS transistor T
The source of N3 is connected to the low potential side power supply line,
The gate of the MIS transistor TP3 and the gate of the third nMIS transistor TN3 are commonly connected to serve as an input terminal, the output terminal of the exclusive OR X circuit is connected to the input terminal, and the drain of the third pMIS transistor TP3 and the third
The second CMIS inverter 22 having the drain of the nMIS transistor TN3 connected in common as an output end is provided, and the exclusive OR of the first input A and the second input B from the output end of the second CMIS inverter 22. * X is output.

The exclusive NOR circuit of the fourth invention is
The number of circuit elements is 6, which is less than the number of elements 8 in the circuit of FIG. 7, and the negative signal * A of the first input A and the second input B
Inputs * A and * are not required because the negative signal * B of
When B does not exist, it is not necessary to add two new CMIS inverters. Therefore, if this exclusive NOR circuit is used, the integration degree of the semiconductor integrated circuit can be improved. The exclusive NOR circuit of the fourth aspect of the invention is superior to the exclusive NOR circuit of the second aspect of the invention in terms of output drive capability.

In the exclusive OR circuit of the fifth invention, for example, as shown in FIG. 5, the source of the first pMIS transistor TP1 is connected to the high potential side power supply line, and the drain of the first pMIS transistor TP1 is connected to the second nMIS transistor TN2TN2. Through the first nMIS transistor TN1
Connected to the drain of the first nMIS transistor TN
A first series circuit in which the source of 1 is connected to the low potential side power supply line through the fourth nMIS transistor TN4;
The drain of the nMIS transistor TN3 is the second pMIS.
The high-potential-side power supply line VC via the transistor TP2
C, the source of the third nMIS transistor TN3 is connected to the source of the third pMIS transistor TP3, and the drain of the third pMIS transistor TP3 is the fourth.
a second series circuit connected to the low-potential-side power supply line via a pMIS transistor TP4, and a first nMIS
Transistor TN1, third nMIS transistor TN
3, first pMIS transistor TP1 and third pMIS
The gates of the transistors TP3 are commonly connected to each other, the first input A is supplied to the gates of the transistors TP3, the second nMIS transistor TN2, the fourth nMIS transistor TN4, and the second pM.
The gates of the IS transistor TP2 and the fourth pMIS transistor TP4 are commonly connected to each other and the second input B is supplied thereto, and the source of the second nMIS transistor TN2 and the source of the third nMIS transistor TN3 are commonly connected to each other. 1 input A and 2nd input B
An exclusive OR X of is output.

The exclusive OR circuit of the fifth invention has eight elements, which is the same as the number of circuit elements shown in FIG.
Since the negative signal * A of the input A and the negative signal * B of the second input B are not required, it is not necessary to add two new CMIS inverters when there are no inputs * A and * B. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved. The exclusive-OR circuit of the fifth invention is superior in output drive capability to the exclusive-OR circuit of the first invention, and operates faster than the exclusive-OR circuit of the third invention. Is excellent in terms of.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows an exclusive OR circuit of the first embodiment.

This circuit includes a pMIS transistor TP1
The input A is supplied to the input terminal of the CMIS inverter 20 composed of the nMIS transistor TN1 and the nMIS transistor TN1, and the gates of the nMIS transistor TN2 and the pMIS transistor TP2 are commonly connected and the input B is supplied thereto. Further, the input end and the output end of the CMIS inverter 20 are commonly connected via the pMIS transistor TP2 and the nMIS transistor TN2, respectively, and the output X is taken out from this.

In the above configuration, when the input B is "1", the nMIS transistor TN2 is turned on, the pMIS transistor TP2 is turned off, and the output X is the input A when the input A is CMI.
It becomes equal to that inverted by the S inverter 20. Also,
When the input B is "0", the nMIS transistor TN2 is turned off, the pMIS transistor TP2 is turned on, and the output X becomes equal to the input A. Therefore, the output X is the input A
And the exclusive OR of the input B.

The exclusive OR circuit of the first embodiment has four circuit elements, which is half the number of elements in the circuit of FIG. Moreover, since the negative signal * A of the input A and the negative signal * B of the input B are not required, it is not necessary to add two new CMIS inverters when the inputs * A and * B are not present. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

[Second Embodiment] FIG. 2 shows an exclusive NOR circuit of the second embodiment.

This circuit has pMIS transistor TP1.
The input A is supplied to the input terminal of the CMIS inverter 20 composed of the nMIS transistor TN1 and the nMIS transistor TN1, and the gates of the nMIS transistor TN2 and the pMIS transistor TP2 are commonly connected and the input B is supplied thereto. Further, the input end and the output end of the CMIS inverter 20 are commonly connected via the nMIS transistor TN2 and the pMIS transistor TP2, respectively, and the output * X
Is taken out.

In the above structure, when the input B is "1", the nMIS transistor TN2 is turned on, the pMIS transistor TP2 is turned off, and the output * X becomes equal to the input A. When the input B is '0', the nMIS transistor TN2 is turned off, the pMIS transistor TP2 is turned on, and the output * X is the input A when the CMIS inverter 20 is used.
It becomes equal to the one inverted at. Therefore, the output * X is the exclusive NOR of the input A and the input B.

The exclusive NOR circuit of the second embodiment has four circuit elements, which is half the number of elements in the circuit of FIG. Moreover, since the negative signal * A of the input A and the negative signal * B of the input B are not required, it is not necessary to add two new CMIS inverters when the inputs * A and * B are not present. Therefore, if this exclusive NOR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

[Third Embodiment] FIG. 3 shows an exclusive OR circuit of the third embodiment. The same components as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

This circuit has a structure in which the output terminal of the exclusive NOR circuit of FIG. 2 is connected to the input terminal of the CMIS inverter 22 composed of the pMIS transistor TP3 and the nMIS transistor TN3. The exclusive OR X of the input A and the input B is taken out from the output end.

This exclusive OR circuit has six circuit elements, which is less than the number of elements in the circuit of FIG.
Since the negation signal * A of the input A and the negation signal * B of the input B are not required, C is newly added when there are no inputs * A and * B.
There is no need to add two MIS inverters. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

This exclusive OR circuit is superior to the exclusive OR circuit of FIG. 1 in terms of output drive capability.

[Fourth Embodiment] FIG. 4 shows an exclusive NOR circuit of the fourth embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

This circuit has a structure in which the output terminal of the exclusive OR circuit of FIG. 1 is connected to the input terminal of a CMIS inverter 22 composed of a pMIS transistor TP3 and an nMIS transistor TN3.
The exclusive-NOR * X of the input A and the input B is taken out from the output terminal of 2.

This exclusive-NOR circuit has six circuit elements, which is less than the number of elements of the circuit of FIG. 7, which is eight, and has the negative signal * A of the input A and the negative signal * B of the input B. Is not required, it is not necessary to add two new CMIS inverters when there are no inputs * A and * B. Therefore, if this exclusive NOR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

This exclusive NOR circuit is superior to the exclusive NOR circuit in FIG. 2 in terms of output drive capability.

[Fifth Embodiment] FIG. 5 shows an exclusive OR circuit of the fifth embodiment.

This circuit has pMIS transistor TP1.
Source is connected to the high potential side power supply line VCC, and pM
The drain of the IS transistor TP1 is connected to the drain of the nMIS transistor TN1 via the nMIS transistor TN2, and the source of the nMIS transistor TN1 is connected to the low potential side power supply line VSS via the nMIS transistor TN4. Further, the drain of the nMIS transistor TN3 is connected to the high potential side power supply line VCC via the pMIS transistor TP2,
The source of the transistor TN3 is the pMIS transistor T.
PMIS transistor TP3 connected to the source of P3
Is connected to the low potential side power supply line VSS through the pMIS transistor TP4.

NMIS transistors TN1, TN3, p
The gates of the MIS transistors TP1 and TP3 are commonly connected to each other, and the input A is supplied to them. Also, n
The gates of the MIS transistors TN2 and TN4 and the pMIS transistors TP2 and TP4 are commonly connected to each other, and the input B is supplied to them. Further, the source of the nMIS transistor TN2 and the nMIS transistor TN3
Source are connected together and the output X is taken from this.

In the above structure, when the input B is "1", the nMIS transistors TN2 and TN4 are turned on and p
The MIS transistors TP2 and TP4 are turned off, and the output X becomes equal to the input A inverted by the CMIS inverter including the pMIS transistor TP1 and the nMIS transistor TN1. Further, when the input B is "0", the nMIS transistors TN2 and TN4 are off, p
The MIS transistors TP2 and TP4 are turned on, and the output X becomes equal to the one obtained by passing the input A through the non-inverting gate formed of the nMIS transistor TN3 and the pMIS transistor TP3, that is, the input A. Therefore, the output X is the exclusive OR of the input A and the input B.

The number of elements of this exclusive OR circuit is eight, which is the same as the number of circuit elements in FIG. 7, but the negation signal * A of the input A and the negation signal * B of the input B are not required. So
When there are no inputs * A and * B, it is not necessary to add two new CMIS inverters. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

This exclusive OR circuit is superior to the exclusive OR circuit of FIG. 1 in terms of output drive capability, and is also shown in FIG.
It is superior to the exclusive OR circuit in that it operates faster.

FIG. 6 shows an on-chip pattern of the circuit of FIG. In this circuit, an n-type well 40 is formed on the surface of a p-type substrate 30, and a p-type diffusion region P1 is formed in the n-type well 40.
And P2 are formed, and n-type diffusion regions N1 and N2 are formed in the p-type substrate 30 near the n-type well 40. In the figure, G1 and G2 are the gates of the 0th layer and are formed of polysilicon or the like. S1, S2 and S3 are metal wirings of the first layer from the p-type substrate 30 side, like the high potential side power supply line VCC and the low potential side power supply line VSS.
Reference numeral 4 denotes a second layer metal wiring from the p-type substrate 30 side. The small rectangle in the figure is an interlayer connection contact, of which C1 is the high potential side power supply line VCC and the n-type well 40.
And C2 and C3 are connected to the low potential side power supply line VSS
Is connected to the p-type substrate 30, and C4 connects the metal wiring S1 and the metal wiring S4.

As is apparent from FIG. 6, the required chip area of this exclusive OR circuit is relatively small.

[0047]

As described above, both the exclusive OR circuit according to the first aspect of the invention and the exclusive NOR circuit according to the second aspect of the invention have four circuit elements. Half the number of elements, and the negative signal of the first input A *
Since A and the negative signal * B of the second input B are not required,
When there are no inputs * A and * B, it is not necessary to add two new CMIS inverters, and therefore, it is possible to reduce the number of circuit elements and improve the integration degree of the semiconductor integrated circuit. ..

Exclusive OR circuit according to third invention and fourth invention
Each of the exclusive NOR circuits according to the invention has six circuit elements, which is half the number of elements of the conventional circuit of FIG.
Moreover, since the negative signal * A of the first input A and the negative signal * B of the second input B are not required, it is not necessary to add two new CMIS inverters when there are no inputs * A and * B. Therefore, there is an excellent effect that the number of circuit elements can be reduced and the degree of integration of the semiconductor integrated circuit can be improved.

The exclusive-OR circuit of the third invention is superior to the exclusive-OR circuit of the first invention in output driving capability, and the exclusive-NOR circuit of the fourth invention is The number of elements of the exclusive OR circuit according to the fifth invention, which is superior to the exclusive NOR circuit of the second invention in terms of output drive capability, is eight, and the number of elements of the conventional circuit of FIG. Same as the above, but since the negative signal * A of the first input A and the negative signal * B of the second input B are not required, two new CMIS inverters are added when there are no inputs * A and * B. You don't have to. Therefore, if this exclusive OR circuit is used, the integration degree of the semiconductor integrated circuit can be improved.

The exclusive OR circuit of the fifth aspect of the invention is superior to the exclusive OR circuit of the first aspect of the invention in terms of output drivability, and is superior to the exclusive OR circuit of the third aspect of the invention. Excellent in high speed operation.

[Brief description of drawings]

FIG. 1 is an exclusive OR circuit diagram of a first embodiment of the present invention.

FIG. 2 is an exclusive NOR circuit diagram of a second embodiment of the present invention.

FIG. 3 is an exclusive OR circuit diagram of a third embodiment of the present invention.

FIG. 4 is an exclusive NOR circuit diagram of a fourth embodiment of the present invention.

FIG. 5 is an exclusive OR circuit diagram of a fifth embodiment of the present invention.

6 is an on-chip pattern diagram of the circuit of FIG.

FIG. 7 is a conventional exclusive OR / exclusive NOR circuit diagram.

[Explanation of symbols]

 10, 12, 20, 22 CMIS inverter 30 p-type substrate 40 n-type well TP1 to TP4 pMIS transistor TN1 to TN4 nMIS transistor

Claims (5)

[Claims] 1. A source of a first pMIS transistor (TP1) is connected to a high potential side power supply line, and a first nMIS is provided.
The source of the transistor (TN1) is connected to the low-potential-side power supply line, the gate of the first pMIS transistor and the gate of the first nMIS transistor are commonly connected to serve as an input terminal, and the drain of the first pMIS transistor and the first pMIS transistor are connected to each other. A first CMIS inverter (20) in which the drains of the 1nMIS transistors are commonly connected to serve as an output terminal.
A second pMI having a source connected to the input end of the first CMIS inverter and being supplied with the first input (A).
An S-transistor (TP2), a drain connected to the output terminal of the first CMIS inverter, a source connected to the drain of the second pMIS transistor, a gate connected to the gate of the second pMIS transistor, and a second connected to the gate. A second nMIS transistor (TN2) to which the input (B) is supplied, and the drain of the second pMIS transistor and the second nMI.
An exclusive OR circuit, wherein an exclusive OR (X) of the first input and the second input is output from a connection point with the source of the S transistor. 2. A source of the first pMIS transistor (TP1) is connected to a high potential side power supply line, and a first nMIS transistor is provided.
The source of the transistor (TN1) is connected to the low-potential-side power supply line, the gate of the first pMIS transistor and the gate of the first nMIS transistor are commonly connected to serve as an input terminal, and the drain of the first pMIS transistor and the first pMIS transistor are connected to each other. A first CMIS inverter (20) in which the drains of the 1nMIS transistors are commonly connected to serve as an output terminal.
A drain is connected to the input end of the first CMIS inverter, the first input (A) is supplied to the drain, and the second nM
An IS transistor (TN2), a source connected to the output terminal of the first CMIS inverter, a drain connected to the source of the second nMIS transistor, a gate connected to the gate of the second nMIS transistor, and a second connected to the gate. A second pMIS transistor (TP2) supplied with an input (B), the drain of the second pMIS transistor and the second nMI.
An exclusive-NOR circuit, wherein an exclusive-NOR (* X) of the first input and the second input is output from a connection point with the source of the S transistor. 3. The exclusive NOR circuit according to claim 2, the source of the third pMIS transistor (TP3) is connected to a high potential side power supply line, and the source of the third nMIS transistor (TN3) is low potential power supply. Connected to the wire,
The gate of the third pMIS transistor and the third nMIS
The gates of the transistors are commonly connected to serve as an input end, the output end of the exclusive NOR circuit is connected to the input end, and the drain of the third pMIS transistor and the third pMIS transistor are connected.
a second CMIS inverter (22) having the drains of the nMIS transistors connected in common to serve as an output end, and the first input (A) and the second input (B) from the output end of the second CMIS inverter An exclusive-OR circuit that outputs an exclusive-OR (X) with 4. The exclusive OR circuit according to claim 1, the source of the third pMIS transistor (TP3) is connected to the high potential side power supply line, and the source of the third nMIS transistor (TN3) is low potential side power supply line. Connected to the
The gate of the third pMIS transistor and the third nMIS
The gates of the transistors are commonly connected to form an input terminal, the output terminal of the exclusive OR circuit is connected to the input terminal, and the drain of the third pMIS transistor and the third nMIS transistor are connected to each other.
A second CMIS inverter (22) having the drains of the MIS transistors connected in common and serving as an output end, and the first input (A) and the second input (B) from the output end of the second CMIS inverter. Exclusive-Nor with (*
X) is output, an exclusive NOR circuit. 5. A source of the first pMIS transistor (TP1) is connected to a high potential side power supply line, and the first pMIS transistor (TP1) is connected to the high potential side power supply line.
The drain of the S transistor is connected to the first nMIS transistor (TN) via the second nMIS transistor (TN2).
1) the drain of the third nMIS transistor (TN3) is connected to the drain of the first nMIS transistor, and the source of the first nMIS transistor is connected to the low potential side power supply line via the fourth nMIS transistor (TN4). Two
It is connected to the high-potential-side power supply line VCC through a pMIS transistor (TP2), the source of the third nMIS transistor is connected to the source of the third pMIS transistor (TP3), and the drain of the third pMIS transistor is the fourth pMIS transistor ( A second series circuit connected to the low-potential-side power supply line via TP4), the first nMIS transistor, the third nMIS transistor, the first pMIS transistor, and the third pMIS.
The gates of the transistors are commonly connected to each other and the first input (A) is supplied thereto, and the gates of the second nMIS transistor, the fourth nMIS transistor, the second pMIS transistor and the fourth pMIS transistor are commonly connected to each other. The second input (B) is supplied to the source of the second nMIS transistor and the third nM transistor.
An exclusive OR circuit, wherein the sources of the IS transistors are commonly connected to each other and an exclusive OR (X) of the first input and the second input is output from the sources.