JP2774165B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (FIGS. 8 and 9) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (FIGS. 2 to 7) (i) Description of the first embodiment (FIGS. 2 and 3) (ii) Description of the second embodiment (FIG. 4) (iii) Third implementation Description of Examples (FIGS. 5 and 6) (iv) Description of Fourth Embodiment (FIG. 7) Effect of the Invention [Overview] Semiconductor integrated circuit, especially logic configured by connecting a plurality of MOS transistors in series Regarding transistor operation of a circuit and integration thereof, an object of the present invention is to compensate for a delay of the transistor in an electric circuit without increasing the size of the transistor connected in series, to reduce power consumption and increase integration. The first circuit includes a plurality of one conductivity type field effect transistors between the power supply line and the output point. Are connected in series, and a plurality of opposite conductivity type field effect transistors are connected in parallel between a ground line and the output point. Each gate of the one conductivity type field effect transistor is connected to the opposite conductivity type electric field. An n-input logic circuit in which each gate of an effect transistor is connected and connected to an input point, wherein a first auxiliary buffer circuit is provided on a power supply side of the n-input logic circuit; The circuit includes a first one conductivity type field effect transistor having a source connected to the power supply line, a drain connected to the output point, and a gate connected to a power supply side of the one conductivity type field effect transistor connected in series. When,
A second conductivity type field effect transistor having a source connected to the power supply line, a drain connected to the power supply side of the one conductivity type field effect transistor connected in series, and a gate connected to the output point. A second circuit is the n-input logic circuit, a second auxiliary buffer circuit is provided at an output point of the n-input logic circuit, and the second auxiliary buffer circuit has a drain Are connected to the output point side of the one conductivity type field effect transistor connected in series, a source is connected to the output point, a gate is connected to the power supply line, and a first opposite conductivity type field effect transistor is connected to the power supply line. A second one-conductivity type field effect transistor connected to the power supply line at the output point side of the one-conductivity type field effect transistor having a source connected to the output point and a gate connected in series. A third circuit, wherein a plurality of one conductivity type field effect transistors are connected in parallel between a power supply line and an output point, and a third circuit is connected between a ground line and the output point. A plurality of opposite conductivity type field effect transistors are connected in series, and each gate of the one conductivity type field effect transistor and each gate of the opposite conductivity type field effect transistor are respectively connected and connected to an input terminal. A NAND logic circuit, wherein a third auxiliary buffer circuit is provided on an output point side of the n-input NAND logic circuit, wherein the third auxiliary buffer circuit has an opposite conductivity type field effect having a drain connected in series. A first conductivity type field effect transistor having a drain connected to the output point and a gate connected to the ground line, a drain connected to the ground line, and a source connected to the ground line; A fourth circuit comprising: a second one-conductivity-type field-effect transistor having a gate connected to the drain of the series-connected opposite-conductivity-type field-effect transistor at the output point. The n-input logic circuit, wherein the n-input logic circuit
A fourth auxiliary buffer circuit is provided on the ground line side of the input logic circuit, and the fourth auxiliary buffer circuit is configured to ground a field effect transistor of the opposite conductivity type having a source connected to the ground line and a drain connected in series. On the line side, a first opposite conductivity type field effect transistor having a gate connected to the drain of the one conductivity type field effect transistor, and a drain connected to the ground line and a drain connected to the one conductivity type field effect transistor. Wherein the gate comprises a second opposite conductivity type field effect transistor connected to the ground line side of the serially connected opposite conductivity type field effect transistor.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, and more particularly to a transistor operation of a logic circuit configured by connecting a plurality of MOS transistors in series and integration thereof.

2. Description of the Related Art In recent years, various logic circuits have been configured based on user's functional requirements, and these circuits are characterized by low power consumption and high-speed operation.
Manufactured by CMOS transistors.

However, when a plurality of MOS transistors are connected in series, such as an n-input logic circuit, the series resistance and the area occupied by the chip may become a problem.

Therefore, there is a demand for a circuit that can electrically compensate for the delay of a transistor connected in series without increasing the size of the transistor and reduce power consumption and achieve high integration.

[Conventional technology]

8 and 9 are explanatory diagrams of a semiconductor integrated circuit according to a conventional example.

FIG. 8 shows a configuration diagram of a four-input NOR circuit according to a conventional example.

In the figure, in the four-input NOR circuit, first, four p-type field effect transistors (hereinafter, referred to as transistors Tp) are connected in series between a power supply line VDD and an output point Y3. Further, four n-type field effect transistors (hereinafter, referred to as transistors Tn) are connected in parallel between the ground line GND and the output point Y3. Each gate Gp of the transistor Tp and the transistor
Each gate Gn of Tn is connected respectively. This connection point is connected to the input points X1 to X4.

FIG. 9 is a diagram illustrating the operation of a four-input NOR circuit according to a conventional example.

In the figure, the function of the circuit is as follows.
~ IN3 are all "L" levels, and then when the input IN4 is inverted from "H" level to "L" level, the output OUT becomes "L".
The level is inverted to the “H” level. Thus, a four-input NOR logical operation process can be performed.

Further, B is a waveform rounded portion, in which the rising of the output signal OUT becomes blunt. This is caused by the inversion of the signal and the current i flowing from the power supply line VDD to the output point Y3 via the transistor Tp connected in series.
The rounded portion B is more remarkable as the load capacity is larger.

[Problems to be solved by the invention]

By the way, according to the conventional example, the size of the transistor Tp connected in series is formed to be larger than the size of the transistor Tn in order to cope with the demand for high-speed operation of the transistor, and a logic circuit is formed by combining bipolar transistors to increase the driving capability. Is composed.

 Therefore, the following problem may occur.

. For example, when an attempt is made to construct a two-input, three-input logic circuit equivalent to the operation speed of a CMOS inverter, the size of the transistor Tp connected in series needs to be increased by a factor of four or six.

This causes an increase in input gate capacitance and an increase in power consumption. Further, the transistor Tp occupies a large area of the chip.

. In addition, the size of the bipolar transistor is CMOS
It is larger than a transistor and hinders high integration.

The present invention has been made in view of the problems of the conventional example, and compensates for the delay of the transistors connected in series in an electric circuit without increasing the size of the transistors connected in series, thereby reducing power consumption. It is an object of the present invention to provide a semiconductor integrated circuit capable of achieving high integration.

[Means for solving the problem]

FIGS. 1A to 1D show principle diagrams of a semiconductor integrated circuit according to the present invention.

The first circuit includes a plurality of one conductivity type field effect transistors Tp connected in series between a power supply line VDD and an output point Y1, and a plurality of opposite conductive fields between a ground line GND and the output point Y1. Type field effect transistors Tn are connected in parallel, each gate Gp of the one conductivity type field effect transistor Tp and each gate Gn of the opposite conductivity type field effect transistor Tn are connected to input points X1 to Xn, respectively. A first auxiliary buffer circuit 1 is provided on the power supply side of the n-input NOR logic circuit, and the first auxiliary buffer circuit 1 has a source S1 connected to the power supply line VDD. A first one-conductivity-type field-effect transistor Tp1 having a drain D1 connected to the output point Y1, a gate G1 connected to the power supply side of the one-conduction-type field-effect transistor Tp connected in series, and a source S2 is connected to the power line VDD D2 is connected to the power supply side of the series-connected one-conductivity type field effect transistor Tp, and gate G2 is formed of a second one-conductivity type field effect transistor Tp2 connected to the output point Y1. The second circuit is the n-input NOR logic circuit, and a second auxiliary buffer circuit 2 is provided at an output point Y1 of the n-input NOR logic circuit.
The drain D1 is connected to the output point Y1 of the one-conductivity type field effect transistor Tp connected in series, and the source S1 is connected to the output point Y1.
A first opposite conductivity type field effect transistor Tn1 having a gate G1 connected to the power supply line VDD, a drain D2 connected to the power supply line VDD, a source S2 connected to the output point Y1,
The gate G2 is composed of a second one-conductivity-type field-effect transistor Tn2 connected to the output point Y1 side of the one-conductivity-type one-conductivity-type field-effect transistor Tp, respectively. A plurality of one conductivity type field effect transistors Tp are connected in parallel between the power supply line VDD and the output point Y2, and a plurality of opposite conductivity type field effect transistors Tn are connected between the ground line GND and the output point Y2. Are connected in series, each gate Gp of the field effect transistor Tp of the one conductivity type and each gate Gn of the field effect transistor Tn of the opposite conductivity type are respectively connected and connected to the input points X1 to Xn. A third auxiliary buffer circuit 3 is provided on the output point Y2 side of the n-input NAND logic circuit, and the third auxiliary buffer circuit 3 has an opposite conductivity type with a drain D3 connected in series. Field-effect transistor T n, a source S3 is connected to the output point Y2, a gate G3 is connected to the ground line GND, and a first conductive type field effect transistor Tp3 is connected. A drain D4 is connected to the ground line GND. S4 is connected to the output point Y2, and the gate G4 is connected to the drain Dn of the series-connected opposite conductivity type field effect transistor Tn.
The fourth circuit is the n-input NAND logic circuit, wherein a fourth auxiliary buffer circuit 4 is provided on the ground line GND side of the n-input NAND logic circuit, Auxiliary buffer circuit 4
The source S3 is connected to the ground line GND, the drain D3 is connected to the ground line GND of the series-connected opposite conductivity type field effect transistor Tn, and the gate G4 is connected to the drain Dp of the one conductivity type field effect transistor Tp. A first opposite conductivity type field effect transistor Tn3, a source S4 connected to the ground line GND, a drain D4 connected to a drain Dp of a one conductivity type field effect transistor Tp, and a gate G4 connected in series to the other. The above object is achieved by comprising a second opposite conductivity type field effect transistor Tn4 connected to the ground line GND side of the conductivity type field effect transistor Tn, respectively.

[Action]

According to the first circuit of the present invention, the first auxiliary buffer circuit 1 is provided on the power supply side of the n-input NOR logic circuit.

For example, if all of the input points X1 to Xn-1 except for the input point Xn are at the "L" level and the input point Xn is inverted from the "H" level to the "L" level, the logic voltage at the output point Y1 becomes the auxiliary buffer. It is determined based on the current flowing through one conductivity type field effect transistor Tp1 of the circuit 1. For this reason, the one-conductivity type field-effect transistor Tp connected in series as in the conventional example is used.
It is possible to minimize the effect of the delay caused by the delay.

As a result, a high-performance, low-power-consumption multi-input NOR logic circuit device can be manufactured using only the CMOS process.

According to the second circuit, the second auxiliary buffer circuit 2 is provided at the output point Y1 of the n-input NOR logic circuit.

For example, when the signal is inverted as in the first circuit, the logic voltage at the output point Y1 is determined based on the current flowing through the opposite conductivity type field effect transistor Tn2 of the auxiliary buffer circuit 1. For this reason, similarly to the first circuit, it is possible to minimize the influence of the delay caused by the one-conduction type field effect transistor Tp connected in series as in the conventional example.

Thus, similarly to the first circuit, a high-performance, low-power-consumption multi-input NOR logic circuit device can be manufactured using only the CMOS process.

Further, according to the third circuit, the third auxiliary buffer circuit 3 is provided on the output point Y2 side of the n-input NAND logic circuit.

For example, if all the input points X1 to Xn-1 except the input point Xn are at the "H" level and the input point Xn is inverted from the "L" level to the "H" level, the logic voltage at the output point Y2 becomes It is determined based on the current flowing through the one conductivity type field effect transistor Tp4 of the circuit 3. Therefore, a field effect transistor of the opposite conductivity type connected in series as in the conventional example
The effect of the delay due to Tn can be minimized.

This makes it possible to manufacture a high-performance, low-power-consumption multi-input NAND logic circuit device using only the CMOS process.

Further, according to the fourth circuit, the auxiliary buffer circuit 4 is provided on the ground line GND side of the n-input NAND logic circuit.

For example, when the signal is inverted as in the third circuit, the logic voltage at the output point Y2 is determined based on the current flowing through the opposite conductivity type field effect transistor Tn4 of the auxiliary buffer circuit 4. Therefore, similarly to the third circuit, a series-connected field effect transistor Tn of the opposite conductivity type as in the conventional example is used.
It is possible to minimize the effect of the delay caused by the delay.

Thus, similarly to the third circuit, a high-performance, low-power-consumption multi-input NAND logic circuit device can be manufactured using only the CMOS process.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

2 to 6 are diagrams for explaining a semiconductor integrated circuit according to an embodiment of the present invention.

(I) Description of First Embodiment FIG. 2 shows a configuration diagram of a four-input NOR circuit according to a first embodiment of the present invention.

In the figure, a first four-input NOR circuit first includes a power supply line VDD.
Four p-channel MOS transistors (hereinafter, referred to as transistors Tp) are connected in series between the transistor and the output point Y1.
Further, four n-channel MOS transistors (hereinafter, referred to as transistors Tn) are connected in parallel between the ground line GND and the output point Y1. Next, each gate Gp of the transistor Tp is connected to each gate Gn of the transistor Tn. This connection point is connected to input points X1 to X4.

Up to now, it is the same as the conventional example, but the four input of the present invention
In the NOR circuit, a first current buffer circuit 11 which is an example of the first auxiliary buffer circuit 1 is provided on the power supply side of the circuit.

The first current buffer circuit 11 includes transistors Tp1, Tp2
Consists of Transistor Tp1 has source S1 connected to power supply line V
DD, the drain D1 is connected to the output point Y1, and the gate G1 is connected to the power supply side of the transistor Tp connected in series.

The transistor Tp2 has its source S2 connected to the power supply line VDD, its drain D2 connected to the power supply side of the transistor Tp connected in series, and its gate G2 connected to the output point Y1.

FIG. 3 is an operation explanatory diagram of the four-input NOR circuit according to the first embodiment of the present invention.

In the figure, a first four-input NOR circuit first has an input point X
It is assumed that the input signals IN1 to IN3 of 1 to X3 are all at "L" level and the input signal IN4 of input point X4 is at "H" level. The output signal OUT in this case is at the “L” level.

Next, when the input signal IN4 at the input point X4 is inverted from “H” level to “L” level, all the transistors Tp are turned “ON” and all the transistors Tn are turned “OFF”. As a result, the point P1 shifts to the “L” level, and the transistor Tp
1 is turned “ON” and the output point Y1 rises to “H” level.

After that, the output point Y1 changes to “H” level,
The point P1 also becomes “H” level, the transistors Tp1 and Tp2 are cut off, and the output signal OUT becomes “H” level.

Here, A in the figure is a forced operation portion, which is a portion improved by the first current buffer circuit 11. Accordingly, it is possible to suppress as much as possible the waveform rounding caused by the delay caused by the series-connected transistors Tp as in the conventional example.

Thus, according to the first circuit of the present invention, the first current buffer circuit 1 is provided on the power supply side of the four-input NOR circuit.

For this reason, it is possible to minimize the influence of the delay caused by the series-connected transistors Tp as in the conventional example.

Thus, a four-input NOR logic circuit device with high performance and low power consumption can be manufactured using only the CMOS process.

(Ii) Description of Second Embodiment FIG. 4 is a configuration diagram of a 4-input NOR circuit according to a second embodiment of the present invention.

In the figure, the second four-input NOR circuit differs from the first circuit in that a second current buffer circuit 12 is provided at the output point Y1 of the circuit.

That is, the second current buffer circuit 12 is connected to the drain D1
Are connected to the output point Y1 side of the transistor Tp, the source S1 is connected to the output point Y1, the gate G1 is connected to the power supply line VDD, the first transistor Tn1 is connected to the power supply line VDD, the drain D2 is connected to the power supply line VDD, and the source S2 Consists of a second transistor Tn2 connected to the output point Y1 and a transistor Tp having a gate G2 connected in series to the output point Y1 side.

Thus, according to the second circuit, the second current buffer circuit 12 is provided at the output point Y1 of the four-input NOR circuit.

For example, when the signal is inverted as in the first circuit, the logic voltage at the output point Y1 is determined based on the current flowing through the transistor Tn2 of the current buffer circuit 12. For this reason,
Similarly to the first circuit, it is possible to minimize the influence of the delay caused by the series-connected transistors Tp as in the conventional example.

Thus, similarly to the first circuit, a high-performance, low-power-consumption multi-input NOR logic circuit device can be manufactured using only the CMOS process.

(Iii) Description of Third Embodiment FIG. 5 is a configuration diagram of a four-input NAND circuit according to a third embodiment of the present invention.

In the figure, a first four-input NAND circuit first includes a power supply line.
Four transistors Tp are connected in parallel between VDD and the output point Y2. Further, four transistors Tn are connected in series between the ground line GND and the output point Y2. Next, the transistor
Each gate Gp of Tp is connected to each gate Gn of the transistor Tn. This connection point is connected to input points X1 to X4.

Up to now, it is the same as the conventional example, but the four input of the present invention
In the NAND circuit, a third current buffer circuit 13 which is an embodiment of the third auxiliary buffer circuit 3 is provided on the power supply side of the NAND circuit.

The third current buffer circuit 13 includes a first transistor Tp
3 and a second transistor Tp4.

The first transistor Tp3 has a drain D3 connected to the drain Dn of the transistor Tn, a source S3 connected to the output point Y2, and a gate G3 connected to the ground line GND.

The second transistor Tp4 has a drain D4 connected to the ground line G.
ND, the source S4 is connected to the output point Y2, and the gate G4 is connected to the drain Dn of the transistor Tn connected in series.

FIG. 6 is an operation explanatory diagram of a four-input NAND circuit according to the third embodiment of the present invention.

In the figure, a third four-input NAND circuit first has an input point
It is assumed that the input signals IN1 to IN3 of X1 to X3 are all at "H" level and the input signal IN4 of input point X4 is at "L" level. The output signal OUT in this case is at the “H” level.

Next, when the input signal IN4 at the input point X4 is inverted from “L” level to “H” level, all the transistors Tn are turned “ON” and all the transistors Tp are turned “OFF”. As a result, the point P2 changes to the “L” level, and the transistor Tp
4 is turned “ON” and the output point Y2 falls to “L” level.

After that, the output point Y2 changes to “L” level,
The point P2 also becomes “L” level, the transistors Tp3 and Tp4 are cut off, and the output signal OUT becomes “L” level.

Here, A in the figure is a forced operation portion, which is a portion improved by the first current buffer circuit 13. Accordingly, it is possible to suppress as much as possible the waveform rounding caused by the delay caused by the series-connected transistors Tp as in the conventional example.

Thus, according to the third circuit of the present invention, the third current buffer circuit 13 is provided on the output point Y2 side of the four-input NAND circuit.

Therefore, it is possible to minimize the influence of the delay caused by the series-connected transistors Tn as in the conventional example.

As a result, a high-performance, low-power-consumption multi-input NAND logic circuit device can be manufactured using only the CMOS process.

(Iv) Description of Fourth Embodiment FIG. 7 is a configuration diagram of a four-input NAND circuit according to a fourth embodiment of the present invention.

In the figure, a fourth 4-input NAND circuit differs from the third circuit in that a fourth current buffer circuit 1 is connected to the ground line GND side of the circuit.
4 is provided.

That is, the fourth current buffer circuit 14 includes the first transistor Tn3 and the second transistor Tn4. The first transistor Tn3 has its source S3 connected to the ground line GND, its drain D3 connected in series to the ground line GND of the transistor Tn connected in series, and its gate G4 connected to the drain Dp of the transistor Tp.

The second transistor Tn4 has its source S4 connected to the ground line GND.
The drain D4 is connected to the drain Dp of the transistor Tp, and the gate G4 is connected to the ground line GND of the transistor Tn connected in series.

Thus, according to the fourth circuit of the present invention, the fourth current buffer circuit 14 is connected to the ground line GND of the four-input NAND circuit.
Is provided.

For example, when the signal is inverted as in the third circuit, the logic voltage at the output point Y2 is determined based on the current flowing through the transistor Tn4 of the current buffer circuit 14. For this reason,
Similarly to the third circuit, it is possible to minimize the influence of the delay caused by the series-connected transistors Tn as in the conventional example.

Thus, similarly to the third circuit, a high-performance, low-power-consumption multi-input NAND logic circuit device can be manufactured using only the CMOS process.

Table 1 is a comparison table of the chip occupied area of the four-input NOR circuit according to the present invention and the conventional example based on the calculation made by the inventor.

[Effects of the Invention] As described above, according to the present invention, the current buffer circuit is provided on the power supply line, the ground line, or the output side of the n-input logic circuit. Can be compensated for.

Therefore, without increasing the size of the p-channel transistor connected in series as in the prior art, the CMOS
It is possible to configure a four-input logic circuit equivalent to the operation speed of the inverter. In addition, only by the CMOS process,
Since an n-input logic circuit having a small-to-medium load capacitance can be formed and the input gate capacitance of the transistor can be suppressed from increasing, power consumption can be reduced and high integration can be achieved.

This greatly contributes to the manufacture of a semiconductor integrated circuit device with high performance and low power consumption.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a semiconductor integrated circuit according to the present invention, FIG. 2 is a configuration diagram of a four-input NOR circuit according to a first embodiment of the present invention, and FIG. FIG. 4 is a diagram illustrating the operation of a four-input NOR circuit according to an embodiment, FIG. 4 is a diagram illustrating the configuration of a four-input NOR circuit according to a second embodiment of the present invention, and FIG. FIG. 6 is a diagram illustrating the operation of the four-input NAND circuit according to the third embodiment of the present invention, and FIG. 7 is a diagram illustrating the four inputs according to the fourth embodiment of the present invention. FIG. 8 is a configuration diagram of a four-input NOR circuit according to a conventional example, and FIG. 9 is an operation explanatory diagram of a four-input NOR circuit according to a conventional example. (Explanation of Signs) 1... First auxiliary buffer circuit 2... 2nd auxiliary buffer circuit 3... 3rd auxiliary buffer circuit 4... 4th auxiliary buffer circuit Tp, Tp1 to Tp4 …… one conductivity type field effect transistor, Tn, Tn1 ~ Tn4 …… opposite conductivity type field effect transistor, GND …… ground line, VDD …… power line, Y1, Y2 …… output point, X1… Xn …… Input points, S1 to S4 ... source, Dp, D1 to D4 ... drain, Gp, Gn, G1 to G4 ... gate.

Claims (4)

(57) [Claims] A plurality of one conductivity type field effect transistors (Tp) are connected in series between a power supply line (VDD) and an output point (Y1), and a ground line (GND) and the output point (Y1) are connected. ), A plurality of opposite conductivity type field effect transistors (Tn) are connected in parallel, each gate (Gp) of the one conductivity type field effect transistor (Tp) and the opposite conductivity type field effect transistor (Tn). )
Gates (Gn) are connected to input points (X1 to X
an n-input logic circuit connected to the n-input logic circuit, wherein a first auxiliary buffer circuit (1) is provided on a power supply side of the n-input logic circuit; (S1) is connected to the power supply line (VDD), and the drain (D1) is connected to the output point (Y
1) a first one conductivity type field effect transistor (Tp) having a gate (G1) connected to the power supply side of the one connection type field effect transistor (Tp) connected in series, respectively.
1) and the source (S2) is connected to the power line (VDD) and the drain (D2)
Is connected to the power supply side of the series-connected one conductivity type field effect transistor (Tp), and the gate (G2) is connected to the output point (Y
A semiconductor integrated circuit comprising a second one-conductivity-type field-effect transistor (Tp2) respectively connected to 1). 2. The n-input logic circuit according to claim 1, wherein a second auxiliary buffer circuit (2) is provided at an output point (Y1) of said n-input logic circuit, wherein said second auxiliary buffer circuit is provided. (2) is the drain (D1)
Are connected to the output point (Y1) of the one-conductivity type field effect transistor (Tp) connected in series, the source (S1) is connected to the output point (Y1), and the gate (G1) is connected to the power supply line (VDD). A first opposite conductivity type field effect transistor (Tn1) and a drain (D2) connected to the power supply line (VDD) and a source (S2), respectively.
Are connected to the output point (Y1), and the gate (G2) is connected to the output point (Y1) side of the series-connected field effect transistor (Tp) of one conductivity type. A semiconductor integrated circuit comprising a transistor (Tn2). 3. A plurality of one conductivity type field effect transistors (Tp) are connected in parallel between a power supply line (VDD) and an output point (Y2), and a ground line (GND) is connected to the output point (Y2). ), A plurality of opposite conductivity type field effect transistors (Tn) are connected in series, each gate (Gp) of the one conductivity type field effect transistor (Tp) and the opposite conductivity type field effect transistor (Tn). )
Gates (Gn) are connected to input points (X1 to X
An n-input logic circuit connected to n), wherein a third auxiliary buffer circuit (3) is provided on the output point (Y2) side of the n-input logic circuit, and the third auxiliary buffer circuit (3) Is the drain (D3)
Is connected to the drain (Dn), the source (S3) is connected to the output point (Y2), and the gate (G3) is connected to the ground line (GND) of the series-connected field effect transistor (Tn) of the opposite conductivity type. A first one conductivity type field effect transistor (Tp3), a drain (D4) connected to the ground line (GND), a source (S4) connected to the output point (Y2), and a gate (G4) connected to the series connection. A semiconductor integrated circuit comprising a first one conductivity type field effect transistor (Tp4) connected to the drain (Dn) of the opposite conductivity type field effect transistor (Tn). 4. The n-input logic circuit according to claim 3, wherein a fourth auxiliary buffer circuit (4) is provided on the ground line (GND) side of the n-input logic circuit, wherein the fourth auxiliary buffer is provided. The circuit (4) includes a source (S3) connected to the ground point (GND), a drain (D3) connected to the ground line (GND) of the opposite conductivity type field effect transistor (Tn) connected in series, and a gate ( G4) is a first opposite conductivity type field effect transistor (Tn3) connected to the drain (Dp) of one conductivity type field effect transistor (Tp), respectively.
And the source (S4) is connected to the ground line (GND) and the drain (D4)
Is connected to the drain (Dp) of the field effect transistor (Tp) of one conductivity type, and the gate (G4) is connected to the ground line (GND) side of the field effect transistor (Tn) of the opposite conductivity type connected in series. A semiconductor integrated circuit comprising a second opposite conductivity type field effect transistor (Tn4).