JPS585611B2 - Lonely Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (Insu
rated Gate Field EffectTr
ansistor (abbreviated as IGFET or MOSFE)
Although it is called T, it will be abbreviated as FET hereafter.

) related to logic circuits using

Traditionally, logic circuits using FETs include complementary symmetrical FET circuits that combine a P-channel type (hereinafter referred to as P-type) FET and an N-channel type (hereinafter referred to as N-type) FET, as shown in Figure 1. It is configured.

Figure 1 shows a logic circuit that obtains an anti-coincidence output signal of A, B + A, B for input signals A and B, which is a so-called exclusive circuit.
The iveOR circuit is used, for example, in an arithmetic circuit or an adder of an electronic computer.

Therefore, the number of semiconductors used in the entire system can be reduced. In addition, achieving lower power consumption and lower prices is
This is naturally the objective imposed on the above logic circuit as well.

Before explaining the logic circuit in Figure 1, let me explain about FETs. Both P-type FETs and N-type FETs control the conductivity of a current path (channel) inside or on the surface of a semiconductor by an electric field that extends directly to the current direction. It is an active three-terminal device, and while the former uses holes as carriers, the latter uses electrons as carriers and current flows between the source and drain.

In general, the source and drain of an EFT are bidirectional elements with almost no difference in electrode structure, like the collector and emitter of a bipolar element (transistor).
The distinction between drains appears in circuit operation.

Since this is a complementary symmetrical circuit of a P-type FET and an N-type FET, the output side is the drain, and the bias power supply side (ground side) is the source.

And VDD is the positive power supply. Set VSS as a negative power supply (ground),
To explain the operation, VDD is set to a "1" level potential. VSS as “
0" level potential. We will use so-called positive logic.

In FIG. 1, P-type FETs 11 and 12 are connected in series between power supply terminal 1 and output terminal 2, and P-type FET 1
3 and 14 are similarly arranged, and between the power supply terminal 3 and the output terminal 2, a series circuit of N-type FETs 15 and 16 and a series circuit of N-type FETs 17 and 18 are provided in parallel.

Input signals A and B are supplied to input terminals 4 and 5, respectively.
It is connected to the gate electrode of 17. Input terminal 5 is directly connected to FETs 13 and 16 and connected to FETs 11 and 18 via inverter 7.

In addition. The inverters 6 and 7 are both circuits composed of two FETs, and the output terminal 2 provides an anticoincidence output of the output signal S=A.B+A.B.

In other words, if the input signals are A=0 and B=0, the P-type FE
T12 and 13 are on (conducting state), and since A=B=1, N-type FETs 17 and 18 are also on, and the other FETs are off (non-conducting state). The output signal S becomes "0" level.

Also, if the input signal is A=1, B=0, then A=0, B=1
Therefore, FETs 13, 14 and 15, 18 are turned on, and the output signal S becomes "1" level.

Also, if the input signals are A=0, B=1, then A=1, B=0
Then, FETs 11 and 12 and FETs 16 and 17 are turned on, and the output signal S becomes "1" level.

Further, if the input signals are A=1 and B=1, A=B=0, FETs 11 and 14 and FETs 15 and 16 are turned on, and the output signal S becomes the "0" level.

Table 1 is a truth table summarizing these anti-coincidence circuit operations, and it is shown that they can be achieved by the logic circuit shown in FIG. 1, which is composed of a total of 12 FETs.

However, in the above logic circuit, four sets of two series FET circuits are used so that each series FET circuit is selectively turned on in each of the four types of input signals. As many as 12 FETs are required, including two inverters for gate control, and if the number of components (FETs) increases when integrated into a circuit, the area occupied by the unit logic function circuit in chip form increases. death. This causes a decrease in the non-defective product rate and an increase in manufacturing costs.

In addition, FETs generally have their own leakage current of several PA to several nA due to the reverse voltage applied to the PN junction. There is a disadvantage that the larger the number of FETs constituting a logic circuit, the greater the power consumption, and in addition to the above point, it has been desired to reduce the number of elements.

This invention was made in view of the above circumstances. The objective is to provide a logic circuit that has a small number of components and has diversified logic circuit functions.

below. An embodiment of the present invention will be described with reference to FIGS. 2 and 3.

In Figure 2, power supply terminal 2 to which positive power supply VDD is applied
1 and the ground potential, a P-type FET 22 and an N-type FET are connected.
23 is connected in series with the series FET circuit 24, P-type FET
25 and an N-type FET 26 are connected in series.

Each series FET circuit 24, 27 has FET 22, 2, respectively.
3 and the gate electrodes of FETs 25 and 26 are commonly connected.
connected to an input terminal 28 to which input signal A is supplied. A connection point between the series FET circuits 24 and 27 is connected to an input terminal 29 to which input signal B is supplied.

P-type FET 2 constituting the series FET circuits 24 and 27
The substrates of 2 and 25 are directly connected to the positive power supply VDD side, that is, the source. Also, N type FET23 and 2
In 6, the substrate is directly connected to the ground side, that is, the source.
Output terminals of series FET circuits 24 and 27, that is, each FET
The drains of 22, 23, 25, and 26 are not connected to the substrate, but diodes D1 to D4 are interposed parasitically. Each of the diodes D1 to D4 is configured to have opposite polarity between the power supply terminal 21 and the ground.

Further, a series FET 32 is provided between the power supply terminal 21 and the output terminal of the series FET circuit 27, and the series FET 32 is formed by connecting a P-type FET 30 and an N-type FET 31 in series.
By connecting the output terminal of the series FET circuit 24 to the input terminal of the ET32. An anticoincidence output S1 is output from the ground point of the FETs 30 and 31 to an output terminal 33.

Note that the terminals 34 and 35 are the series FET circuits 24 and 35, respectively.
27 output terminals.

Also in FETs 30 and 31, the substrate and source are directly connected. Diodes D5 and D6 parasitically interposed between the substrate and drain, which are not directly connected, are connected to D1.
~ As in the case of D4, the polarity is opposite to the power supply VDD.

FIG. 3 is a cross-sectional structural diagram of the logic circuit of the above embodiment specifically constituted by an SOS (silicon on sapphire) MOS type integrated circuit.

In the figure, numeral 36 is a sapphire substrate, and the FETs 22, 23, 25, 26, 30, and 31 are formed by providing a thin silicon layer grown by, for example, heteroepitaxial growth on this substrate, and removing unnecessary silicon by etching. are doing.

The substrate 36 may be any insulating substrate, such as spinel. Unlike ordinary MOSIC, CMOS, etc., individual transistors can be easily separated electrically. The circuit is smaller and consumes less power.

Note that 37 is a silicon oxide film, on which a gate electrode is formed. sauce. A drain electrode is formed by a metal layer, such as aluminum.

The reason why the diodes D1 to D6 shown by broken lines are interposed between the substrate and the drain of each FET is that the substrate and source regions are connected to a conductor on the surface of the substrate 36 or on the side surface of the FET. This is because the wires are formed parasiticly by connecting the wires using the wire.

In FIG. 8, the FET and terminals are all indicated by the same reference numerals in correspondence with those in FIG. 2, and the connection relationship between each terminal and the electrode of the FET is also schematically shown.

Next, the operation of the logic circuit shown in FIG. 2 will be explained.

For example, now. Input signal A to input terminals 28 and 29, respectively.
, B are supplied at the levels of A=0 and B=0, what happens to the output signal S1 appearing at the output terminal 33 will be considered.

The P-type FET 22 of the series FET circuit 24 is in a conductive state, and the N-type FET 23 is in a non-conductive state. Series FET circuit 2
4, that is, the output signal S appearing at the terminal 34.
2 becomes the "1" level.

In addition, in the series FET circuit 27, the P-type FET 25 directly connects the source and the substrate and sets the potential of the substrate to "0".
'', so it is in a non-conducting state along with N-type FET 26, but the source of FET 25. Since the diode D3 parasitically formed between the drains is in the forward direction, the output signal S3 at the output terminal, that is, the terminal 35, appears at the "0" level.

However. The output signal S2 (=1) is applied to its input terminal. A series F whose output signal S3 (=0) is supplied to the second control terminal
In the ET circuit 32, the P-type FET 30 is in a non-conducting state and the N-type FET 30 is in a non-conducting state.
Since ET31 becomes conductive, the output signal S1 appearing at output terminal 33 becomes "0" level.

That is, when the input signal state is A=0 and B=0, the output signal is S=0.

Similarly, if the input signal states are A=1 and B=0. A=
0, B=1, A=1, B=1, the output signal S
1 is summarized as shown in Table 2.

From this second table, input signals A, B and output signals S1, S2,
Expressing the relationship of S3 with a logical formula, S2=A・B=A+B, S3=A・B, S1=S2・S
Since 3=S2+S3, S1=A.B+A.B, and it can be seen that the circuit operates as an anti-coincidence circuit shown in the truth table of Table 1 above.

Next, Figure 4. Another embodiment of the invention shown in FIG. 5 will be described.

The configuration of the logic circuit in Figure 4 is the same as in Figure 2, with 6 FETs.
In this embodiment, three series FET circuits 24, 27, and 32 are formed, and the same parts as in the embodiment shown in FIG. 2 are given the same reference numerals.

And since the arrangement and connection relationship of each FET is exactly the same,
It is clear that when the input signals A and B are supplied to the input terminals 28 and 29, respectively, the signal S1 appearing at the output terminal 33 becomes an anti-coincidence output.

The difference from FIG. 2 is that in addition to the diodes D3 and D3' parasitic to the P-type FET 25 of the series FET circuit 27, the
The point is that a diode D7 is placed between the source and drain of ET25. In this embodiment, as shown in FIG.
This is because it is realized as a normal complementary integrated circuit (CMOS IC) formed on a type semiconductor substrate 40 using selective diffusion technology.

That is, in FIG. 5, the substrate of the P-type FET 25 and the other P-type FETs 22 and 30 are commonly
This is because a type semiconductor substrate 40 is used. This FET25
Source of. The diode D3 is not parasitically formed in one direction between the drains, and the diode D3 of the embodiment shown in FIG.
The diode D7 must be formed by newly providing an N+ type diffusion region 42 in the P well region 41 forming the N type FET 31.

In other words, this is because the substrate potential of the P-type FET 25 cannot be made equal to its source potential as in the case of FIG.

The embodiment of the present invention shown in FIG. 6 is also a logic circuit that performs anticoincidence operation like the above two embodiments.

The difference from the embodiment shown in FIG. 2 is that each series FET circuit 24,
27, 32 P type FET22, 25, 30 and N type FET
The substrates 23, 26, and 31 are each commonly connected to the power supply terminal 21 and the ground. Therefore, FETs 25, 23, and 31 each have a source. Diodes D7, D8, and D9 are formed between the drains.

The configuration of such a logic circuit consists of N-type FETs 23, 26, and 3.
This is necessary in order to realize anticoincidence operation in the case of a complementary integrated circuit where all 1s are formed in a common P-well region. Although the circuit cross-sectional diagram is omitted, the above diode D7
, D8, D9, an extra semiconductor diffusion region must be provided.

However, Figure 4. When compared with the embodiment shown in FIG.
, D8, and D9 are formed.
The circuit area can be reduced.

The three types of logic circuits described above all perform anticoincidence operations, and are uniformly expressed by the logic symbol diagram in FIG.

Three sets of series FET circuits 24, 27, 32 are provided for the input signals A, B input to the input terminals 28, 29, and the output signals S2, S of the respective output terminals 34, 35, 33 are provided.
3, S1 (=A・B+A・B) is obtained.

FIGS. 8a and 8b are a circuit configuration diagram and a logical symbol diagram showing another embodiment of the present invention.

In the same figure a, the power supply terminal 5 to which the positive power supply VDD is applied
Two sets of series FETs connected in series between 1 and ground potential
The circuits 54 and 57 are P type FET52, N type FET53 and P
A type FET 55 and an N type FET 56 are connected in series, whereas a third series FET circuit 62 has a first
The control terminal, that is, the source of the N-type FET 61 is connected to the source of the FET 56 by being grounded, and the second control terminal, that is, the source of the P-type FET 60, is connected to the above-mentioned series FE.
It is connected to the output terminal of the T circuit 54, that is, the connection point between the FETs 52 and 53.

Further, the gates of the N-type FET 61 and the P-type FET 60 are commonly connected and connected to the output terminal of the series FET circuit 57, that is, the connection point between the FETs 55 and 56.

Note that input signals A and B are supplied to input terminals 58 and 59, respectively. The input terminal 58 is connected to each FET 52, 53, 55.
, 56 gates. Input terminal power 59 is series FET
It is connected to the connection point of circuits 54 and 57.

Further, the output terminals 63, 64, and 65 are respectively connected to the output terminals of the series FET circuits 62, 54, and 57, that is, the respective common drain electrodes.

The diodes D1 to D6 shown between the substrate and drain of the six FETs are... Figure 2. Similar to the diode in the embodiment shown in FIG.
It is formed parasitically when an OS is configured with a MOS type integrated circuit.

The logic circuit configured in this manner provides output signals S1, S2, and S3 expressed by the following logical equations in response to input signals A and B, and the circuit operation is as shown in FIG. Since it can be easily understood from what is shown in the following Table 3 according to Table 2 regarding the embodiment shown in FIG. 3, detailed explanation thereof will be omitted.

Note that the logic circuit shown in FIG. 8a is constructed as an SOS type MOS type integrated circuit. Of course, it can also be formed by a normal complementary MOS circuit, that is, by selective diffusion.

FIG. 8b is a logical symbol diagram of the above logic circuit which performs anticoincidence operation. The same reference numerals are given to the parts corresponding to those in FIG.

With such a configuration, any of the above embodiments can be used as 6
An anti-coincidence circuit or a coincidence circuit can be realized by combining two FETs and their parasitic diodes or one to three intentionally configured diodes, whereas the conventional anti-coincidence circuit required 12 FETs. Since the logic circuit is composed of half as many FETs as compared to the previous one, it is possible to further reduce power consumption and price.

Moreover, in each embodiment, not only an anti-coincidence output or a coincidence output is obtained. Since the OR output and AND output of the input signals A and B can be obtained simultaneously as output signals, it is possible to reduce the minimum number of elements, that is, the area occupied within the integrated circuit, and to diversify the logic circuit functions.

Therefore, the logic circuit of the present invention can be easily applied to half adders, half subtracters, etc., and can greatly contribute to improving the degree of integration of arithmetic circuits.

Note that this invention is not limited to the above embodiments. It can be implemented with various modifications and can be widely applied.

As detailed above, according to the present invention, the constituent elements (FET
), it is possible to realize anti-coincidence and coincidence circuits with a minimum number of circuits, and by having other logic functions, it can be widely applied as a logic circuit.In addition, it is possible to reduce the circuit area, reduce the power consumption of integrated circuits, and reduce manufacturing costs. It is possible to provide a logic circuit that can be easily reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a conventional logic circuit that performs anticoincidence operation, and FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention. Figure 3 is an explanatory diagram of a circuit cross section when the same embodiment is constructed using an integrated circuit. FIG. 4 is a circuit configuration diagram showing a second embodiment of the present invention. Fig. 5 is an explanatory diagram of a circuit cross section when the same embodiment is constructed with an integrated circuit, Fig. 6 is a circuit configuration diagram showing a third embodiment of the present invention, and Fig. 7 corresponds to the first to third embodiments. FIGS. 8a and 8b are circuit configuration diagrams and logical symbol diagrams showing another embodiment of the present invention. 24,57...First series FET circuit, 27,
54... Second series FET circuit, 32, 62.
...Third series FET circuit.

Claims (1)

[Claims] 1. An insulated gate field effect transistor (hereinafter abbreviated as FET) of one conductivity type is connected in series with a FET of the opposite conductivity type. Both terminals of this series circuit are used as first and second control terminals, respectively, and the gate electrodes of each FET are commonly connected to serve as an input terminal. In a logic circuit configured using three sets of series FET circuits with the connection point of each FET serving as an output terminal, the first and second series FET circuits are connected in series. The first control terminal of the third series FET circuit is connected to the first control terminal of the first series FET circuit, and the second control terminal is connected to the second series FET circuit.
The input terminal of the third series FET circuit is connected to the output terminal of the T circuit, and the input terminal of the third series FET circuit is connected to the output terminal of the first series FET circuit. The input signal A is connected to the first series FET circuit and the second series FET circuit.
By supplying the input signal B to the connection point of the series FET circuit, an anticoincidence output signal (A・B+A・B) or a coincidence output signal of the input signals A and B is output from the output terminal of the third series FET circuit. A logic circuit characterized in that it obtains (A・B+A・B).