JPS62195922A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease number of circuit components and to improve the circuit integration by constituting a tri-state output circuit comprising CMOS by eight transistors (TRs) except an inverter circuit inverting an output enable signal OE. CONSTITUTION:Sources of P-channel MOSFETs Q1, Q3 are connected to a power supply voltage Vcc and drains of them are connected to a gate of a P-channel MOSFET Q4 of an output CMOS inverter circuit in common respectively and an input data Din is given to one gate and an output enable signal OE is fed to the other gate. Sources of N-channel MOSFETs Q6, Q7 are connected to a ground potential and drains are connected to a gate of an N-channel MOSFET Q8 of the output CMOS inverter circuit respectively in common, and the input data Din is given to one gate and an inverse of signal OE is fed to the other gate. Further, MOSFETs Q2, Q5 are connected in common between drains of the FETs Q1, Q3 and the FETs Q6, Q7. The FETs Q2, Q5 are made conductive when the signal OE is effective.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is applicable to, for example, a logic integrated circuit having a tri-state output circuit using 6MO8 (complementary MO3). It is about effective techniques.

[Conventional technology]

Regarding tri-state output circuits using CMO3, for example, in 1982, Hitachi published “Hitachi CMO
HD62 J/ to S gate array data file
It is listed as the L series.

[Problem that the invention seeks to solve]

FIG. 2 shows a circuit diagram of the tri-state output circuit previously developed by the present inventors.

The output circuit receives input data Din and output enable signal O.
It is composed of a NAND gate circuit receiving E, a NOR gate circuit receiving input data Din and an inverted signal of output enable signal OE, and an output inverter circuit. In the figure, the NAND gate circuit is composed of P-channel MOSFETs Q11 and Q12 and N-channel MOSFETs Q16 and Q17,
NOR gate circuit is P channel MOSFET QI 3
, Q14 and N-channel MOSFET Q1B, Q1
Consisting of 9. In addition, the output inverter circuit consists of P-channel MO5FETQ15 and N-channel MOS
It is composed of FETQ20. Like this, CMO5
The inventors of the present invention have discovered that a tri-state output circuit using the following has the following problems. In other words, when connecting the outputs of multiple output circuits, although it is said that a tri-state output circuit that can simply perform wired OR is effective, the number of circuit elements constituting one output circuit is Ten inverter circuits are required, excluding the inverter circuit for inverting the enable signal OE, which is a factor that hinders high integration.

An object of the present invention is to provide a semiconductor integrated circuit device including a CMO3I-right state output circuit configured with a relatively small number of circuit elements.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
The output CMOS inverter circuit has its source connected to the power supply voltage VCC and its drain commonly connected to the gate of the P-channel O3FET of the output CMOS inverter circuit, and input data Din is connected to one gate and input data is connected to the other gate. Two P-channel MOS FETs receive an output enable signal OE, their sources are commonly connected to the ground potential of the circuit, and their drains are commonly connected to the gate of the N-channel MOS FET of the output CMOS inverter circuit. Input data Din to the gate and output enable signal O to the other gate
Two N-channel MOS F receiving the inverted signal of E
ET and these two P-channel MOS FETs
and a switch MOSFET which is located between the commonly connected drains of the N-channel MO5FET and becomes conductive when the output enable signal OE is valid, forming a tri-state output circuit.

[For production]

According to the above-mentioned means, the tri-state output circuit by the CMO3 can be configured with eight transistors, excluding the inverter circuit for inverting the output enable signal OE, and it is possible to construct a semiconductor such as a logic integrated circuit with an improved degree of integration. An integrated circuit device can be realized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a tri-state output circuit using a CMO3 to which the present invention is applied. Each of the circuit elements shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known CMO5J1 circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel MOS
The FET is made of polysilicon, which is formed on the surface of a semiconductor substrate with a source region, a drain region, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. Consists of a gate electrode. The N-channel MOS FET is formed in a P-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed thereon. The P-type well region has an N well formed thereon.
Configures the substrate gate of the channel MOSFET.

P-channel output MOSFETQ that forms a high-level output signal between the output terminal Dout and the power supply voltage VCC
4 is provided, and an N-channel MO is provided to form a low level output signal between the output terminal Dout and the ground potential of the circuit.
SF ETQ B is provided.

Between the power supply voltage VCC and the gate of the P-channel MOSFETQ4, there are a P-channel MOSFETQ1 whose gate receives input data Din, and a P-channel MOSFETQ1 whose gate receives an output enable signal OE.
ETQ3 is connected in parallel. Also, the ground potential of the circuit and N
Between the gates of channel MOSFETQB is an N-channel MOSFET that receives input data Din at its gate.
TQ6 and an N-channel MOSFETQ7 whose gate receives an inverted signal σ of the output enable signal are connected in parallel. These commonly connected P-channel MOSFs
ETQI and Q3 drain and N-channel MOSF
Between the drains of ETQ6 and Q7, there is an N-channel MOS whose gate receives an output enable signal OE.
P-channel M which receives the inverted signal plane of the output enable signal by the inverter circuit N1 at the FET Q5 and its gate.
O5FETQ2 is connected in parallel.

When the output enable signal OE is high level, P-channel MOSFETQI, Q3 and N-channel MOSFET
ETQ5 and Q6 form a NAND gate circuit of input data Din and output enable signal OE for P-channel MO5FETQ4 of the output inverter circuit. In addition, when the output enable signal OE is low level, P channel MOSFET QI, Q2 and N channel MOSFET
SFETQ6 and Q7 form an N0R gate circuit for input data Din and inverted signal σ1 of the output enable signal for N-channel MOSFETQ8 of the output inverter circuit.

The circuit shown in FIG. 1 has a function as a tri-state output circuit through the following operation. That is, if the output enable signal OE is at a low level and its inverted signal σ is at a high level, both the P-channel MO5FETQ2 and the N-channel MOSFETQ5 are in the off state,
Furthermore, since the P-channel MOS FETQ3 is turned on, a high level voltage such as the power supply voltage VCC is supplied to the gate of the output P-channel MOSFETQ4 via the P-channel MOSFETQ3. This results in
The output P-channel MOS FET Q4 is turned off. In addition, since the N-channel MOSFETQ7 is turned on by the inverted signal of the output enable signal 1, a low level like the ground potential of the circuit is supplied to the gate of the output N-channel MOSFETQ8 via the N-channel MOSFETQ7. be done. As a result, the output N-channel MOSFET Q8 is also turned off. Therefore, the output terminal Dout of this output circuit is brought into a high impedance state regardless of its input data Din.

On the other hand, when the output enable signal OE is at a high level and its inverted signal level is at a low level, the switching MOSFET
As Q2 and Q5 turn on, P channel MOS FETQ3 and N channel MO5F
Both ETQ7 are turned off. At this time, if the input data Din is at a low level of logic "0", the P-channel MOS receives the input data Din at its gate.
F F, T Q 1 is on state, N channel MOS
FETQ6 is turned off. This allows the output MO
The gates of S FETQ4 and Q8 are at high level, and P-channel MOS FETQ4 is in the off state.
N channel MOSFET Q8 is turned on. Therefore, the output terminal Dout of this output circuit has a MOSFET.
A low level is output via ETQ8.

Furthermore, when the output enable signal OE is at a high level and the input data Din is at a high level of logic "1", the P channel MO receives the input data Din at its gate.
S F ETQ 1 is off, N-channel MOSF
ETQ6 is turned on. As a result, the output MOS
The gates of FETQ4 and Q8 become low level, and P
The channel MO5FET Q4 is in the on state, and the N channel MOSFET Q8 is in the off state. Therefore, the output terminal Dout of this output circuit has a MOSFE
A high level is output via TQ4.

As shown in the above embodiment, when the present invention is applied to a tri-stay 1-output circuit of a semiconductor integrated circuit device such as a logic integrated circuit, the following effects can be obtained. That is, (1) a CMOS inverter circuit that receives a signal to be output, a switch MOSFET that is located between the P-channel MOSFET and N-channel MOSFET of this inverter circuit and connects or disconnects both MOSFETs according to the output control signal; A CMOS complementary push-pull output circuit whose gate is connected to the drain of each MOSFET of the same conductivity type in the impark circuit, and a CMOS complementary push-pull output circuit whose gate is connected to the drain of each MOSFET of the same conductivity type in the output circuit, and which is located between the gate and source of each MOSFET of the same conductivity type in the output circuit, and is connected to each other according to an output control signal. By configuring a tri-state output circuit with a switch MOS FET that shorts the gate and source of MOS FETs of the same conductivity type, 0M
An effect can be obtained in that the number of circuit elements of the tri-state output circuit using O3 can be reduced.

(2) Item (1) above provides the effect that the degree of integration of a semiconductor integrated circuit device such as a CMO5 logic integrated circuit including a tri-state output circuit can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, the CMO3 circuit has all the conductivity types of the above embodiments reversed, that is, an N-channel MOS on a P-type substrate.
A FET is formed and a P channel MO is formed in the N type well region.
It may also form an SFET. In this case, the polarity of the power supply voltage may be changed accordingly. In addition, a switch MOS FET consisting of a P-channel MOSFET Q2 and an N-channel MOSFET Q5
may be only one of the MOSFETs, or the inverter circuit N1 for inverting the output enable signal OE may not be provided, and a common inverting signal may be formed outside the output circuit.

In the above explanation, the invention made by the present inventor was mainly applied to logic integrated circuits, which is the background field of application, but the invention is not limited to this, and for example, It can also be used in various control devices, storage devices, etc. The present invention
The present invention is applicable to a semiconductor integrated circuit device having a tri-state output circuit configured with at least 0 MO3.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a CMOS inverter circuit that receives the signal to be output, and a P-channel MOS of this inverter circuit.
A switch MOSFET that is located between the FET and the N-channel MOS FET and connects or disconnects both MO5FETs according to the output control signal, and a CMOS complementary MOSFET whose gate is connected to the drain of each MOS FET of the same conductivity type in the CMOS inverter circuit. MOSFETs of the same conductivity type between the push-pull output circuit and the gate and source of the MOSFETs of the same conductivity type in the output circuit according to the output control signal.
Switch MOS F that shorts between the gate and source of ET
By configuring a tri-state output circuit with ET, the number of circuit elements in the tri-state output circuit using CM OS can be reduced, and the degree of integration of semiconductor integrated circuit devices such as CM OS logic integrated circuits including this can be improved. It is something that can be done.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a 0MO3I state output circuit to which the present invention is applied, and FIG. 2 is a circuit diagram showing a conventional CMO3I state output circuit. Ql-Q4, Qll-Q15...P channel MOS
FET, Q5-Q8, Q16-Q20...N-channel MO5FETSNl-N2...Inverter circuit Din...Input data terminal, Dout...Output data terminal, OE...Output enable signal terminal Fig. 1 Figure 2

Claims (1)

[Claims] 1. A first MOSFET of a first conductivity type and a second MOSFET of a second conductivity type of a CMOS inverter configuration receiving a signal to be output;
and a switch MOSFET that shorts the drain of the second MOSFET, and the first and second MOSFETs.
a first conductivity type output MOSFET and a second conductivity type output MOSFET whose respective gates are coupled to the drain of T;
A complementary push-pull output circuit composed of an ET and the gate and source of the output MOSFET of the first conductivity type is provided, and the gate and source of the output MOSFET of the first conductivity type are short-circuited according to the output control signal. a switch MOSFET of a first conductivity type, and a switch MOSFET of the second conductivity type.
The output MOSFET of the second conductivity type is provided between the gate and the source of the output MOSFET, and outputs the second conductivity type according to the output control signal.
A semiconductor integrated circuit device comprising a tri-state output circuit configured with a second conductivity type switch MOSFET that short-circuits the gate and source of the OSFET. 2. The first conductivity type MOSFET is a P-channel MOSFET.
The SFET and the MOSFET of the second conductivity type are N-channel MOSFETs, and the MOSFET for the switch is
T is an N-channel MO whose source and drain are connected in common, and whose gate receives the above output control signal.
2. The semiconductor integrated circuit device according to claim 1, comprising an SFET and a P-channel MOSFET whose gate receives an inverted signal of the output control signal.