JPH0218960A - Complementary clocked nand circuit - Google Patents

Abstract

PURPOSE:To reduce the occupied area of a circuit so as to improve integration and reduce cost by changing the circuit constitution of a clocked NAND circuit in a semiconductor integrated circuit. CONSTITUTION:In a clocked NAND circuit integrated in a semiconductor, the parallel-series connection part of a P-channel type transistor is changed to longically equivalent series-parallel connection structure. Accordingly, the sharing of source and drain electrodes of each transistor is realized, and further wiring and contact hole for connection between each transistor can be reduced. Hereby, occupied area can be reduced, and switching speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock donand circuit implemented as a semiconductor integrated circuit.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of a clock donand circuit.

This conventional example consists of PMOS transistors T1 and T2 whose sources are connected to a power supply α and whose gates receive digital signals @A and B, respectively, and PMOS transistors T1. NMO8 transistor T5. whose source-drain path is connected in series between the second common drain and ground (GND). T6. T3. T4 and NM
The output (10) is obtained from the connection point of the OSMOS transistor T5.The clock signal φ is input to the gate of the transistor T5, the clock signal φ of the opposite phase is input to the gate of the transistor T6, and the output (10) is input to the gate of the transistor T3. is input with digital signal A, and transistor T4
Digital signal B is input to the gate of .

Next, the circuit operation will be explained.

When the clock signal φ is at low level (0) (i.e.,
When φ is at a high level, PMOS transistor T5 and NMOS transistor No. 6 are both turned off, and the output O becomes a high impedance state regardless of the levels of digital signals A and B.

When the clock signal φ becomes high level, the PMOSMOS
Transistor T5OI and transistor T6 are both turned on,
At this time, when digital signals A and B are both high level, both NMO8 transistors T3゜4 are turned on, and output 0 is low level, and for other combinations, PM
OS transistor T1 or -2 turns on, output ○
is at a high level. Table 1 is a truth table of this conventional example.

FIG. 4 is a diagram showing a layout pattern when the circuit of FIG. 3 is made into a semiconductor integrated circuit.

In FIG. 4, the parts corresponding to those in FIG. 3 are given the reference numerals of the parts shown in FIG. 3 to clarify the correspondence. The goo 1-electrode (the part marked with many dots in the figure) of each transistor is made of, for example, polysilicon, and the wiring 20 is made of, for example, aluminum. The wiring 20 and the source or drain of the transistor are connected through a contact hole 19.

[Problem to be solved by the invention]

When the conventional complementary clock donand circuit described above is implemented as an IC, as shown in FIG. Since these electrodes are located far apart, it takes 1
extra contact holes 19 and wiring 20 are required, and in order to take out the output O, the transistor T
One extra contact hole 19 is required for the drain electrode 14 of PMOS transistor T1°2.7.
5, the occupied area increases,
Furthermore, since the pattern becomes complicated, there is a drawback that the electrical characteristics deteriorate due to an increase in the parasitic surface.

[Means to solve the problem]

In the complementary clock donand circuit of the present invention, the source is the first
A first HOS FET of a first conductivity type is connected to the operating potential point of the first 803 FET and a first digital signal is input to the first 803 FET; a second HOS FET of the first conductivity type into which a signal is input; and a third HOS FET of the first conductivity type whose source is connected to the first operating potential point and whose gate is inputted with a second digital signal.
S FET, and a fourth HOS FET of a first conductivity type whose source is connected to the drain of the third HOS FET and whose gate receives the clock signal,
The drain of the FET and the train of the fourth HOS FET are commonly connected, and the drain of the fourth HOS FET is connected in common.
A fifth. a sixth MOS FET and a seventh MOS FET;
A clock signal having an opposite phase to the clock signal is input to the gate of the FET, and the gate of the sixth and seventh 803F
The first digital signal is input to one of the gates of the ET, and the second digital signal is input to the other gate.

[Effect]

By changing the parallel-series connection of P-channel transistors to a logically equivalent series-parallel connection configuration,
The source and drain electrodes of each transistor can be shared, and the wiring and holes for connecting each transistor can be reduced, thereby reducing the occupied area and improving switching speed. can.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the complementary clock donand circuit of the present invention, and FIG. 2 is a diagram showing a layout pattern when this embodiment is implemented as an IC.

In this embodiment, in the circuit section from PMO81 to MOS transistors, a PMOS transistor T7 is newly added to divide the transistors to which the φ clock signal is input into two, and the A signal gate input transistor 1 and the φ clock signal gate input transistor The transistor T5 is connected in series, one B signal gate input transistor 2 and the φ clock signal gate input transistor T7 are connected in series, and these two series circuits are connected in parallel. It is obvious that this embodiment is logically equivalent to the conventional example, with the only difference being the position of the MOS transistor to which the φ clock signal is input.

In the conventional example, when integrated into an IC, the φ clock signal gate input transistor T5 and the digital signal A are used.

A transistor T1.B is input to the transistor T1. T2 is source,
Although the drain electrode cannot be shared and each transistor has its own source and drain electrode, in this embodiment, as shown in FIG. 2, the transistors T5 and T7 to which the φ clock signal is input are used. and a transistor r1. to which digital signals A and B are input. Since T2 and T2 are connected in series, the source and drain electrodes can be shared. As a result, the number of contact holes can be reduced and unnecessary wiring between transistors can be eliminated. Although the explanation has been given above using an example of a two-man clocked NAND circuit, the present invention is not limited to this.
It is also applicable to clock donand circuits that require more than human power.

〔Effect of the invention〕

As explained above, the present invention has the advantage that, by changing the circuit configuration of a semiconductor integrated circuit, the area occupied by the circuit can be reduced, the degree of integration can be improved, and a low-cost LSI can be manufactured. There is. Furthermore, the pattern shape is simplified and the areas of contact holes and diffusion layers are reduced, thereby reducing parasitic capacitance and enabling high-speed switching speed.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of one embodiment of the complementary clock donand circuit of the present invention, Fig. 2 is a diagram showing a layerer l-pattern when the circuit of Fig. 1 is integrated into an IC, and Fig. 3 is a conventional example. FIG. 4 is a diagram showing a layerer 1 pattern when the conventional circuit of FIG. 3 is integrated into an IC. A, B...Digital gate input signal, φ...Clock signal, φ...Clock reverse phase signal, 0...Transistor output, Vcc...Power supply, GND...Grounding, T
1. T2. T5. T7...P channel type transistor, T3. T4. T6... N-channel transistor, 1 to 18... Source or drain electrode of each transistor, 19... Contact hole, 20... Wiring.

Claims (1)

[Claims] 1. A first MO of a first conductivity type whose source is connected to a first operating potential point and whose gate is inputted with a first digital signal.
a second MOSFET of a first conductivity type whose source is connected to the drain of the first MOSFET and whose gate receives a clock signal;
a third MOSFET of a first conductivity type whose source is connected to the first operating potential point and whose gate receives a second digital signal;
SFET, and a fourth MOSFET of a first conductivity type, the source of which is connected to the drain of the third MOSFET, and the clock signal is input to the gate, the drain of the second MOSFET and the fourth MOSFET. MOS
The drains of the second MOSFET and the fourth MOSFET are commonly connected.
fifth, sixth and seventh MOSFETs of the second conductivity type, the source-drain paths of which are connected in series between the common connection point of the drains of the transistors T and the second operating potential point; 5
A clock signal having an opposite phase to the clock signal is input to the gate of the sixth and seventh MOSFET.
A complementary clock donand circuit configured such that the first digital signal is input to one of the gates of the SFET, and the second digital signal is input to the other gate of the SFET.