JPH0481120A - Cmos level shift circuit - Google Patents

Abstract

PURPOSE:To generate a CMOS level shift circuit with a small element area and excellent high speed performance by providing a couple of series connection circuits each comprising a P-channel MOS TR and an N-channel MOS TR between a power terminal and ground and operating them based on a level of a Si substrate. CONSTITUTION:Two signals whose phase is inverted are inputted respectively to each gate of N-channel MOS TRs 14,15 in a high voltage operation from inverters 10,11 in low voltage operation. The N-channel MOS TRs 14,15 are so designed that the size of the TR is increased nearly twice more than that of the P-channel MOS TRs 12,13 and their threshold voltage is decreased more than 1/2VDD, then one of the Nchannel MOS TRs 14,15 is made conductive and the other is made nonconductive. Thus, the input level to the gate of the P-channel MOS TR is VDD and the TR is surely nonconductive, and therefore no through-current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to CMOS level shift circuits.

2. Description of the Related Art A conventional CMOS level shift circuit will be described below. FIG. 2 shows a conventional example of a level shift circuit.

There is a circuit that uses a P-type MO3 as a driver, and a circuit that lowers the threshold voltage by changing the transistor size ratio of the N-type MOS transistor and the P-type MOS transistor between the power supply terminal and the ground, as shown in FIG.

In the CMOS process, an N-type Si substrate is used, and S
In order to set the i-substrate to the power supply voltage (V D, D ), there is aluminum wiring for VDD around the chip, and VDD is generally used as a reference for mask design.

Further, although the circuit format shown in FIG. 3 has the advantage of having a small number of elements, a through current always flows, resulting in an increase in current consumption when used as an integrated circuit.

Problems to be Solved by the Invention On the other hand, when forming a CMO3 circuit on a wafer on which an N layer of Si is epitaxially grown using a P-type Si substrate,
The 81 board is grounded (GND), and there is a GN around the chip.
Because of the D aluminum wiring, it was not possible to use a Si substrate as a reference, and due to the mask design, a P-type MO3 transistor was used as a driver, which resulted in a large area and poor high-speed performance. .

The present invention solves the above-mentioned conventional problems, and aims to provide a CMOS level shift circuit with low current consumption and based on an 81 substrate.

Means for Solving the Problems The present invention has a pair of P-type MOS transistors and an N-type MOS transistor connected in series between a power supply terminal and ground, and an S
In order to operate with the i-board as a reference, two signals with inverted phases are input from the low voltage section to each gate of the N-type MOS transistor in the high voltage section, and the transistor size of the N-type MOS transistor is changed to that of the P-type MOS transistor. This is a CMOS level shift circuit with a thicker configuration.

Therefore, the threshold voltage is set to 1,・'2・VDD
By lowering the voltage even at low voltage input, the N
In order to make the P-type MOS transistor conductive and non-conductive, and to reduce the through current, the gate of one of the two P-type MOS transistors is connected to the drain of the other. The P-type MOS transistor is reliably cut off only by making the MOS transistor conductive or non-conductive.

According to the present invention, when a P-type Si substrate is used, G
ND (substrate) can be used as a reference, and thereby a CMOS level shift circuit with a small element area and excellent high speed can be created.

Example Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, inverter 10.11 operates at low voltage. The output is N type MO
Connected to each gate of S transistors 14 and 15, respectively. The drains of N-type MOS transistors 1, 4, and 15 are input connected to the respective gates of P-type MOS transistors 13 and 12.

The operation of the CMOS level shift circuit configured as described above will be described below.

First, two signals whose phases are inverted from each other are input from the inverter 10.degree. 11 operating at a low voltage to each gate of the N-type MOS transistors 14 and 15 operating at a high voltage. N-type MOS transistors 14 and 15 are P-type MOS transistors.
Compared to the S transistor 12°13, the transistor size is about twice as thick (and the threshold voltage is 1/2).
・N-type M even with low voltage input by lowering the voltage below VDD
One of the OS transistors 14 and 15 can be in a conductive state and the other can be in a non-conductive state. This conductive N-type MOS
The drain of the transistor is a P-type M whose drain is common to the drain of an N-type MOS transistor in a non-conducting state.
Since it is connected to the gate of the OS transistor, P
The input level to the type MOS transistor is GND, so that it is reliably conductive. Therefore, a P-type MOS transistor whose drain and train are common to an N-type MOS transistor in a conductive state
Since the input level to the gate of the transistor is VDD and the transistor is definitely non-conductive, almost no through current flows.

Effects of the Invention The present invention has the advantage that it can be based on GND (substrate), the element area can be reduced by using an N-type MOS transistor for the driver, it is excellent in high speed, and it is advantageous for connection with bipolar elements. has.

[Brief explanation of the drawing]

FIG. 1 shows a CMOS level shift circuit of the present invention, FIG.
FIG. 3 shows a conventional example of a CMOS level shift circuit. 10.11... Inverter, 12.13...
...P-type MOS transistor, 14, 15, old--
N-type MOS transistor, ■...Input terminal, 0
...Output terminal.

Claims (1)

[Claims] P-type MOS transistor and N-type MO between power supply and ground
A pair of S transistors connected in series are connected in parallel, and the output of each stage of the two-stage connected inverter is connected to each gate of each N-type MOS transistor in the parallel circuit,
Each drain of the same N-type MOS transistor and each gate of each P-type MOS transistor in the parallel circuit are cross-connected to each other, and one of the N-type MOS transistors in the parallel circuit
A CMOS level shift circuit characterized in that an inverter 16 is connected to the drain of the transistor, and the size of each of the N-type MOS transistors is larger than the size of each of the P-type MOS transistors.