JPH114157A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of power consumption and also to change the wiring delay time for a semiconductor integrated circuit where the circuits showing each necessary function are integrated on a semiconductor substrate and connected to each other via wiring. SOLUTION: When the voltage of a low level is applied to a line 6, a transistor TR 21 of a digital circuit 2 is turned on. Then a node C is set at the power voltage level and accordingly the delay time caused between an inverter circuit 1 and its next stage circuit is decreased. When the voltage of a high level is applied to the line 6, the TR 21 is turned off. Then the current supplied from a power supply bypasses the TR 21 and flows to the node C via a resistor 2 of the circuit 2. As a result, the node C is set at the power voltage level or lower due to the drop of voltage caused by the resistor 22. As a result, the delay time caused between the circuit 1 and its next circuit is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a problem of wiring delay time, and more particularly to a technique for reducing power consumption.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, circuits exhibiting required functions are integrated on a semiconductor substrate, and the circuits are connected to each other via wiring such as aluminum. In such a semiconductor integrated circuit, the wiring has a resistance and a capacitance. Therefore, a so-called wiring delay occurs. Here, the wiring delay is the signal transmission time required to transmit a signal from one circuit to another circuit, estimated at the design stage, and the signal transmission time from one circuit to another circuit during actual driving. This means that there is a difference in the signal transmission time required to perform the operation. Therefore, the wiring delay is reduced by adjusting the size of each circuit so that the circuit operates normally.

The adjustment of the circuit size cannot be accurately determined at the design stage. In particular, if a wiring delay larger than estimated at the design stage occurs, the circuit will not operate properly. Therefore, there is a tendency to increase the circuit size in order to ensure safety.

[0004]

As described above, in a semiconductor integrated circuit, the circuit size is increased for safety, and the power consumption is actually increased. In order to cope with such a situation, the present inventor adjusts the wiring delay time by changing the voltage value supplied to the circuit or the current value flowing into the circuit according to the level change of the input signal. I thought that if we could do that, we wouldn't have to bother increasing the circuit size.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described concept, and has as its object to provide a semiconductor integrated circuit capable of changing a wiring delay time while preventing an increase in power consumption.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a circuit having a required function is integrated on a semiconductor substrate, and the circuits are interconnected via wiring. And a means for changing a voltage value applied to the circuit according to a change in the level of an input signal.

According to a second aspect of the present invention, a circuit having a required function is integrated on a semiconductor substrate, and the circuit is input to a semiconductor integrated circuit in which each circuit is connected via a wiring. It is characterized by including means for changing a current value flowing into the circuit according to a change in a signal level.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. Note that FIG. 2 specifically shows only the inverter circuit for convenience of explanation.

Referring to FIG. 1, a semiconductor integrated circuit according to the first embodiment has an inverter circuit 1 for performing a NOT logical function and a voltage applied to inverter circuit 1 according to a change in the level of a digital signal. A digital circuit 2 for changing a value.

The inverter circuit 1 includes a P-type MOS transistor 11 and an N-type MOS transistor 12, and the digital circuit 2 includes a P-type MOS transistor 21.
And a resistor 22.

P-type MOS transistor 11 and N-type MO
The gates of the S transistors 12 are connected to each other, and the input line 3 is connected to the connection midpoint A. Further, the P-type MOS transistor 11 and the N-type MO
The drains of the S transistors 12 are connected to each other, and the output line 4 is connected to this connection midpoint B. Further, the source of the N-type MOS transistor 12 is connected to the ground line 5.

The gate of the P-type MOS transistor 21 is
The source is connected to the control line 6 and the source is connected to the power supply line 7. One end of the resistor 22 is connected to the power line 7
The other end is connected to a P-type MOS transistor 1
1 source. The drain of the P-type MOS transistor 21 is connected to a connection midpoint C (hereinafter, referred to as “node C”) between the source of the P-type MOS transistor 11 and the other end of the resistor 21.

Here, the operation of the semiconductor integrated circuit will be described. When the high voltage V _H1 is applied to the input line 3, the P-type MOS transistor 11 of the inverter circuit 1
Is turned off while the N-type MO of the inverter circuit 1 is
S transistor 12 is turned on. Then,
The low-level signal _SL is output to a subsequent circuit via the output line 4.

On the other hand, when the low voltage V _L1 is applied to the input line 3, the P-type MOS transistor 1 of the inverter circuit 1
1 is turned on, while the N-type M
The OS transistor 12 is turned off. Then, the output to the subsequent circuit via a high-level signal S _H is output lines 4.

At this time, when the low voltage V _L2 is applied to the control line 6, the P-type MOS transistor 21 of the digital circuit 2 is turned on. Therefore, the node C becomes the power supply voltage V _CC . As a result, a delay time generated between the inverter circuit 1 and a subsequent circuit is reduced.

On the other hand, when the high voltage V _H2 is applied to the control line 6, the P-type MOS transistor 21 of the digital circuit 2
Is turned off. Then, the current supplied from the power supply bypasses the P-type MOS transistor 21 and flows to the node C through the resistor 22 of the digital circuit 2. Therefore, the voltage at the node C becomes lower than the power supply voltage V _CC due to the voltage drop caused by the resistor 22. As a result, the delay time generated between the inverter circuit 1 and the circuit at the subsequent stage increases.

That is, in the first embodiment, the digital circuit 2 changes the voltage value applied to the inverter circuit 1 according to a change in the level of the digital signal, so that the inverter circuit 1 and the circuit at the subsequent stage are connected to each other. The delay time generated between them is increased or decreased.

Therefore, the wiring delay time can be adjusted without adjusting the size of the inverter circuit 1 as in the related art. Therefore, it is not necessary to increase the size of the inverter circuit 1 in the sense of safety as in the related art. As a result, power consumption can be reduced. In addition, even after the semiconductor integrated circuit is manufactured, there is a ripple effect that the wiring delay time can be adjusted.

(Embodiment 2) FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 2 of the present invention. Note that FIG. 2 specifically shows only the inverter circuit for convenience of explanation. Referring to FIG. 2, a feature of the semiconductor integrated circuit according to the second embodiment is that the digital circuit 2 changes a current value flowing into the inverter circuit 1 according to a change in the level of the digital signal. The other configuration is the same as that of the first embodiment.

Specifically, the digital circuit 2 is a P-type MO
S transistors 211, 212, and 213 are provided.
The control line 61 is connected to the gate of the P-type MOS transistor 211, and the P-type MOS transistor 21
The control line 62 is connected to the gate of
The control line 63 is connected to the gate of the type MOS transistor 213.

P-type MOS transistors 211, 212,
Each of the sources 213 is connected to the power supply line 7. P-type MOS transistors 211, 212, 2
13 are connected to the P of the inverter circuit 1 respectively.
It is connected to the source of the type MOS transistor 11.

Here, the operation of the semiconductor integrated circuit will be described. When the low voltage _VL3 is applied to all of the control lines 61, 62, and 63, all of the P-type MOS transistors 211, 212, and 213 of the digital circuit 2 are turned on. Then, the bias current of the inverter circuit 1 increases. Therefore, the driving capability of the inverter circuit 1 increases. As a result, a delay time generated between the inverter circuit 1 and a subsequent circuit is reduced.

When a high voltage V _H3 is applied to one of the control lines 61, 62, 63, the P-type MOS transistors 211, 212, 21
Out of 3, the P-type MOS transistor connected to the control line to which the high voltage V _H3 is applied is turned off.
Then, the bias current of the inverter circuit 1 becomes smaller than when the low voltage _VL3 is applied to all of the control lines 61, 62, 63. Therefore, the driving capability of the inverter circuit 1 is controlled by the control lines 61, 62, 63.
Are lower than when the low voltage V _L3 is applied to all of them. As a result, the delay time generated between the inverter circuit 1 and the subsequent circuit is controlled by the control lines 61, 62, 63.
_Are higher than when the low voltage V _L3 is applied to all of them. In this case, power consumption is controlled by the control lines 61 and 6.
In comparison with the case where the low voltage V _L3 is applied to all of
Can be smaller.

Further, when a high voltage V _H3 is applied to two of the control lines 61, 62, 63, the P-type MOS transistors 211, 212, 213 of the digital circuit 2 are applied.
Among them, the P-type MOS transistors connected to the two control lines to which the high voltage V _H3 is applied are turned off. Then, the bias current of the inverter circuit 1 becomes
Of the control lines 61, 62, 63, the voltage is smaller than that when a high voltage V _H3 is applied to one line. Therefore, the driving capability of the inverter circuit 1 is such that one of the control lines 61, 62, 63 has the high voltage V _H3
Is smaller than in the case where is applied. As a result, the delay time generated between the inverter circuit 1 and the circuit at the subsequent stage becomes larger than when the high voltage V _H3 is applied to one of the control lines 61, 62, 63. In this case, power consumption is controlled by the control lines 61 and 6.
2, 63, it can be made smaller than the case where the high voltage V _H3 is applied to one line.

That is, in the second embodiment, the digital circuit 2 changes the value of the current flowing into the inverter circuit 1 in accordance with the change in the level of the digital signal, thereby connecting the inverter circuit 1 to the circuit at the subsequent stage. The delay time generated between them is increased or decreased.

Therefore, the wiring delay time can be adjusted without adjusting the size of the inverter circuit 1 as in the related art. Therefore, it is not necessary to increase the size of the inverter circuit 1 in the sense of safety as in the related art. As a result, power consumption can be reduced. In addition, even after the semiconductor integrated circuit is manufactured, there is a ripple effect that the wiring delay time can be adjusted.

The present invention is not limited to the above embodiments. For example, in the first and second embodiments, a control signal is applied to a transistor between an inverter circuit and a power supply. Although the configuration is made as described above, the same effect can be obtained by inserting a control signal and a digital circuit between the inverter circuit and the ground.

Further, the first and second embodiments are described.
In the above, an example in which a MOS transistor is used has been described. Alternatively, a similar effect can be obtained by using a switching element such as a bipolar transistor.

Further, in the second embodiment, the number of control voltages is three. However, the number of control voltages may be any number as long as it is two or more. The wiring delay time can be adjusted in more stages. In addition, it is needless to say that various design changes and modifications can be made within the scope of the present invention.

[0030]

As is apparent from the above description, claim 1
According to the invention described in the above, the delay time is increased or decreased by changing the voltage value applied to the circuit in accordance with the level change of the input signal, As before, the wiring delay time can be adjusted without adjusting the size of the circuit, and as a result, there is no need to increase the size of the circuit in the sense of safety as in the past. Power consumption can be reduced.

According to the second aspect of the present invention, the delay time can be increased or decreased by changing the value of the current flowing into the circuit according to the level change of the input signal. Since the wiring delay time can be adjusted without adjusting the size of the circuit as in the past, the size of the circuit must be increased in the sense of safety as in the past. As a result, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Inverter circuit 11 P-type MOS transistor 12 N-type MOS transistor 2 Digital circuit 21 P-type MOS transistor 22 Resistance 211 P-type MOS transistor 212 P-type MOS transistor 213 P-type MOS transistor

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which circuits exhibiting required functions are integrated on a semiconductor substrate, and each circuit is connected to each other via a wiring. And a means for changing a voltage value applied to the circuit. 2. A semiconductor integrated circuit in which circuits exhibiting required functions are integrated on a semiconductor substrate, and each circuit is connected to each other via a wiring, according to a change in the level of an input signal. A means for changing a value of a current flowing into the circuit.