JPH08251004A - Output circuit - Google Patents

Abstract

PURPOSE: To provide an output circuit which generates no through current inside irrelevantly when of a high, a low level or high impedance is set for the output potential in an output circuit which operates with a relatively low internal source voltage. CONSTITUTION: The gate of the P MOS transistor(TR) 105 of a 1st transfer gate 110 between a signal generating circuit 101 and a P MOD TR 107 which supplies a current to an output pad part OUT is connected to the output pad part OUT through a 2nd transfer gate 210. The gate of the N type MOS TR 203 of the 2nd transfer gate 210 is connected to an output control terminal nEN. The gate of the P MOS TR 105 of the 1st transfer gate 110 is pulled down by 1st and 2nd N MOS TRs 201 and 202 connected in a cascade.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit which operates at a relatively low power supply voltage, and the output circuit operates at a voltage higher than the power supply voltage in the output circuit (hereinafter referred to as "on-chip power supply voltage"). The present invention relates to an interface when connected to another semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of LSIs, semiconductor devices themselves, particularly gate oxide films, cannot withstand a voltage of 5 V or higher, and the on-chip power supply voltage has become a low voltage of 3 V or lower. However, the on-chip power supply voltage is 3
Even if it is V, if the external LSI connected is a 5V operation product, the output circuit directly connected to this external LSI is affected by 5V. Therefore, it is necessary to design the output circuit to withstand a voltage (5V) higher than the on-chip power supply voltage (3V).

A conventional output circuit will be described below with reference to the drawings. This output circuit is a circuit that outputs a high-level, low-level, or high-impedance potential state, and is devised so that a voltage of 5 V or more is not applied to the gate oxide film of each transistor.

FIG. 2 (a) is a configuration of a conventional output circuit, and FIG. 2 (b) is a schematic diagram of a transient voltage fluctuation state of its internal node.

In FIG. 2A, OUT is an output pad portion to which a signal line of an external LSI operating at a voltage higher than the on-chip power supply voltage is connected. IN and nEN are output control terminals for controlling the potential state of the output pad section OUT, IN is an input terminal from an on-chip circuit, and nEN
Is an enable terminal. VDD is an on-chip power supply, its voltage is, for example, 3V, VDD1 is a power supply having a voltage higher than that of the on-chip power supply, and its voltage is, for example, 5V.
Is. Moreover, NP, NP1, and NN are internal nodes.

Reference numeral 101 is a signal generation circuit for generating a pull-up control signal according to the potentials of the output control terminals IN and nEN. Reference numeral 102 is a NAND gate, and 103 is a NOR gate, which form the signal generation circuit 101.

Reference numerals 105, 106 and 107 denote P-type MOS transistors, and all substrates are connected to VDD1. Reference numerals 104, 108 and 109 denote N-type MOS transistors, and all substrates are grounded.

110 is a transfer gate,
It is composed of an N-type MOS transistor 104 and a P-type MOS transistor 105.

Further, in FIG. 2B, V (IN), V
(NP), V (NP1), V (NN), and V (OUT) indicate transient voltage fluctuations at the input terminal IN, the node NP, the node NP1, the node NN, and the output pad section OUT, respectively.

The operation of the output circuit configured as described above will be described below. In the following description, the high level of the digital signal is "H" and the low level is "L".

To output "H" from the output pad OUT, the enable terminal nEN is set to "L" and the input terminal I
Set N to "H". The second power supply voltage VDD1 is 5V. Then, the output of the NAND gate 102 is "L", N
The output of the OR gate 103 also becomes "L". Since the N-type MOS transistor 104 is in the ON state, the gate potential of the P-type MOS transistor 107 becomes "L", and the P-type M-transistor 107
The OS transistor 107 is turned on. On the other hand, N type MO
Since the output of the NOR gate 103 is "L", the S transistor 109 is turned off, and the output pad section OUT is "H". At this time, the P-type MOS transistor 10
No. 5 is turned off because its gate potential is "H".

Next, when outputting "L" from the output pad OUT, the enable terminal nEN is set to "L" and the input terminal IN is set to "L". Then, the NAND gate 10
2 output, that is, node NP is “H”, NOR gate 1
The output of 03, that is, the node NN also becomes "H". N type M
The OS transistor 109 is turned on and the N-type MOS
Since the transistor 108 is also in the ON state, these N-type MOS transistors in the ON state connected in series start to decrease the potential of the output pad section OUT. Output pad section OUT
The P-type MOS transistor 105 is turned on due to the potential drop. On the other hand, the node NP in the “H” state and the N-type MOS transistor 104 and the P-type MOS transistor 105 in the on-state make the P-type MOS transistor 107.
Has a gate potential of "H" and is turned off. Therefore, the output pad section OUT becomes "L".

The P-type MOS transistor 105 has a gate potential of 0V and a substrate potential of 5V, and it seems that 5V is applied to the gate oxide film, but since the node NP is "H", the channel potential is It has an on-chip power supply voltage (3V), and the P-type MOS transistor 105
5V is not applied to the gate oxide film.

Next, when the high impedance state is set, the enable terminal nEN is set to "H". Then N
The output of the AND gate 102 is "H", and the NOR gate 10
The output of 3 becomes "L" and the N-type MOS transistor 109
Is turned off. When the output pad section OUT has a voltage of 5V, which is higher than the on-chip power supply voltage, the P-type MOS transistor 106 is turned on, and the gate potential of the P-type MOS transistor 107 becomes 5V. The P-type MOS transistor 105 is off, and the N-type MOS transistor 10
Since the gate potential of 4 is an on-chip power supply voltage lower than 5V, the gate potential of the P-type MOS transistor 107 is 5V.
The potential does not propagate to the NAND gate 102 and no leak current occurs. In addition, the P-type MOS transistor 10
Since the gate potential 7 and the substrate potential 7 are in an off state of 5 V, the output pad portion 7 is connected to the P-type MOS transistor 1
No leak current is generated to the on-chip power supply through 07. Further, the drain potential of the N-type MOS transistor 108 is 5V, but since the gate potential is the on-chip power supply voltage (3V), 5V is not applied to the gate oxide film. The source potential Vd of the N-type MOS transistor 108 is the on-chip power supply voltage V (VDD),
If the threshold voltage considering the substrate bias effect of the N-type MOS transistor is Vtn ′, then Vd = V (VDD) −Vtn ′, and 5V is not applied to the gate oxide film of the N-type MOS transistor 109.

Further, when the output pad portion OUT becomes 0 V in the high impedance state, the P-type MOS transistor 105 is turned on and the P-type MOS transistor 106 is turned on.
Is turned off, and the P-type MOS transistor 107 is turned off when the gate potential is “H”.

As described above, the conventional output circuit has a structure for preventing the application of a voltage of 5 V to the gate oxide film of each transistor and for preventing the generation of a leak current.

[0017]

However, in the above configuration, when the output pad section OUT is to be changed from "H" to "L", a through current is temporarily generated from the on-chip power supply to the ground. I have a problem.

That is, when the output pad portion OUT is to be changed from "H" to "L", the output of the NAND gate 102, that is, the node NP changes from "L" to "H", but the P-type MOS transistor 105 is used. Is off because the gate potential is "H". Therefore, P-type MOS
The gate potential V (NP1) of the transistor 107 is V (NP1) = V (VDD) −Vtn ′. If the threshold voltage of the P-type MOS transistor is Vtp, the P-type MOS transistor 107 is turned off when the gate potential V (NP1) is V (NP1) ≧ V (VDD) − | Vtp |. However, the N-type MOS transistor 104
Since the source potential of is close to the on-chip power supply voltage V (VDD), the threshold value becomes large due to the substrate bias effect, so that Vtn ′ ≧ | Vtp |. Therefore, V (NP1) = V (VDD) −Vtn ′ ≦ V (VDD)
Since − | Vtp | may occur, the P-type MOS transistor 107 may not be in the off state. Therefore, the P-type MOS transistor 107 and the N-type MOS transistors 108, 1
09 are all in the ON state, and a through current is generated from the on-chip power supply to the ground.

This through current continues until the P-type MOS transistor 107 is turned off. That is, the P-type MOS transistor 107 in the state where the through current is generated.
Since the gate-source voltage is small, the on-resistance is large, and therefore the potential V (OUT) of the output pad section OUT gradually drops. Assuming that the threshold voltage considering the substrate bias effect of the P-type MOS transistor is Vtp ′, when the potential V (OUT) of the output pad OUT becomes V (OUT) ≦ V (VDD) − | Vtp ′ | The transistor 105 is turned on, and the gate potential V of the P-type MOS transistor 107
(NP1) becomes V (NP1) ≧ V (VDD) − | Vtp |, the P-type MOS transistor 107 is turned off, the through current disappears, and the potential of the output pad OUT also becomes the ground potential.

FIG. 2 (b) shows the state in which this shoot-through current occurs by the potential of each node. As shown in the figure, the potential V (IN) of the output control terminal IN changes from "H" to "L", and the potential V (NP) of the node NP changes from "L" to "H".
Even if it changes to, the P-type MOS transistor 105 cannot be turned on immediately, so the potential V (NP
It takes a certain amount of time for 1) to reach the "H" level. That is, the timing for completely turning off the P-type MOS transistor 107 is delayed. During this delayed time, the P-type MOS transistor 107 and the N-type MOS transistor 109 are turned on at the same time, and a through current is generated.

If a through current is generated from the on-chip power supply VDD to the ground, there is a problem in that a malfunction occurs due to a momentary potential drop of the on-chip power supply and an increase in power consumption. Further, since the potential of the output pad section OUT does not drop immediately, there is a problem that the delay time increases.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an output circuit in which the through current from the on-chip power supply to the ground is small.

[0023]

In order to solve the above-mentioned problems, the output circuit of the present invention includes a first transfer gate between a signal generation circuit and a P-type MOS transistor supplied to an output pad section. The gate of the P-type MOS transistor is connected to the output pad section via the second transfer gate, and the P-type M of the second transfer gate is connected.
The gate of the OS transistor is the on-chip power supply voltage,
The gate of the N-type MOS transistor of the second transfer gate is connected to the output control terminal, and
The gates of the P-type MOS transistors of the transfer gates are connected to the first and second N-type M-type transistors connected in cascade.
The gate of the first N-type MOS transistor connected in cascade is pulled down by an OS transistor, and the gate of the first N-type MOS transistor is set to an on-chip power supply voltage.
The gate of the N-type MOS transistor is connected to the output control terminal.

[0024]

With the above structure, even when the output pad OUT is to be changed from "H" to "L", the P-type MOS transistor of the first transfer gate is the N-type MOS transistor having the gates cascade-connected. Since it is pulled down, it is turned on. For this reason,
Since the gate potential of the P-type MOS transistor supplied to the output pad section is turned off at the on-chip power supply voltage V (VDD), it is possible to prevent the occurrence of a through current from the on-chip power supply to the ground.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

1 (a) and 1 (b) are schematic diagrams of the configuration of the output circuit in the first embodiment of the present invention and the transient voltage fluctuation state of its internal node, respectively.

In FIG. 1A, OUT is an output pad portion to which an external signal line having a voltage higher than the on-chip power supply voltage can be connected. IN, EN, and nEN are output control terminals for controlling the output pad section OUT, and
Is an input terminal from the on-chip circuit, and EN and nEN are enable terminals. Note that nEN is an inverted signal of EN. VDD is an on-chip power supply, and in this embodiment, 3V,
VDD1 is a power supply having a voltage higher than that of the on-chip power supply and is 5V in this embodiment. Further, NP, NP1 and NN indicate internal nodes.

Further, 101 is output control terminals IN and n.
It is a signal generation circuit that generates a pull-up control signal according to the potential of EN. 102 is a NAND gate, 103 is N
It is an OR gate, and these constitute the signal generation circuit 101.

Further, 105, 106, 107, 204
Is a P-type MOS transistor, the substrate of which is connected to the second power supply voltage VDD1.

Further, 104, 108, 109, 20
1, 202 and 203 are N-type MOS transistors,
In both cases, the substrate is connected to the ground potential. Also N type M
OS transistors 108 and 109, and N-type MO
The S transistors 201 and 202 are connected in cascade.

Of these transistors, the first P-type MOS transistor 107 has a role of receiving the signal output from the signal generating circuit 101 at the control terminal and supplying the power supply voltage VDD to the output pad section OUT. 1 N type M
The OS transistor 109 has a role of receiving a signal output from the signal generation circuit 101 at a control terminal and lowering the potential of the output pad portion OUT. The control terminal of the first N-type MOS transistor 109 has an on-chip power supply voltage VD.
The N-type MOS transistor 108 connected to D is cascade-connected.

Reference numeral 110 is a first transfer gate, which is composed of a second N-type MOS transistor 104 and a second P-type MOS transistor 105. The first transfer gate 110 is connected to the output of the NAND gate 102 and the first P-type MOS transistor 107.
The conduction / non-conduction with the control terminal of is controlled. The control terminal (gate terminal) of the second N-type MOS transistor 104 is connected to the on-chip power supply voltage VDD. Further, the control terminal of the second P-type MOS transistor 105 is connected to the output pad portion OUT via the second transfer gate 210, and at the same time the N-type MO transistor 105 is connected.
It is also connected to the ground potential via the S transistor 201 and the fourth N-type MOS transistor 202. In this embodiment, the configuration different from the conventional one is such that the control terminal of the second P-type MOS transistor 105 is connected to the output pad section O.
Second transfer gate 21 without direct connection to UT
0 and the N-type MOS transistor 20
The point is that they are connected to the ground potential via the first and fourth N-type MOS transistors 202.

The second transfer gate 210 includes a third N-type MOS transistor 203 and a third P-type MOS transistor.
It is composed of the transistor 204. The second transfer gate 210 controls conduction / non-conduction between the output pad section OUT and the control terminal of the second P-type MOS transistor 105. The control terminal of the third N-type MOS transistor 203 is connected to the output control terminal nEN, and the control terminal of the third P-type MOS transistor 204 is connected to the on-chip power supply voltage VDD.

Further, the fourth N-type MOS transistor 20
The second control terminal is connected to the terminal EN that outputs an inverted signal of the output control terminal nEN. An N-type MOS that is cascade-connected to the fourth N-type MOS transistor 202
The control terminal of the transistor 201 is the on-chip power supply voltage V
It is connected to DD.

The output pad section OUT and the first P-type M
The control terminal of the OS transistor 107 is the fourth P-type MOS whose control terminal is connected to the on-chip power supply voltage VDD.
They are connected to each other via transistors.

In FIG. 1 (b), V (IN), V (N
P), V (NP1), V (NN), and V (OUT) are input terminal IN, node NP, node NP1, node NN, respectively.
This is a transient voltage fluctuation of the output pad section OUT.

The operation of the output circuit configured as described above will be described below. Output pad OU
When outputting “H” from T, enable terminal EN is set to “H”, nEN is set to “L”, and input terminal IN is set to “H”.
To The second power supply voltage is 5V. Then NAN
The output of the D gate 102 becomes "L", and the output of the NOR gate 103 also becomes "L". On the other hand, since the second transfer gate 210 is off and the N-type MOS transistors 201 and 202 are on, the gate of the P-type MOS transistor 105 is pulled down to be on.
Since the N-type MOS transistor 104 is also in the ON state, the gate potential of the P-type MOS transistor 107 becomes "L" and the P-type MOS transistor 107 is in the ON state.
On the other hand, the N-type MOS transistor 109 is turned off, and the output pad section OUT becomes "H".

Next, when outputting "L", the enable terminal EN is set to "H", nEN is set to "L", and the input terminal IN is set to "L". Then, the output of the NAND gate 102, that is, the node NP is “H”, and the NOR gate 103
Output, that is, the node NN also becomes "H". As in the case of outputting “H”, the second transfer gate 21
0 is in the off state, and the N-type MOS transistor 20
Since 1,202 is on, the P-type MOS transistor 105 is on. N-type MOS transistor 10
Since 4 is also on, the gate potential of the P-type MOS transistor 107, that is, the node NP1 becomes "H", and the P-type MOS transistor 107 is turned off. On the other hand, N
Type MOS transistor 109 is in an ON state, and an N type M transistor
Since the OS transistor 108 is also in the ON state, the output pad section OUT becomes "L".

As described above, when outputting "L",
In the conventional example, the potential V (OUT) of the output pad section OUT
However, the P-type MOS transistor 105 was turned on only when V (OUT) ≦ V (VDD) − | Vtp ′ |, whereas the transfer gate 210 is provided in this embodiment. Output pad section OUT
Can be cut off from the potential of the control terminal of the P-type MOS transistor 105. Therefore, when the N-type MOS transistor 202 is turned on, the control terminal of the P-type MOS transistor 105 is set to "L" without depending on the potential V (OUT) of the output pad section OUT which is at "H" level. It can be lowered to the level, and the P-type MOS transistor 105 can be turned on. As a result, the node NP in the "H" level state and the control terminal of the P-type MOS transistor 107 can be surely brought into conduction.
That is, the P-type MOS transistor 107 can be surely turned off. Therefore, the P-type MOS transistor 107 does not turn on at the same time as the N-type MOS transistors 108 and 109, so that no through current is generated from the on-chip power supply to the ground.

Although the P-type MOS transistor 105 has a gate potential of 0V and a substrate potential of 5V, it is in the ON state and the channel potential becomes the on-chip power supply voltage (3V), so that 5V is applied to the gate oxide film. There is no worry, and this point is the same as the conventional example.

FIG. 1B shows the state of the potential change at each node at this time. As shown in the figure, when the potential V (IN) of the output control terminal IN changes from "H" to "L" and the potential V (NP) of the node NP changes from "L" to "H", P Since the MOS transistor 105 is immediately turned on, the potential V (NP1) of the node NP1 is also immediately set to the “H” level. That is, the P-type MOS transistor 107 is completely turned off without delay. Therefore, the P-type MOS transistor 107 and the N-type MOS transistor 109 are not turned on at the same time, and no through current is generated.

Next, when the output pad section OUT is set to the high impedance state, the enable terminal EN is set to "L".
Then, nEN is set to "H". Then, NAND gate 1
The output of 02 is "H", the output of the NOR gate 103 is "L", and the N-type MOS transistor 109 is turned off. Further, the N-type MOS transistor 202 is turned off and the N-type MOS transistor 203 is turned on.

At this time, if the potential of the external circuit connected to the output pad portion OUT is a sufficiently low potential such as 0V, first, the P-type MOS transistor 106 is turned off. Further, since the N-type MOS transistor 203 is in the ON state, the potential 0V of the output pad portion OUT is supplied to the control terminal of the P-type MOS transistor 105, and P
The type MOS transistor 105 is turned on. Therefore, the gate potential of the P-type MOS transistor 107 becomes "H" because the potential of the node NP is transmitted. That is, the P-type MOS transistor 107 is also the N-type MOS transistor 1
The output pad section OUT is in a high impedance state as in 09.

When the potential of the external circuit connected to the output pad section OUT becomes 5 V, which is higher than the on-chip power supply voltage, the P-type MOS transistor 106 is turned on, and the gate potential of the P-type MOS transistor 107. Is 5V. As a result, the P-type MOS transistor 107 can be turned off and the output pad section OUT can be brought to a high impedance state. At this time, since the P-type MOS transistor 204 is also in the ON state and the N-type MOS transistor 202 is in the OFF state, the gate potential of the P-type MOS transistor 105 is 5V.
Therefore, the P-type MOS transistor 105 is in the off state, and the N-type MOS transistor 104 also has a gate potential of 5
Since the on-chip power supply voltage (3V) is lower than V and it is in the off state, the gate potential of 5V of the P-type MOS transistor 107 does not propagate to the NAND gate 102 and no leak current occurs. That is, according to this configuration,
Even when the external circuit operates at 5 V, which is higher than the on-chip power supply voltage, when the output pad section OUT is set to the high impedance state, the transfer gate and the transistor can properly protect the internal circuit.

At this time, the P-type MOS transistor 1
Since 07 is in the off state where the gate potential and the substrate potential are 5V, even if the potential of the output pad OUT is 5V, P
No leak current is generated to the on-chip power supply through the MOS transistor 107.

Further, the drain potential of the N-type MOS transistor 108 is 5V, but since the gate potential is the on-chip power supply voltage (3V), there is no risk of applying 5V to the gate oxide film. The source potential Vd of the N-type MOS transistor 108 is the on-chip power supply voltage V (VD
D), assuming that the threshold voltage in consideration of the substrate bias effect of the N-type MOS transistor is Vtn ', Vd = V (VDD) -Vtn', and 5V is not applied to the gate oxide film of the N-type MOS transistor 109. .

Similarly, the drain potential of the N-type MOS transistor 201 is 5V, but since the gate potential is the on-chip power supply voltage, 5V is not applied to the gate oxide film. Further, the source potential of the N-type MOS transistor 201 becomes V (VDD) −Vtn ′, and 5V does not apply to the gate oxide film of the N-type MOS transistor 202.

Further, when the output pad OUT becomes 0V in the high impedance state, the P-type MOS transistor 105 is in the ON state and the P-type MOS transistor 107 is in the ON state.
Is turned off when the gate potential is "H".

Incidentally, the first transfer gate 110
May have a clocked inverter configuration.

In the above embodiment, the N-type MOS transistors 201 and 202 and the N-type MOS transistor 10 are used.
Although 8 and 109 are configured as a cascade connection, this is to protect the gate oxide film of the N-type MOS transistors 109 and 202, and is not directly related to the prevention of the generation of the through current which is the object of the present invention. Therefore, these N
The type MOS transistor is more preferable if it is in a cascade connection, but it is not necessarily limited to this configuration and may function as a pull-down means for pulling it down to the ground potential.

[0051]

As described above, according to the output circuit of the present invention, the P-type MOS is independent of the potential of the output pad section.
Since the transistor is turned off, the P-type MOS transistor is not turned on at the same time as the N-type MOS transistor, and a through current is not generated from the on-chip power supply to the ground. Therefore, it is possible to prevent malfunction due to momentary potential drop of the on-chip power supply, increase in power consumption, and increase in delay time because the potential of the output pad portion does not drop immediately.

[Brief description of drawings]

FIG. 1A is a diagram showing a configuration of an output circuit in a first embodiment of the present invention, and FIG. 1B is a diagram showing a transient voltage fluctuation state of an internal node thereof.

FIG. 2A is a diagram showing a configuration of a conventional output circuit, and FIG. 2B is a diagram showing a transient voltage fluctuation state at an internal node.

[Explanation of symbols]

 101 signal generation circuit for generating pull-up control signal 102 NAND gate 103 NOR gate 104 N-type MOS transistor 105-107 P-type MOS transistor 108, 109 N-type MOS transistor 110 First transfer gate 201-203 N-type MOS transistor 204 P-type MOS transistor 210 Second transfer gate OUT Output pad section IN Input terminal from on-chip circuit nEN Enable terminal VDD On-chip power supply VDD1 Power supply of higher voltage than on-chip power supply NP, NP1, NN Internal node V (IN) input Transient voltage fluctuation of terminal IN V (NP) Transient voltage fluctuation of node NP V (NP1) Transient voltage fluctuation of node NP1 V (NN) Transient voltage fluctuation of node NN V (OUT) Output pad section O Transient voltage fluctuation of T

Claims (1)

[Claims] 1. An output pad section to which an external signal line is connected, an output control terminal for supplying a control signal, a signal generation circuit for generating a control signal according to the potential of the output control terminal, and the signal. A first P-type MOS transistor that receives a control signal of a generation circuit and supplies a power supply voltage to the output pad section, and a first N-type that receives a control signal of the signal generation circuit and lowers the potential of the output pad section. A MOS transistor is provided, and the potential state of the output pad section is changed to a high level, a low level, or a high impedance state according to the on / off operation of the first P-type MOS transistor and the first N-type MOS transistor. Which is a second P-type MO.
The first P gate is formed via a first transfer gate composed of an S transistor and a second N-type MOS transistor.
Type MOS transistor, the control terminal of the second N-type MOS transistor is an on-chip power supply voltage, and the control terminal of the second P-type MOS transistor is the third P-type MOS transistor and the third P-type MOS transistor. 3 N-type MOS
The third P-type MO transistor is connected to the output pad section via a second transfer gate formed of a transistor.
The control terminal of the S transistor is an on-chip power supply voltage,
The control terminal of the third N-type MOS transistor is connected to the output control terminal, and the control terminal of the second P-type MOS transistor is connected to the fourth N-type MOS transistor for lowering the potential.
Type N-type MO transistor
The control terminal of the S transistor is connected to the output control terminal, and the control terminal of the first P-type MOS transistor is connected to the output pad through a fourth P-type MOS transistor whose control terminal is an on-chip power supply voltage. The substrate potentials of the first to fourth P-type MOS transistors are higher than the on-chip power supply voltage, and the substrate potentials of the first to fourth N-type MOS transistors are ground potentials. An output circuit characterized by the above.