JPS5931864B2 - Complementary insulated gate semiconductor circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to complementary insulated gate semiconductor circuits.

In a complementary insulated gate semiconductor circuit (hereinafter abbreviated as a CMOS circuit), input/output terminals are generally used as an input protection circuit, and are clamped from a ground point to within a power supply voltage by a provided diode. If a voltage higher than the power supply voltage is applied to this input/output terminal for this diode (a PN junction diode formed on a semiconductor single crystal substrate and made up of a semiconductor region with the opposite polarity to the substrate), it will operate similar to a thyristor. A so-called latch-up occurs when the power supply current flows abnormally and cannot be recovered unless the power supply voltage is turned off. Generally commercials
As mentioned above, the input and output of the OS are clamped to the power supply voltage by diodes, so if a voltage higher than the power supply voltage is applied to the input/output terminals, a forward current flows, creating a parasitic bipolar transistor and damaging the internal circuit. A malfunction may occur, or a circuit similar to a thyristor may occur, causing excessive power supply current to flow.
Destroy devices and reduce reliability. This can easily be solved by clamping the input and output power supply sides with insulated gate transistors instead of protecting them with diodes. However, in the tri-state output or input/output common terminal, since the output consists of P-channel type and N-channel type insulated gate transistors, SOS (formed on sapphire)
When P-channel type and N-channel type insulated gate transistors (hereinafter abbreviated as MOS transistors) are formed on a semiconductor substrate that is not separated by an insulator, as in the case of type CMOS, the power supply side is also inevitably affected. , clamped to the power supply voltage by a diode. SUMMARY OF THE INVENTION An object of the present invention is to provide a complementary insulated gate semiconductor circuit that is free from latch-up and malfunction of internal circuits when input voltages to output terminals, particularly input/output terminals, are higher than the power supply voltage. The present invention will be explained below using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which P channel M
Connect the power source V to the source (contact 0) of the OS transistor Tl, input the signal 11 to the gate (contact 2), connect the base of the NPN transistor T2 to the drain (contact 3), and connect the collector of the transistor T2 to the power source. V, the emitter (contact 5) is connected to the drain of the N-channel NOS transistor T3, the source of the transistor T3 is grounded (contact 6), the signal 12 is input to the gate, and the contact 5 is connected to the output terminal 01. This is a circuit that does this.

When 11 and 12 are in-phase inputs, that is, when both 11 and 12 are at high level, output 01 is at low level; conversely, when both 12 are at low level, output 01 is at high level, and when 11 is at high level and 12 is at low level, the MOS transistor Ti and T3 become non-conductive, resulting in an output high impedance state.

(When the output is high level, low level, or high impedance in this way, it is called tri-state output.)
FIG. 2 shows a cross-sectional view of a device in which the circuit of FIG. 1 is formed on an N-type single crystal substrate.

However, the field insulating film was omitted. Numbers 1 to 6 correspond to contacts 1 to 6 in FIG. 1 and indicate electrical wiring.

13 is an N-type semiconductor single crystal substrate; 14 is a P-type diffusion region in the N-channel region; 15 is a P+ diffusion layer in the source or drain region of the P-channel; 16 is an N+ diffusion layer in the source or drain region of the N-channel; A gate electrode conductor (aluminum, polycrystalline silicon, etc.), and 18 a gate insulating film (silicon oxide, etc.).

As a channel stopper, N+ is diffused (or ion-implanted) into the N-type substrate and P+ into the P well region, but these are omitted as they are not relevant to this explanation. As shown in this figure, the output terminal is connected only to the N+ diffusion layer, so
For a positive voltage, the NP junction diode has a reverse voltage and the parasitic bibolar transistor is non-conducting.
Even if a suitable voltage higher than the V1 power supply voltage is applied (T3 M
OS transistor is in a non-conducting state) to prevent latch-up or malfunction. FIG. 3 is a circuit diagram showing another embodiment.
Since the S transistor T1 becomes non-conductive and the MOS transistor T2 does not immediately become non-conductive due to the charge accumulated here, an N-channel MOS transistor T5 is provided between the contact point 3 and the ground point, and the input signal is in phase with 11. Alternatively, the charge at contact 3 can be immediately discharged using the same signal. FIG. 3 shows a circuit diagram when the I signal is input.

The circuit connection in Figure 3 will be explained. It consists of a P-channel MOS transistor T4, an N-channel MOS transistor T5, and an Npn transistor T6.
Connect the source of T4 and the collector of T6 (contact 7) to power supply 2, connect the drain of T4 and T5 and the base of T6 (contact 9), input the input signal 13 to the gate of T4 and T5 (contact 8), This circuit connects the drain (contact 11) of emitter T7 of T6, makes this point the output terminal 02, and connects the sources of T5 and T7 to ground (contact 12).When the input signals of 13 and 14 are in phase, the output is It is inverted and becomes H or L level, and becomes a high impedance state when 13 is at H level (V2 voltage level) and 14 is at L level (ground potential).

FIG. 4 shows the signals of inputs 13 and 4 and the output waveform of output 02. In the case of a silicon PN junction, the output H level appears as low as about 0.6V from the current voltage. Although the complementary MOS circuit formed on the N-type semiconductor substrate has been described above, the same applies to the P-type semiconductor substrate, only the polarity of the voltage is reversed. As explained in detail above, according to the present invention, without requiring particularly complicated steps,
Further, since a CMOS circuit that does not cause latch-up or malfunction due to parasitic bipolar elements can be realized without sacrificing characteristics such as operating speed, this has a significant effect on improving the reliability of the CMOS circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a cross-sectional view of a device in the circuit of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. FIG. 4 is an input/output waveform diagram of the circuit of FIG. 3; Tl, T4...P channel MOS transistor, T2, T6...NPn transistor, T,,
T5, T7... N-channel MOS transistor, Vl, 2... Power supply voltage (or terminal), 11,
12, 13, 14... Input voltage, 01, 02.
...Output voltage (or terminal), 1, 2...
, 12...Contact (or wiring), 13...
・N-type semiconductor single crystal substrate, 14...P-type diffusion region, 15...P+ diffusion layer, 16...N
+7 diffusion layers, 17... conductor for gate electrode, 1
8...Gate insulating film.

Claims (1)

[Claims] 1 a bipolar transistor, a first field effect transistor connected in series to the bipolar transistor and having a first signal applied to its gate, and a source or drain connected to the base of the bipolar transistor and a second signal applied to the gate; A semiconductor circuit having a second field effect transistor applied thereto and obtaining an output signal from an intermediate junction between the first field effect transistor and the bipolar transistor.