JPS5931864B2 - Complementary insulated gate semiconductor circuit - Google Patents
Complementary insulated gate semiconductor circuitInfo
- Publication number
- JPS5931864B2 JPS5931864B2 JP51108071A JP10807176A JPS5931864B2 JP S5931864 B2 JPS5931864 B2 JP S5931864B2 JP 51108071 A JP51108071 A JP 51108071A JP 10807176 A JP10807176 A JP 10807176A JP S5931864 B2 JPS5931864 B2 JP S5931864B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- transistor
- circuit
- insulated gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000000295 complement effect Effects 0.000 title description 5
- 230000005669 field effect Effects 0.000 claims 3
- 239000000758 substrate Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 本発明は相補型絶縁ゲート半導体回路に関する。[Detailed description of the invention] The present invention relates to complementary insulated gate semiconductor circuits.
相補型絶縁ゲート半導体回路(以下CMOS回路と略記
する)において、入出力端子を一般に入力保護回路とし
て、設けられているダイオードで接地点から電源電圧内
にクランプされている。このダイオード(半導体の単結
晶基板上に形成された基板と逆極性の半導体領域よりな
るPN接合ダイオード)のため電源電圧以上の電圧をこ
の入出力端子に加えると、サイリスタと同様な動作を起
こし、電源電流が異常に流れ、電源電圧を切らないと回
復しない、いわゆるラッチアップが生じる。一般にCM
OSの入出力は、前記のようにダイオードで電源電圧に
クランプされているため、入出力端子に電源電圧以上の
電圧を加えると順方向電流が流れ、寄生バイポーラ・ト
ランジスタが出来て、内部回路が誤動作したり、またサ
イリスタと同様な回路が生じ、過大の電源電流が流れ、
デバイスを破壊したりして信頼性の低下をもたらす。こ
のためには、入力保護として、入出力の電源側をダイオ
ードで保護する代りに絶縁ゲート・トランジスタでクラ
ンプすれば簡単に解決される。しかし、トライ・ステー
ト出力または入出力共通端子においては、出力がPチャ
ネル型とNチャネル型の絶縁ゲート・トランジスタより
成つているために、SOS(サファイア上に形成した)
型CMOSのようにPチャネル型とNチャネル型の絶縁
ゲート・トランジスタ(以下MOSトランジスタと略記
する)が絶縁物で分離されてはいない半導体基板上に形
成している場合、必然的に電源側も、ダイオードで電源
電圧にクランプされる。本発明は出力端子、特に入出力
端子への電源電圧以上の入力電圧に対して、ラッチアッ
プおよび内部回路の誤動作のない相補型絶縁ゲート半導
体回路を提供することを目的としている。以下図面を用
いて本発明を説明する。In a complementary insulated gate semiconductor circuit (hereinafter abbreviated as a CMOS circuit), input/output terminals are generally used as an input protection circuit, and are clamped from a ground point to within a power supply voltage by a provided diode. If a voltage higher than the power supply voltage is applied to this input/output terminal for this diode (a PN junction diode formed on a semiconductor single crystal substrate and made up of a semiconductor region with the opposite polarity to the substrate), it will operate similar to a thyristor. A so-called latch-up occurs when the power supply current flows abnormally and cannot be recovered unless the power supply voltage is turned off. Generally commercials
As mentioned above, the input and output of the OS are clamped to the power supply voltage by diodes, so if a voltage higher than the power supply voltage is applied to the input/output terminals, a forward current flows, creating a parasitic bipolar transistor and damaging the internal circuit. A malfunction may occur, or a circuit similar to a thyristor may occur, causing excessive power supply current to flow.
Destroy devices and reduce reliability. This can easily be solved by clamping the input and output power supply sides with insulated gate transistors instead of protecting them with diodes. However, in the tri-state output or input/output common terminal, since the output consists of P-channel type and N-channel type insulated gate transistors, SOS (formed on sapphire)
When P-channel type and N-channel type insulated gate transistors (hereinafter abbreviated as MOS transistors) are formed on a semiconductor substrate that is not separated by an insulator, as in the case of type CMOS, the power supply side is also inevitably affected. , clamped to the power supply voltage by a diode. SUMMARY OF THE INVENTION An object of the present invention is to provide a complementary insulated gate semiconductor circuit that is free from latch-up and malfunction of internal circuits when input voltages to output terminals, particularly input/output terminals, are higher than the power supply voltage. The present invention will be explained below using the drawings.
第1図は、本発明の一実施例の回路図で、PチャネルM
OSトランジスタTlのソース(接点0に電源V、を接
続し、ゲート(接点2)に信号11を入力し、ドレイン
(接点3)に、NPNトランジスタT2のベースを接続
し、トランジスタT2のコレクタを電源V、に、エミッ
タ(接点5)を、NチャネルNOSトランジスタT3の
ドレインにそれぞれ接続し、トランジスタT3のソース
を接地(接点6■)しゲートに信号12を入力し、接点
5を出力端子01とする回路である。FIG. 1 is a circuit diagram of an embodiment of the present invention, in which P channel M
Connect the power source V to the source (contact 0) of the OS transistor Tl, input the signal 11 to the gate (contact 2), connect the base of the NPN transistor T2 to the drain (contact 3), and connect the collector of the transistor T2 to the power source. V, the emitter (contact 5) is connected to the drain of the N-channel NOS transistor T3, the source of the transistor T3 is grounded (contact 6), the signal 12 is input to the gate, and the contact 5 is connected to the output terminal 01. This is a circuit that does this.
11、12が同相の入力すなわち11112ともに高レ
ベルのとき出力01は低レベル、逆に工、、12ともに
低レベルのとき出力01は高レベルとなり、11が高レ
ベル、12が低レベルでMOSトランジスタTiおよび
T3は不導通になり、出力高インピーダンス状態になる
。When 11 and 12 are in-phase inputs, that is, when both 11 and 12 are at high level, output 01 is at low level; conversely, when both 12 are at low level, output 01 is at high level, and when 11 is at high level and 12 is at low level, the MOS transistor Ti and T3 become non-conductive, resulting in an output high impedance state.
(このように出力が高レベル、低レベルまたは高インピ
ーダンスとなる場合をトライ・ステート出力という。)
第2図に第1図の回路をN型単結晶基板上に形成したデ
バイスの断面図を示す。(When the output is high level, low level, or high impedance in this way, it is called tri-state output.)
FIG. 2 shows a cross-sectional view of a device in which the circuit of FIG. 1 is formed on an N-type single crystal substrate.
ただし、フイールド絶縁膜は省略した。1〜6の番号は
第1図の接点1〜接点6に対応し、電気的配線を示す。However, the field insulating film was omitted. Numbers 1 to 6 correspond to contacts 1 to 6 in FIG. 1 and indicate electrical wiring.
13はN型半導体単結晶基板、14はNチヤネル領域の
P型拡散領域、15ぱPチヤネルのソースまたはドレイ
ン領域のp+拡散層、16はNチヤネルのソースまたは
ドレイン領域のN+拡散層、17はゲート電極用導電体
(アルミ、多結晶シリコンなど)、18はゲート絶縁膜
(酸化シリコンなど)である。13 is an N-type semiconductor single crystal substrate; 14 is a P-type diffusion region in the N-channel region; 15 is a P+ diffusion layer in the source or drain region of the P-channel; 16 is an N+ diffusion layer in the source or drain region of the N-channel; A gate electrode conductor (aluminum, polycrystalline silicon, etc.), and 18 a gate insulating film (silicon oxide, etc.).
チヤネル●ストツパとして、N型基板上にN+、Pウエ
ル領域にp+を拡散(またはイオン注入)するがここで
の説明には関係ないので略す.この図に示されているよ
うに出力端子はN+拡散層だけに接続されているため、
プラスの電圧に対して、NP接合ダイオードは逆方向電
圧となり、寄生バイボーラ・トランジスタは不導通で、
V1電源電圧以上の適当な電圧を印加しても(T3のM
OSトランジスタ不導通状態に}いて)ラツチアツプや
誤動作を起こさない。第3図は他の実施例を示す回路図
で、第1図の回路に}いて接点3の浮遊容量のためMO
SトランジスタT1が不導通になつて、ここにたまつた
電荷のためMOSトランジスタT2がすぐに不導通にな
らないため接点3と接地点間にNチヤネルMOSトラン
ジスタT5をもうけ、入力信号として11と同相または
同一信号にてすぐに接点3の電荷を放電できるようにし
たものである.第3図にはI,信号を入力した場合の回
路図を示してある。As a channel stopper, N+ is diffused (or ion-implanted) into the N-type substrate and P+ into the P well region, but these are omitted as they are not relevant to this explanation. As shown in this figure, the output terminal is connected only to the N+ diffusion layer, so
For a positive voltage, the NP junction diode has a reverse voltage and the parasitic bibolar transistor is non-conducting.
Even if a suitable voltage higher than the V1 power supply voltage is applied (T3 M
OS transistor is in a non-conducting state) to prevent latch-up or malfunction. FIG. 3 is a circuit diagram showing another embodiment.
Since the S transistor T1 becomes non-conductive and the MOS transistor T2 does not immediately become non-conductive due to the charge accumulated here, an N-channel MOS transistor T5 is provided between the contact point 3 and the ground point, and the input signal is in phase with 11. Alternatively, the charge at contact 3 can be immediately discharged using the same signal. FIG. 3 shows a circuit diagram when the I signal is input.
第3図の回路接続を説明する.PチヤネルMOSトラン
ジスタT4、nチヤネルMOSトランジスタT5訃よび
T,、そうして、NpnトランジスタT6より成り、T
4のソースとT6コレクタ(接点7)を電源2に接続し
、T4とT5のドレインとT6のベースを接続し(接点
9)T4とT5のゲート(接点8ノに入力信号13を入
力し、T6のエミツタT7のドレイン(接点11)を接
続し、この点を出力端子02としT5,T7のソースを
接地(接点12)とする回路である.13と14の入力
信号が同相のとき出力は反転してHまたはLレベルとな
り、13がHレベル(V2電圧レベル)で14がLレベ
ル(接地電位)のとき高インピーダンス状態になる。The circuit connection in Figure 3 will be explained. It consists of a P-channel MOS transistor T4, an N-channel MOS transistor T5, and an Npn transistor T6.
Connect the source of T4 and the collector of T6 (contact 7) to power supply 2, connect the drain of T4 and T5 and the base of T6 (contact 9), input the input signal 13 to the gate of T4 and T5 (contact 8), This circuit connects the drain (contact 11) of emitter T7 of T6, makes this point the output terminal 02, and connects the sources of T5 and T7 to ground (contact 12).When the input signals of 13 and 14 are in phase, the output is It is inverted and becomes H or L level, and becomes a high impedance state when 13 is at H level (V2 voltage level) and 14 is at L level (ground potential).
第4図に入力13,4の信号と、出力02の出力波形を
示す。出力Hレベルは電流電圧からシリコンのPN接合
の場合、約0.6Vほど低い電圧が現われる。以上N型
半導体基板上に形成した相補型MOS回路について説明
したが、P型半導体基板上でも同じであり、ただ電圧の
極性が逆になるだけである。以上詳細に説明したように
、本発明によれば、特に複雑な工程を要することなく、
また動作スピード等の特性上の犠性を払うことなく、寄
生バイポーラ素子によるラツチアツプや誤動作をしない
CMOS回路が実現できるので、CMOS回路の信頼性
の向上に対して著しい効果がある。FIG. 4 shows the signals of inputs 13 and 4 and the output waveform of output 02. In the case of a silicon PN junction, the output H level appears as low as about 0.6V from the current voltage. Although the complementary MOS circuit formed on the N-type semiconductor substrate has been described above, the same applies to the P-type semiconductor substrate, only the polarity of the voltage is reversed. As explained in detail above, according to the present invention, without requiring particularly complicated steps,
Further, since a CMOS circuit that does not cause latch-up or malfunction due to parasitic bipolar elements can be realized without sacrificing characteristics such as operating speed, this has a significant effect on improving the reliability of the CMOS circuit.
第1図は本発明の一実施例の回路図、第2図は第1図の
回路のデバイスの断面図、第3図は、本発明の他の実施
例の回路図、第4図は、第3図の回路の入出力波形図で
ある。
Tl,T4・・・・・・PチャネルMOSトランジスタ
、T2,T6・・・・・・NPnトランジスタ、T,,
T5,T7・・・・・・nチヤネルMOSトランジスタ
、Vl,2・・・・・・電源電圧(又は端子)、11,
12,13,14・・・・・・入力電圧、01,02・
・・・・・出力電圧(又は端子)、1,2・・・・・・
,12・・・・・・接点(又は配線)、13・・・・・
・N型半導体単結晶基板、14・・・・・・P型拡散領
域、15・・・・・・P+拡散層、16・・・・・・N
+拡散7層、17・・・・・・ゲート電極用導電体、1
8・・・・・・ゲート絶縁膜。FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a cross-sectional view of a device in the circuit of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. FIG. 4 is an input/output waveform diagram of the circuit of FIG. 3; Tl, T4...P channel MOS transistor, T2, T6...NPn transistor, T,,
T5, T7... N-channel MOS transistor, Vl, 2... Power supply voltage (or terminal), 11,
12, 13, 14... Input voltage, 01, 02.
...Output voltage (or terminal), 1, 2...
, 12...Contact (or wiring), 13...
・N-type semiconductor single crystal substrate, 14...P-type diffusion region, 15...P+ diffusion layer, 16...N
+7 diffusion layers, 17... conductor for gate electrode, 1
8...Gate insulating film.
Claims (1)
スタに直列に接続されゲートに第1の信号が印加された
第1の電界効果トランジスタと、該バイポーラトランジ
スタのベースにソース又はドレインが接続されゲートに
第2の信号が印加された第2の電界効果トランジスタを
有し、該第1の電界効果トランジスタと該バイポーラト
ランジスタとの中間接続点から出力信号を得る半導体回
路。1 a bipolar transistor, a first field effect transistor connected in series to the bipolar transistor and having a first signal applied to its gate, and a source or drain connected to the base of the bipolar transistor and a second signal applied to the gate; A semiconductor circuit having a second field effect transistor applied thereto and obtaining an output signal from an intermediate junction between the first field effect transistor and the bipolar transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51108071A JPS5931864B2 (en) | 1976-09-09 | 1976-09-09 | Complementary insulated gate semiconductor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51108071A JPS5931864B2 (en) | 1976-09-09 | 1976-09-09 | Complementary insulated gate semiconductor circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60108054A Division JPS61198661A (en) | 1985-05-20 | 1985-05-20 | Complementary insulated gate semiconductor circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5333071A JPS5333071A (en) | 1978-03-28 |
JPS5931864B2 true JPS5931864B2 (en) | 1984-08-04 |
Family
ID=14475134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51108071A Expired JPS5931864B2 (en) | 1976-09-09 | 1976-09-09 | Complementary insulated gate semiconductor circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5931864B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54152852A (en) * | 1978-05-23 | 1979-12-01 | Matsushita Electric Ind Co Ltd | Semiconductor circuit |
JPS5587391A (en) * | 1978-12-22 | 1980-07-02 | Hitachi Ltd | Semiconductor memory circuit device |
JPS5896762A (en) * | 1981-12-03 | 1983-06-08 | Mitsubishi Electric Corp | Semiconductor element |
JPS6062149A (en) * | 1983-09-14 | 1985-04-10 | Nec Kansai Ltd | Semiconductor device |
JPS6062150A (en) * | 1983-09-14 | 1985-04-10 | Nec Kansai Ltd | Semiconductor device |
-
1976
- 1976-09-09 JP JP51108071A patent/JPS5931864B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5333071A (en) | 1978-03-28 |
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