JPS6062149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6062149A JPS6062149A JP17019483A JP17019483A JPS6062149A JP S6062149 A JPS6062149 A JP S6062149A JP 17019483 A JP17019483 A JP 17019483A JP 17019483 A JP17019483 A JP 17019483A JP S6062149 A JPS6062149 A JP S6062149A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- bipolar transistor
- mos
- fet
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002131 composite material Substances 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 101150073536 FET3 gene Proteins 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
この発明は増幅回路などに単体で使用される半導体装置
で、詳しくはバイポーラトランジスタとＭＯＳ −ＰＵ
Ｔ 、抵抗の複合タイプの半導体装置に関する。Detailed Description of the Invention A. Field of Industrial Application This invention relates to a semiconductor device used alone in an amplifier circuit, etc.
T, relates to a resistor composite type semiconductor device.
口、従来技術
各種増幅回路の増幅素子等に単体使用されている半導体
装置にＮＰＮ型又はＰＮＰ型のバイポーラトランジスタ
と、Ｎチャンネル型又はＰチャンネル型のＭＯＳ −Ｆ
ＥＴ （メタルオキサイドシリコン・フィールドエフェ
クトトランジスタ）があり、この両者は特性上、次の相
反する長所、短所を持ち、用途に制限を受けている。2. Prior Art Semiconductor devices used alone as amplifier elements in various amplifier circuits include NPN or PNP bipolar transistors and N-channel or P-channel MOS-F.
There are ETs (metal oxide silicon field effect transistors), and both have the following contradictory advantages and disadvantages in their characteristics, and their applications are limited.
即ち、バイポーラトランジスタは導通時のいわゆるオン
抵抗が小さい長所を持つ反面、入力抵抗が小さい短所を
持つ。長所のオン抵抗は０．２〜０．３Ω以下にするこ
とが可能である。また短所である入力抵抗は大部分がベ
ースとエミッタ間の抵抗で決まり、大きくしてもＩＫΩ
程度まででそれ以上にすることが難しく、そのため例え
ばこのバイポーラトランジスタを増幅素子として使用し
た場合は実質的負荷抵抗がバイポーラトランジスタの入
力抵抗でほぼ決まって大きくとれず、増幅度が小さく制
限される。That is, while bipolar transistors have the advantage of having a small so-called on-resistance when conducting, they have the disadvantage of having a small input resistance. The advantage is that the on-resistance can be reduced to 0.2-0.3Ω or less. In addition, the input resistance, which is a disadvantage, is mostly determined by the resistance between the base and emitter, and even if it is large, it is IKΩ.
Therefore, when this bipolar transistor is used as an amplification element, for example, the actual load resistance is almost always determined by the input resistance of the bipolar transistor, and it is difficult to increase it further, and the amplification degree is limited to a small value.
一方ＭＯ３−ＰＥＴはバイポーラトランジスタと逆で入
力抵抗が大きい長所と、オン抵抗が大きい短所を持つ。On the other hand, MO3-PET is the opposite of a bipolar transistor, having the advantage of high input resistance and the disadvantage of high on-resistance.
このＭＯＳ −ＦＥＴの入力抵抗はゲートとワニス間の
抵抗でゲートとソース間にはＳｔ ０２等の絶縁膜があ
って入力抵抗はほぼ無限大と大きく、従ってＭＯＳ −
ＦＥＴは真空管と同じように増幅度が大きな範囲で設定
され得る。The input resistance of this MOS-FET is the resistance between the gate and the varnish, and there is an insulating film such as St02 between the gate and the source, and the input resistance is large and almost infinite.
Like vacuum tubes, FETs can have amplification levels set over a wide range.
またＭＯＳ −ＦＥＴのオン抵抗はバイポーラトランジ
スタに比べ大きくて０．２Ω〜数Ωである。Furthermore, the on-resistance of a MOS-FET is larger than that of a bipolar transistor, ranging from 0.2 Ω to several Ω.
ハ１発明の目的
本発明は上記バイポーラトランジスタとＭＯＳ・ＦＥＴ
の特性上の問題点に鑑みてなされたもので、バイポーラ
トランジスタとＭＯＳ ・ＮＥＴの各長所が活かされ、
短所が除去された特性を持つ単体の複合型半導体装置を
提供することを目的とする。C1 Purpose of the Invention The present invention relates to the above-mentioned bipolar transistor and MOS/FET.
It was created in view of the problems with the characteristics of
It is an object of the present invention to provide a single composite semiconductor device having characteristics in which disadvantages have been eliminated.
二１発明の構成
本発明は１つの半導体基板内にバイポーラトランジスタ
素子と、間５−ＦＥＴ素子及び抵抗素子を前記バイポー
ラトランジスタ素子のコレクタとＭＯＳ −ＦＥＴ素子
のドレインを共通にして一括形成すると共に、前記バイ
ポーラトランジスタ素子のベースとＭＯＳ −ＦＥＴ素
子のソースを直接に、バイポーラトランジスタ素子のエ
ミッタとＭＯＳ −ＦＥＴ素子のソースを抵抗素子を介
して電気的接続して１個の３端子トランジスタ構造とし
たことを特徴とする。このような構造によるとオン抵抗
はバイポーラトランジスタ素子のオン抵抗で決定され、
逆に入力抵抗はＭＯＳ −ＦＥＴ素子の入力抵抗だけで
決定され、従って従来のバイポーラトランジスタとＭＯ
Ｓ −ＦＥＴの各長所が活かされ、各短所が相殺された
動作をする１個のトランジスタとしての半導体装置が実
現される。21 Structure of the Invention The present invention forms a bipolar transistor element, an inter-FET element, and a resistor element in one semiconductor substrate at once, with the collector of the bipolar transistor element and the drain of the MOS-FET element being common, and The base of the bipolar transistor element and the source of the MOS-FET element are electrically connected directly, and the emitter of the bipolar transistor element and the source of the MOS-FET element are electrically connected via a resistance element to form one three-terminal transistor structure. It is characterized by According to this structure, the on-resistance is determined by the on-resistance of the bipolar transistor element,
Conversely, the input resistance is determined only by the input resistance of the MOS-FET element, so conventional bipolar transistors and MO
A semiconductor device as a single transistor is realized in which the advantages of the S-FET are utilized and the disadvantages are canceled out.
ホ、実施例
本発明”の一実施例を図面から説明する。第１図及び第
２図において、（１）は１つの半導体基板、（２）（３
）（４）は半導体基板（１）に不純物選択拡散で形成さ
れたバイポーラトランジスタ素子、ＭＯＳ −Ｆｌ！Ｔ
素子、抵抗素子である。図面ではＮ型の半導体基板（１
）にＮＰＮ型バイポーラトランジスタ素子（２） 、Ｎ
チャンネル型ＭＯＳ −ＦＥＴ （３） 、 Ｐ型半導
体抵抗素子（４）を形成した例を示す。（５，）は半導
体基板（１）の裏面に形成された裏面電極でバイポーラ
トランジスタ素子（２）のコレクタＣとＭＯＳ −ＦＥ
Ｔ （３）のドレインＤの共通電極である。（６）及び
（７）はバイポーラトランジスタ素子（２）のベースＢ
及びエミッタＥの各電極、（８）及び（，９）はＭＯＳ
−ＦＥＴ素子（３）のゲートＧ及びソースＳの各電極
、（１０〉及び（１１）は抵抗素子（４）の両端の各電
極で、これら各々の電極（６）〜（１１）は半導体基板
（１）の表面に形成した絶縁膜（１２）を選択除去して
Ａβ蒸着等の手段で次の配線パターンでもつて被着形成
される。Embodiment One embodiment of the present invention will be explained with reference to the drawings. In FIGS. 1 and 2, (1) is one semiconductor substrate, (2) (3
)(4) is a bipolar transistor element formed in the semiconductor substrate (1) by selective diffusion of impurities, MOS-Fl! T
element, resistance element. In the drawing, an N-type semiconductor substrate (1
) is an NPN bipolar transistor element (2), N
An example in which a channel type MOS-FET (3) and a P-type semiconductor resistance element (4) are formed is shown. (5,) is the back electrode formed on the back surface of the semiconductor substrate (1), and the collector C of the bipolar transistor element (2) and the MOS-FE
This is the common electrode of the drain D of T (3). (6) and (7) are the base B of the bipolar transistor element (2)
and each electrode of emitter E, (8) and (,9) are MOS
- Each electrode of the gate G and source S of the FET element (3), (10> and (11) are each electrode at both ends of the resistance element (4), and each of these electrodes (6) to (11) is the semiconductor substrate The insulating film (12) formed on the surface of (1) is selectively removed and the next wiring pattern is deposited by Aβ vapor deposition or the like.
バイポーラトランジスタ素子（２）のベース電極（６）
とＭＯＳ −ＦＥＴ素子（４）のソース電極（９）と抵
抗素子（４）の−電極（１１）は電気的に結線され、抵
抗素子（４）の他の一電極（１０）はバイポーラトラン
ジスタ素子（２）のエミッタ電極（７）に電気的結線さ
れる。そしてＭＯＳ−ＦＥＴ素子（３）のゲート電極（
８）と裏面電極（５）及びバイポーラトランジスタ素子
（２）のエミッタ電極（７）が夫々に外部の入出力端子
（１３） （１４） （１５）に電気的接続されて、１
個の３端子トランジスタが得られる。Base electrode (6) of bipolar transistor element (2)
The source electrode (9) of the MOS-FET element (4) and the - electrode (11) of the resistive element (4) are electrically connected, and the other electrode (10) of the resistive element (4) is a bipolar transistor element. (2) is electrically connected to the emitter electrode (7). And the gate electrode of the MOS-FET element (3) (
8), the back electrode (5), and the emitter electrode (7) of the bipolar transistor element (2) are electrically connected to external input/output terminals (13), (14), and (15), respectively.
3-terminal transistors are obtained.
次に上記半導体装置の動作特性を第３図から説明する。Next, the operating characteristics of the above semiconductor device will be explained with reference to FIG.
第３図に示す如（バイポーラトランジスタ素子（２）の
コレクタＣとエミッタ８間にバイアス電圧ｖＯを付与し
、ＭＯＳ −ＦＥＴ素子（３）のゲートＧに所望の入力
電圧ｖ１を印加してＭＯＳ −ＦＥＴ素子（３）を導通
させて抵抗素子（４）に電流１１を流す。入力電圧ｖ１
．を大きくして抵抗素子（４）での電圧ドロップを大き
（し、バイポーラトランジスタ素子（２）のベースＢに
動作電圧（約０．６Ｖ）が加わるとバイポーラトランジ
スタ素子（２）が導通してコレクタＣ−エミッタ８間に
電流Ｉ？がメイン電流として流れ、この時の装置全体の
オン抵抗はバイポーラトランジスタ素子（２）のオン抵
抗ではほぼ決定され、小さなオン抵抗特性を持つことが
分る。As shown in FIG. 3, a bias voltage vO is applied between the collector C and emitter 8 of the bipolar transistor element (2), and a desired input voltage v1 is applied to the gate G of the MOS-FET element (3). The FET element (3) is made conductive and current 11 flows through the resistance element (4).Input voltage v1
．． is increased to increase the voltage drop across the resistor element (4), and when an operating voltage (approximately 0.6 V) is applied to the base B of the bipolar transistor element (2), the bipolar transistor element (2) becomes conductive and the collector A current I? flows as a main current between C and emitter 8, and the on-resistance of the entire device at this time is almost determined by the on-resistance of the bipolar transistor element (2), and it can be seen that the device has small on-resistance characteristics.
また上記半導体装置の入力抵抗はＭＯＳ −ＦＥＴ素子
（３）の入力抵抗そのものでほぼ無限大のものが得られ
る。Further, the input resistance of the semiconductor device is almost infinite due to the input resistance of the MOS-FET element (3) itself.
尚、本発明は上記実施例に限らず、１つの半導体基板に
ＰＮＰ型バイポーラトランジスタ素子、Ｐチャンネル型
Ｍｔ）Ｓ −ＦＥＴ素子、Ｎ型半導体抵抗素子を形成し
て上述要領で配線したも゛のであってもよい。It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also include a PNP bipolar transistor element, a P-channel type Mt)S-FET element, and an N-type semiconductor resistance element formed on one semiconductor substrate and wired in the manner described above. There may be.
へ１発明の効果
以上の如く、本発明によればバイポーラトランジスタと
ＭＯＳ −ＦＥＴの短所が消え両者長所のみがそのまま
発揮されるオン抵抗小、入力抵抗大な、る１個のトラン
ジスタとしての使用が可能であり、増幅回路等での実用
効果は極めて大である。また１つの半導体基板にバイポ
ーラトランジスタ、ＭＯＳ −ＦＢＴ 、抵抗の各素子
を形成して配線したので量産性に優れ、複合型半導体装
置として安価なものが提供できる。1. Effects of the Invention As described above, according to the present invention, the disadvantages of bipolar transistors and MOS-FETs are eliminated, and only the advantages of both can be utilized as they are.On-resistance is low, input resistance is high, and the transistor can be used as a single transistor. It is possible, and the practical effect in amplifier circuits etc. is extremely large. Furthermore, since the bipolar transistor, MOS-FBT, and resistor elements are formed and wired on one semiconductor substrate, mass productivity is excellent, and a composite semiconductor device can be provided at low cost.
第１図及び第２図は本発明の一実施例を示す等価回路図
及び模式断面図、第３図は第１図回路における動作原理
を説明する等価回路図である。
（１）・・半導体基板、（２）・・バイポーラトランジ
スタ素子、（３）・・ＭＯＳ −ＦＥＴ素子、（４）
・・抵抗素子。1 and 2 are an equivalent circuit diagram and a schematic sectional view showing one embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram illustrating the operating principle of the circuit shown in FIG. 1. (1) Semiconductor substrate, (2) Bipolar transistor element, (3) MOS-FET element, (4)
...Resistance element.
Claims (1)
子、ＭＯＳ −ＦＥＴ素子及び抵抗素子を前記バイポー
ラトランジスタ素子のコレクタとＭＯＳ −ＰＲ，Ｔ素
子のドレインを共通にして形成すると共に、バイポーラ
トランジスタ素子のベースとＭＯＳ −ＦＥＴ素子のソ
ースを直接に、バイポーラトランジスタ素子のエミッタ
とＭＯＳ −ＦＥＴ素子のソースを前記抵抗素子を介し
て電気的配・ 線して１個のトランジスタとして動作さ
せることを特徴とする半導体装置。(1) A bipolar transistor element, a MOS-FET element, and a resistance element are formed in one semiconductor substrate so that the collector of the bipolar transistor element and the drain of the MOS-PR, T element are common, and the base of the bipolar transistor element and the drain of the MOS-PR, T element are formed in common. A semiconductor device characterized in that the source of a MOS-FET element is electrically wired directly and the emitter of a bipolar transistor element and the source of a MOS-FET element are electrically wired via the resistance element to operate as one transistor. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17019483A JPS6062149A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17019483A JPS6062149A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6062149A true JPS6062149A (en) | 1985-04-10 |
Family
ID=15900413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17019483A Pending JPS6062149A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062149A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000200791A (en) * | 1999-01-05 | 2000-07-18 | Kansai Electric Power Co Inc:The | Voltage driven bipolar semiconductor device |
| US8324691B2 (en) | 2007-06-12 | 2012-12-04 | Toyota Jidosha Kabushiki Kaisha | Power semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333071A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Complementary type insulated gate semiconductor circuit |
| JPS57186833A (en) * | 1981-05-13 | 1982-11-17 | Hitachi Ltd | Switching element |
-
1983
- 1983-09-14 JP JP17019483A patent/JPS6062149A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333071A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Complementary type insulated gate semiconductor circuit |
| JPS57186833A (en) * | 1981-05-13 | 1982-11-17 | Hitachi Ltd | Switching element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000200791A (en) * | 1999-01-05 | 2000-07-18 | Kansai Electric Power Co Inc:The | Voltage driven bipolar semiconductor device |
| US8324691B2 (en) | 2007-06-12 | 2012-12-04 | Toyota Jidosha Kabushiki Kaisha | Power semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SU528894A3 (en) | Current amplifier | |
| JP3319406B2 (en) | Comparison amplification detection circuit | |
| JP3325396B2 (en) | Semiconductor integrated circuit | |
| JP2001168651A (en) | Semiconductor device | |
| JP3043250B2 (en) | Analog output drive circuit for gate array | |
| JPS6062149A (en) | Semiconductor device | |
| US4994694A (en) | Complementary composite PNP transistor | |
| JPH0865074A (en) | Current to voltage conversion circuit, current compression and expansion circuit, automatic exposure control system and automatic exposure control system with built-in sensor | |
| JPH0321927B2 (en) | ||
| US6768139B2 (en) | Transistor configuration for a bandgap circuit | |
| JPH01162005A (en) | Amplifying circuit | |
| JPS58207672A (en) | Semiconductor device | |
| JPH053424A (en) | Minute voltage detection circuit and current limit circuit using the same | |
| US4859966A (en) | Current amplifier circuit and a current amplifying type differential current converter circuit | |
| KR820001797B1 (en) | Differential anplitier | |
| JPH0526769Y2 (en) | ||
| JP2571102Y2 (en) | Semiconductor integrated circuit | |
| JP3086687B2 (en) | Differential amplifier | |
| JP2596151B2 (en) | Voltage comparator | |
| JPH0327606A (en) | Field effect transistor amplifying circuit | |
| JP2674274B2 (en) | Reference voltage circuit | |
| JPS6221310A (en) | Current constant multiple circuit | |
| JP3094564B2 (en) | Semiconductor device | |
| JP2001127167A (en) | Semiconductor device | |
| JP2671304B2 (en) | Logic circuit |