JPH04280513A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce the number of fanouts viewed from a pre-stage and to improve the load drive capability. CONSTITUTION:The output signal of a dual-input NOR circuit composed of enhancement FETs 11, 12 and a depletion type FET 21 is fed to the FET 13 of a buffer section. Sources of the FETs 11, 12 in the dual-input NOR are connected to a power supply via a resistor and a signal at a connecting point between the source and the resistor is fed to the FET 14 of the buffer section. Since the two signals take opposite logic state to each other, the FETs 13, 14 of the buffer section turn on/off alternately. Thus, one input signal is connected to only a single FET, then the fanouts are not increased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic circuits, and more particularly to logic circuits used in compound semiconductor integrated circuits.

0002

[Prior Art] Compound semiconductors such as GaAs have higher mobility than silicon, which is currently most used, and high-resistance substrates can be obtained relatively easily. It has been expected to be used as a material for integrated circuits. Particularly from the viewpoint of low power consumption, DCFL (Direct-coupled FE) as shown in Fig.
It is promising to use logic circuits. FIG. 5 shows a circuit diagram of a two-input NOR circuit as an example of a DCFL logic circuit. This circuit consists of two enhancement type FETs (hereinafter referred to as E-FETs) 11 and 12.
and depression type FET (hereinafter referred to as D-FET) 2
Consists of 1. In the figure, 3 and 4 indicate inputs, 5 and 8 indicate outputs, and 6 indicates a power supply (VDD).

This circuit has the characteristics of a simple configuration, a small number of elements, low power consumption, and high speed when the load is small. However, since the DCFL logic circuit has a small load driving capability, it has the disadvantage that the delay time increases as the load increases. Therefore, when it is necessary to drive a large load such as long wiring or large fan-out in an integrated circuit configured with DCFL logic circuits, a logic circuit equipped with a push-pull type buffer as shown in the circuit diagram in Figure 6 is required. A circuit is used. This circuit is SBFL
(Super-buffered FET log
ic) Also called a circuit.

The operation of the SBFL circuit will be explained below with reference to FIG. FIG. 6 shows a two-input NOR as an example of a logic circuit equipped with a push-pull buffer. This circuit is a circuit in which a push-pull buffer 2 made up of three E-FETs 13, 14, and 15 is added to the 2-input NOR 1 shown in FIG. In this circuit, if at least one of inputs 3 and 4 is "H", DCFL-
Since the output of the 2-input NOR1 is "L", the FET 15 whose gate is connected to this output is "off", and the gates of the FETs 13 and 14 connected in parallel are connected to the input terminals, so at least one of them is One is “on”
Therefore, "L" is output to the output terminal. Conversely, input 3,
4 are both "L", the output of DCFL-2 input NOR1 is "H", so FET15 is "on", FET
13 and 14 are turned "off" and output "L". In this circuit, when FET15 is “on”, FET1
3 and 14 are "off", and when at least one of FETs 13 and 14 is "on", FET 15 operates to be "off", so no through current flows through the buffer section.
Load driving ability can be improved without increasing power consumption.

[0005]

However, the logic circuit equipped with the push-pull buffer described above has the following problems. This problem will be explained with reference to FIG. Looking at this logic circuit from input 3, the gates of two FETs 11 and 14 are connected. This means that the fan-out of the load appears to increase from the logic circuit connected upstream of the logic circuit. Usually from the perspective of increasing load driving capacity,
Since the gate width of FETs 13 and 14 is set to be the same as or larger than that of FETs 11 and 12, the fanout seen from the previous stage is 2 when using a DCFL circuit.
It will more than double. This increase in fan-out results in an increase in the delay time of the preceding logic circuit.

An object of the present invention is to provide a logic circuit that can maintain a high load driving capability and suppress the increase in fan-out seen from the preceding stage.

[0007]

[Means for Solving the Problems] The logic circuit of the first invention connects the source of a first FET of enhancement type and the drain of a second FET of enhancement type to form an output terminal, and an output buffer section in which the drain of the FET is connected to a first power supply and the source of the second FET is connected to a second power supply having a voltage lower than that of the first power supply; a logic section configured with a DCFL circuit; and a resistor. The high voltage side power supply terminal of the logic section is connected to a third power supply, the low voltage side power supply terminal of the logic section is connected to a fourth power supply having a lower voltage than the third power supply via a resistor, The first F of the output buffer section
The gate of the ET is connected to the output terminal of the logic section, and the gate of the second FET of the output buffer section is connected to the connection point between the low voltage side power supply terminal of the logic section and the resistor.

In the logic circuit of the second invention, the source of the first enhancement type FET and the drain of the second enhancement type FET are connected as an output terminal, and the first
The drain of the FET is connected to the first power supply, and the drain of the second FET is connected to the first power supply.
It consists of an output buffer section in which the source of T is connected to a second power supply whose voltage is lower than that of the first power supply, a logic section made up of a DCFL circuit, and a third depression type FET. The voltage side power supply terminal is connected to the third power supply, the low voltage side power supply terminal of the logic section is connected to the drain of the third FET, and the gate and source of the third FET are connected to the fourth power supply whose voltage is lower than that of the third power supply. The gate of the first FET of the output buffer section is connected to the power supply, and the gate of the second FET of the output buffer section is connected to the connection point of the low voltage side power supply terminal of the logic section and the third FET. It is characterized by being connected.

In the logic circuit of the third invention, the source of the first enhancement type FET and the drain of the second enhancement type FET are connected as an output terminal, and the first
The drain of the FET is connected to the first power supply, and the drain of the second FET is connected to the first power supply.
It consists of an output buffer section in which the source of T is connected to a second power supply whose voltage is lower than that of the first power supply, a logic section made up of a DCFL circuit, and a third enhancement type FET. The voltage side power supply terminal is connected to the third power supply, the low voltage side power supply terminal of the logic section is connected to the gate and drain of the third FET, and the source of the third FET is connected to the fourth power supply whose voltage is lower than that of the third power supply. Connected to the power supply, the gate of the first FET of the output buffer section is connected to the output terminal of the logic section, and the gate of the second FET of the output buffer section is connected to the connection point of the low voltage side power supply terminal of the logic section and the third FET. It is characterized by being connected to.

In the logic circuit of the fourth invention, the source of the first enhancement type FET and the drain of the second enhancement type FET are connected as an output terminal, and the first
The drain of the FET is connected to the first power supply, and the drain of the second FET is connected to the first power supply.
It consists of an output buffer section in which the source of T is connected to a second power supply whose voltage is lower than that of the first power supply, a logic section made up of a DCFL circuit, and a third enhancement type FET. The voltage side power supply terminal is connected to the third power supply, the low voltage side power supply terminal of the logic section is connected to the drain of the third FET, the gate of the third FET is connected to the output terminal of the logic section, and the source is connected to the third FET. The gate of the first FET of the output buffer section is connected to the output terminal of the logic section, and the gate of the second FET of the output buffer section is connected to a fourth power supply whose voltage is lower than the power supply of the logic section. It is characterized in that it is connected to the connection point between the terminal and the third FET.

[0011]

Embodiments (First Embodiment) An embodiment and its operation will be explained regarding the logic circuit of the first invention. FIG. 1 is a diagram showing a two-input NOR as an embodiment of the logic circuit of the first invention. In this embodiment, the DCFL-2 input NO.
R1 E-FET11, 12 source and power supply (VSS)
Connect a resistor 31 between DCFL-2 input NOR
Connect the gate of E-FET13 to the output of DCFL-1, and connect the source of E-FET11 and 12 in DCFL-2 input NOR1 to the resistor 3.
Connect the gate of E-FET14 to the connection point of D-F
Connect the power supply (VDD) 6 to the drain of ET21, and connect it to the E-FET.
Connect the power supply (VDD2) 7 to the drain of E-FET1
Connect the power supply (VSS2) 9 to the source of E-FET
This circuit extracts an output signal from the connection point between the source of E-FET 13 and the drain of E-FET 14. In addition, VSS<VDD
, VSS2<VDD2.

Next, the operation of this circuit will be explained. DCF
L-2 input NOR1 performs normal operation, outputting "H" only when inputs 3 and 4 are both "L", and outputs "L" in other cases.
” is output. First, DCFL-2 input NOR is “H”
We will explain the case of outputting . In this case, input 3,
Both E-FETs 11 and 12 in the DCFL-2 input NOR1 are "off", and no current flows through the resistor 31. Therefore, the gate-source voltage of E-FET14 is VSS-VSS2, and if this value is smaller than the threshold voltage of E-FET14, E-FET
ET14 is "off". On the other hand, "H" voltage VDD is applied to the gate of E-FET13, and the E-FET
13 becomes “on” and output 5 receives E-F from VDD2.
A voltage lower by the threshold voltage of ET13 is output.

Next, when the DCFL-2 input NOR outputs "L", the E-F in the DCFL-2 input NOR
Since at least one of the ETs 11 and 12 is "on", a current equal to the saturation current of the D-FET 21 flows through the resistor 31. This current generates a voltage Vr across the resistor 31, and the gate-source voltage of the E-FET 14 becomes VSS-VSS2+Vr. This is E-FET14
If the threshold voltage of
”. Also, the output voltage of DCFL-2 input NOR is
It becomes VL+Vr, which is higher than the "L" output voltage VL of a normal DCFL by Vr. If the difference between this value and the output voltage Vo of the buffer section is smaller than the threshold voltage of the E-FET 13, the E-FET 13 is turned "off" and "L" is output to the output 5, and the output voltage Vo at this time is VSS2
becomes. Note that E-FETs 13 and 14 are alternately "on",
In order to “off” and push-pull operation, E-F
The threshold voltage of ET13 and 14 is Vt(13), respectively.
, Vt(14), VL+Vr+VSS2<Vt(13)
(1)
VSS-VSS2<Vt(14)<VSS-VSS
It is necessary to satisfy 2+Vr (2). Note that the resistance value of the resistor 31 is R, the D-FET21
When the saturation current of is Idss, Vr=R・Idss

(3).

In this embodiment, the FET connected to the front stage of the circuit is E-FET11 or E-FET12.
It is the same as a general DCFL circuit,
There is no increase in fan-out numbers. Further, since the load is driven by a buffer circuit with excellent driving ability, the circuit of the present invention has high load driving ability.

Note that even if the threshold voltages of the E-FETs 13 and 14 do not satisfy equations (1) and (2), operation as a logic circuit is possible, and the fan-out obtained by the present invention The feature that the number is equal to that of a normal DCFL circuit is preserved.

[0016] Also, when VSS2 and VSS are equal, V
Even when DD2 and VDD are equal, the essential features of the present invention do not change.

(Second Embodiment) An embodiment and its operation will be explained regarding the logic circuit of the second invention. FIG. 2 is a diagram showing a two-input NOR as an embodiment of the logic circuit of the second invention. In this embodiment, two E-FETs 11 and 12 are used.
DCFL-2 input NOR1 composed of and D-FET21
Connect the drain of D-FET 22 to the sources of E-FETs 11 and 12, the gate and source of D-FET 22 to the power supply (VSS) 8, connect the gate of E-FET 13 to the output of DEFL-2 input NOR1, and 2 input NOR1
Connect the gate of E-FET 14 to the connection point between the sources of E-FETs 11 and 12 inside and D-FET 22, and
Power supply (VDD) 6 to the drain of 21, E-FET13
Connect the power supply (VDD2) 7 to the drain of E-FET14, and the power supply (VSS2) 9 to the source of E-FET14.
This circuit takes out an output signal from the connection point between the source of the E-FET 14 and the drain of the E-FET 14. Note that VSS<VDD, V
A power supply voltage is applied so that SS2<VDD2.

Next, the operation of this circuit will be explained. DCF
L-2 input NOR1 performs normal operation, outputting "H" only when inputs 3 and 4 are both "L", and outputs "L" in other cases.
” is output. First, DCFL-2 input NOR is “H”
We will explain the case of outputting . In this case, input 3,
4 are both "L", and E-FETs 11 and 12 in DCFL-2 input NOR1 are both "off", and D-
No current flows between the drain and source of FET22. Therefore, the gate-source voltage of E-FET14 is VS
S-VSS2, and if this value is smaller than the threshold voltage of the E-FET 14, the E-FET 14 is "off". On the other hand, the “H” voltage V is applied to the gate of E-FET13.
When DD is applied, the E-FET 13 is turned on, and a voltage lower than VDD2 by the threshold voltage of the E-FET 13 is outputted to the output 5.

Next, when the DCFL-2 input NOR outputs "L", the E-F in the DCFL-2 input NOR
At least one of ET11 and ET12 is turned on, and voltage Vr is generated between the drain and source of D-FET22, and the voltage between the gate and source of E-FET14 is VSS.
-VSS2+Vr. If this is greater than the threshold voltage of the E-FET 14, the E-FET 14 is turned "on". Further, the output voltage of the DCFL-2 input NOR becomes VL+Vr, which is higher than the "L" output voltage VL of the normal DCFL by Vr. This value and the output voltage V of the buffer section
If the difference in o is smaller than the threshold voltage of E-FET 13, E-FET 13 becomes "off" and output 5 is set to "L".
is output, and the output voltage Vo at this time becomes VSS2. Note that E-FETs 13 and 14 are alternately "on" and "off".
f” for push-pull operation, E-FET1
The threshold voltages of 3 and 14 are Vt(13) and Vt, respectively.
(14), VL+Vr+VSS2<Vt(13)
(4)
VSS-VSS2<Vt(14)<VSS-VSS
It is necessary to satisfy 2+Vr (5).

In this embodiment, the FET connected to the front stage of the circuit is E-FET11 or E-FET12.
It is the same as a general DCFL circuit,
There is no increase in fan-out numbers. Further, since the load is driven by a buffer circuit with excellent driving ability, the circuit of the present invention has high load driving ability.

Note that even if the threshold voltages of the E-FETs 13 and 14 do not satisfy equations (4) and (5), operation as a logic circuit is possible, and the fan-out obtained by the present invention The feature that the number is equal to that of a normal DCFL circuit is preserved.

[0022] Also, when VSS2 and VSS are equal, V
Even when DD2 and VDD are equal, the essential features of the present invention do not change.

Furthermore, unlike the first embodiment, it is not necessary to create a new resistor in this embodiment, so that it is possible to use the conventional integrated circuit manufacturing process using a DCFL circuit as is.

(Third Embodiment) An embodiment and its operation will be explained regarding the logic circuit of the third invention. FIG. 3 is a diagram showing a two-input NOR as an embodiment of the logic circuit of the third invention. In this embodiment, two E-FETs 11 and 12 are used.
DCFL-2 input NOR1 composed of and D-FET21
Connect the drain and gate of E-FET 15 to the sources of E-FET 11 and 12, and connect E-FET 15 to the power supply (VSS) 8.
Connect the source of E-FET13 to the output of DCFL-2 input NOR1, and connect the gate of E-FET13 to the output of DCFL-2 input NOR1.
Connect the gate of E-FET 14 to the connection point between the sources of E-FETs 11 and 12 inside and D-FET 22, and
Power supply (VDD) 6 to the drain of 21, E-FET13
Connect the power supply (VDD2) 7 to the drain of E-FET14 and the power supply (VSS2) 9 to the source of E-FET13.
This circuit takes out an output signal from the connection point between the source of the E-FET 14 and the drain of the E-FET 14. Note that VSS<VDD, V
A power supply voltage is applied so that SS2<VDD2.

Next, the operation of this circuit will be explained. DCF
L-2 input NOR1 performs normal operation, outputting "H" only when inputs 3 and 4 are both "L", and outputs "L" in other cases.
” is output. First, DCFL-2 input NOR is “H”
We will explain the case of outputting . In this case, input 3,
4 are both "L", and E-FETs 11 and 12 in DCFL-2 input NOR1 are both "off", and E-FETs 11 and 12 in DCFL-2 input NOR1 are both "off".
No current flows between the drain and source of FET15. Therefore, the gate-source voltage of E-FET14 is VS
S-VSS2, and if this value is smaller than the threshold voltage of the E-FET 14, the E-FET 14 is "off". On the other hand, the “H” voltage V is applied to the gate of E-FET13.
When DD is applied, the E-FET 13 is turned on, and a voltage lower than VDD2 by the threshold voltage of the E-FET 13 is outputted to the output 5.

Next, when the DCFL-2 input NOR outputs "L", the E-F in the DCFL-2 input NOR
At least one of ET11 and ET12 is turned on, and voltage Vr is generated between the drain and source of E-FET15, and the voltage between the gate and source of E-FET14 is VSS.
-VSS2+Vr. If this is greater than the threshold voltage of the E-FET 14, the E-FET 14 is turned "on". Further, the output voltage of the DCFL-2 input NOR becomes VL+Vr, which is higher than the "L" output voltage VL of the normal DCFL by Vr. This value and the output voltage V of the buffer section
If the difference in o is smaller than the threshold voltage of E-FET 13, E-FET 13 becomes "off" and output 5 is set to "L".
is output, and the output voltage Vo at this time becomes VSS2. Note that E-FETs 13 and 14 are alternately "on" and "off".
f” for push-pull operation, E-FET1
The threshold voltages of 3 and 14 are Vt(13) and Vt, respectively.
(14), VL+Vr+VSS2<Vt(13)
(6)
VSS-VSS2<Vt(14)<VSS-VSS
It is necessary to satisfy 2+Vr (7).

In this embodiment, the FET connected to the front stage of the circuit is E-FET11 or E-FET12.
It is the same as a general DCFL circuit,
There is no increase in fan-out numbers. Further, since the load is driven by a buffer circuit with excellent driving ability, the circuit of the present invention has high load driving ability.

Note that even if the threshold voltages of the E-FETs 13 and 14 do not satisfy equations (6) and (7), operation as a logic circuit is possible, and the fan-out obtained by the present invention The feature that the number is equal to that of a normal DCFL circuit is preserved.

[0029] Furthermore, when VSS2 and VSS are equal, V
Even when DD2 and VDD are equal, the essential features of the present invention do not change.

Furthermore, unlike the first embodiment, it is not necessary to newly create a resistor in this embodiment, so that it is possible to use the conventional integrated circuit manufacturing process using a DCFL circuit as is.

(Fourth Embodiment) An embodiment and its operation will be explained regarding the logic circuit of the fourth invention. FIG. 4 is a diagram showing a two-input NOR as an embodiment of the logic circuit of the fourth invention. In this embodiment, two E-FETs 11 and 12 are used.
DCFL-2 input NOR1 composed of and D-FET21
Connect the drain of E-FET15 to the sources of E-FET11 and 12, connect the source of E-FET15 to the power supply (VSS) 8, and connect the E-FET15 to the output of DCFL-2 input NOR1.
Connect the gates of T13 and E-FET15 to the sources of E-FETs 11 and 12 in DCFL-2 input NOR1 and E-FET15.
Connect the gate of E-FET14 to the connection point of ET15,
Power supply (VDD) 6 is connected to the drain of D-FET21, and E-
Power supply (VDD2) 7 is connected to the drain of FET13, E-F
Connect the power supply (VSS2) 9 to the source of ET14, and
This circuit takes out an output signal from the connection point between the source of FET 13 and the drain of E-FET 14. In addition, VSS<
A power supply voltage is applied so that VDD, VSS2<VDD2.

Next, the operation of this circuit will be explained. DCF
L-2 input NOR1 performs normal operation, outputting "H" only when inputs 3 and 4 are both "L", and outputs "L" in other cases.
” is output. First, DCFL-2 input NOR is “H”
We will explain the case of outputting . In this case, input 3,
4 are both "L", and E-FETs 11 and 12 in DCFL-2 input NOR1 are both "off", and E-FETs 11 and 12 in DCFL-2 input NOR1 are both "off".
No current flows between the drain and source of FET15. Therefore, the gate-source voltage of E-FET14 is VS
S-VSS2, and if this value is smaller than the threshold voltage of the E-FET 14, the E-FET 14 is "off". On the other hand, the “H” voltage V is applied to the gate of E-FET13.
When DD is applied, the E-FET 13 is turned on, and a voltage lower than VDD2 by the threshold voltage of the E-FET 13 is outputted to the output 5.

Next, when the DCFL-2 input NOR outputs “L”, the E-F in the DCFL-2 input NOR
At least one of ET11 and ET12 is turned on, and voltage Vr is generated between the drain and source of E-FET15, and the voltage between the gate and source of E-FET14 is VSS.
-VSS2+Vr. If this is greater than the threshold voltage of the E-FET 14, the E-FET 14 is turned "on". Further, the output voltage of the DCFL-2 input NOR becomes VL+Vr, which is higher than the "L" output voltage VL of the normal DCFL by Vr. This value and the output voltage V of the buffer section
If the difference in o is smaller than the threshold voltage of E-FET 13, E-FET 13 becomes "off" and output 5 is set to "L".
is output, and the output voltage Vo at this time becomes VSS2. Note that E-FETs 13 and 14 are alternately "on" and "off".
f” for push-pull operation, E-FET1
The threshold voltages of 3 and 14 are Vt(13) and Vt, respectively.
(14), VL+Vr+VSS2<Vt(13)
(8)
VSS-VSS2<Vt(14)<VSS-VSS
2+Vr (9).

In this embodiment, the FET connected to the front stage of the circuit is E-FET11 or E-FET12.
It is the same as a general DCFL circuit,
There is no increase in fan-out numbers. Further, since the load is driven by a buffer circuit with excellent driving ability, the circuit of the present invention has high load driving ability.

Note that even if the threshold voltages of the E-FETs 13 and 14 do not satisfy equations (8) and (9), operation as a logic circuit is possible, and the fan-out obtained by the present invention The feature that the number is equal to that of a normal DCFL circuit is preserved.

[0036] Also, when VSS2 and VSS are equal, V
Even when DD2 and VDD are equal, the essential features of the present invention do not change.

Furthermore, unlike the first embodiment, it is not necessary to newly create a resistor in this embodiment, so that the present embodiment has the feature that the conventional integrated circuit manufacturing process using a DCFL circuit can be used as is.

[0038]

[Effects of the Invention] According to the present invention, it is possible to enhance the load driving capability without increasing the number of fan-outs seen from the front stage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a two-input NOR according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a two-input NOR according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a two-input NOR according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a two-input NOR according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a DCFL configuration 2-input NOR.

[Figure 6] 2-input N with conventional push-pull buffer
FIG. 3 is a circuit diagram showing an OR.

[Explanation of symbols]

1 DCFL configuration 2-input NOR 2 Push-pull buffer 3, 4 Input 5 Output 6 Power supply (VDD) 7 Power supply (VDD2) 8 Power supply (VSS) 9 Power supply (VSS2) 11, 12, 13, 14, 15 Enhancement type FET (E -FET) 21, 22, 23 Depression type FET (D-F
ET) 31 Resistance

Claims (4)

[Claims] Claims: 1. The source of a first enhancement-type FET and the drain of a second enhancement-type FET are connected to form an output terminal, and the drain of the first FET is connected to the drain of a second enhancement-type FET.
an output buffer section connected to a power supply of the second FET and having a source of the second FET connected to a second power supply having a lower voltage than the first power supply;
Consisting of a logic section configured with a DCFL circuit and a resistor, the high voltage side power supply terminal of the logic section is connected to a third power supply, and the low voltage side power supply terminal of the logic section is connected to the third power supply via the resistor. It is connected to a fourth power supply with a lower voltage, the gate of the first FET of the output buffer section is connected to the output terminal of the logic section, and the gate of the second FET of the output buffer section is connected to the low voltage side power supply terminal of the logic section. A logic circuit characterized in that it is connected to a connection point of a resistor. 2. The source of the first enhancement type FET and the drain of the second enhancement type FET are connected to form an output terminal, and the drain of the first FET is connected to the drain of the first enhancement type FET.
an output buffer section connected to a power supply of the second FET and having a source of the second FET connected to a second power supply having a lower voltage than the first power supply;
It consists of a logic section configured with a DCFL circuit and a third depletion type FET, the high voltage side power supply terminal of the logic section is connected to the third power supply, and the low voltage side power supply terminal of the logic section is connected to the third power supply terminal. The gate and source of the third FET are connected to the drain of the first FET, and the gate and source of the third FET are connected to a fourth power source having a lower voltage than the third power source. A logic circuit characterized in that a gate of a second FET of the logic section is connected to a connection point between a low voltage side power supply terminal of the logic section and a third FET. 3. The source of the first enhancement type FET and the drain of the second enhancement type FET are connected to form an output terminal, and the drain of the first FET is connected to the first FET.
an output buffer section connected to a power supply of the second FET and having a source of the second FET connected to a second power supply having a lower voltage than the first power supply;
It consists of a logic section configured with a DCFL circuit and a third enhancement type FET, the high voltage side power supply terminal of the logic section is connected to the third power supply, and the low voltage side power supply terminal of the logic section is connected to the third power supply terminal. A third FET is connected to the gate and drain of the FET.
The source of the ET is connected to a fourth power supply having a lower voltage than the third power supply, the gate of the first FET of the output buffer section is connected to the output terminal of the logic section, and the gate of the second FET of the output buffer section is connected to the logic section. A logic circuit characterized in that the logic circuit is connected to a connection point between a low voltage side power supply terminal of the section and a third FET. 4. The source of the first enhancement type FET and the drain of the second enhancement type FET are connected to form an output terminal, and the drain of the first FET is connected to the drain of the first enhancement type FET.
an output buffer section connected to a power supply of the second FET and having a source of the second FET connected to a second power supply having a lower voltage than the first power supply;
It consists of a logic section configured with a DCFL circuit and a third enhancement type FET, the high voltage side power supply terminal of the logic section is connected to the third power supply, and the low voltage side power supply terminal of the logic section is connected to the third power supply terminal. is connected to the drain of the third FET.
The gate of the first FET of the output buffer section is connected to the output terminal of the logic section, the source is connected to the fourth power supply whose voltage is lower than the third power supply, and the gate of the first FET of the output buffer section is connected to the output terminal of the logic section. A logic circuit characterized in that a gate of the second FET is connected to a connection point between a low voltage side power supply terminal of the logic section and the third FET.