JPH0823029A - Semiconductor integrated circuit and designing thereof - Google Patents

Abstract

PURPOSE:To improve electromigration resistance by normally operating a semiconductor integrated circuit device so as to route signal wiring with good efficiency. CONSTITUTION:This is a semiconductor integrated circuit device whereas semiconductor element is provided on the main surface, and on the upper layer thereof, wiring layers of lamination structure where wirings such as branch power supply wirings 5, trunk power supply wirings 6 and signal wirings are provided so as to constitute a base circuit cell group having a prescribed function where the semiconductor elements are connected by wiring, and the base circuit cell group is divided into a plurality of feed areas, every feed area 4 is connected to the branch power supply wires 5 and the branch power supply wirings 5 are connected to an external power supply through the branch power supply wirings 6. Wirings width of the branch power supply wirings 5 is different according to the kind and the number of base circuit cells arranged in each feed area 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to an ASIC (Aplication Replication Integer).
ated Circuit or Application Replication Standard
Product: A technology effective when applied to a special purpose IC).

[0002]

2. Description of the Related Art An ASIC is a design method of a semiconductor integrated circuit device for a specific application such as a gate array method, a standard cell method, a custom method, etc., and the concept of ASIC is one of these methods. All of the semiconductor integrated circuit devices adopted are included.

A semiconductor integrated circuit device adopting an ASIC is basically based on the support of an automatic wiring arrangement system (DA: Design Automation) using a computer.
Design development is performed. For example, in a semiconductor integrated circuit device adopting the standard cell method, generally, a basic circuit cell (macro cell) having a plurality of types of functions, which has been optimally designed in advance, is registered in an automatic placement and routing system, and if necessary, This is a method of arranging basic circuit cells and connecting each of the basic circuit cells.

The semiconductor integrated circuit device adopting the standard cell system is mainly composed of a semiconductor substrate having a rectangular planar shape. A plurality of power supply areas are arranged in a matrix in the X and Y directions on the main surface of the substrate. In the power supply area, basic circuit cells such as logic circuit cells, input / output circuit cells and diagnostic circuit cells are arranged, and power supply circuit cells for supplying power to these basic circuit cells are arranged.

The logic circuit cells in the power supply area are connected to other logic circuit cells to form an internal logic circuit. The input / output circuit in the power supply area is connected to the logic circuit cell to input / output signals to / from the outside.

The wiring within the power feeding area and between the power feeding areas is performed by wiring formed in a wiring layer of a multilayer wiring structure. For example, in the case of a 6-layer wiring structure, a sixth wiring layer, that is, a so-called uppermost wiring layer is used as a wiring layer of a main power supply wiring extending in the Y direction, and a low-voltage main power supply wiring,
The terminal trunk power wiring and the ground trunk power wiring are alternately arranged.

The wiring layer of the fifth layer is used as a wiring layer of the branch power wiring used as the branch of the main power wiring. The branch power supply wiring is arranged in the upper part of each of the power supply block rows aligned in the X direction with the low-voltage branch power supply wiring, the terminal branch power supply wiring, and the ground branch power supply wiring extending in the column direction. The logic circuit cell, the input / output circuit cell, the diagnostic circuit cell, and the power supply circuit cell that are arranged are respectively connected.

In addition, the branch power supply wiring has electron migration and potential drop in the branch power supply wiring,
The wiring width is set according to the power supply area where the amount of flowing current is the largest.

[0009]

However, as a result of examining the above-mentioned prior art, the present inventor found the following problems.

According to the above-mentioned semiconductor integrated circuit device, since the wiring width of the main power supply wiring is set according to the power feeding area where the amount of current flowing is the largest, the branches connected to the respective power feeding areas are set. Although the power supply wiring has the same wiring width, the amount of current flowing in the power supply area varies depending on the type and number of basic circuit cells arranged. For this reason, there is a problem that the semiconductor integrated circuit device malfunctions due to a difference in potential drop in the branch power supply wiring and a different potential applied to each power supply area.

Further, conventionally, the branch power supply wiring determines the wiring width according to the amount of current in the power supply area where the maximum current flows, so that the branch power supply wiring for supplying power to the power supply area where the maximum current flows is: Although it satisfies the line width at which electron migration does not occur, the line width is not as wide as that of other branch power supply lines. Therefore, there is a possibility that disconnection may occur due to the electron migration phenomenon.

Further, since the wiring width of the branch power wiring is set in accordance with the power feeding area where the amount of current flowing is the largest,
In the power supply area where the amount of flowing current is small, the trunk power supply wiring with a wiring width wider than necessary is arranged, and the wiring channel area is unnecessarily occupied, and the signal wiring cannot be routed efficiently. .

An object of the present invention is to provide a technique capable of preventing a voltage drop due to resistance of a power supply voltage in a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving the electromigration resistance of the power supply wiring of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of efficiently arranging signal wirings in designing a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A semiconductor element is provided on the main surface of a semiconductor substrate, and a wiring layer having a laminated structure for arranging wiring such as branch power wiring, trunk power wiring and signal wiring is provided on the semiconductor element.
The semiconductor element is connected by the wiring to form a basic circuit cell group having a predetermined function, the basic circuit cell group is divided into a plurality of power feeding areas, the branch power supply wiring is connected to each power feeding area, In the semiconductor integrated circuit device in which the branch power supply wiring is connected to an external power supply through the trunk power supply wiring, the wiring width of the branch power supply wiring varies depending on the type and number of basic circuit cells arranged in each power supply area.

(2) A method of designing a semiconductor integrated circuit device, wherein predetermined basic circuit cells are arranged in a plurality of power supply areas arranged in a matrix, and branch power supply lines for supplying a current to the power supply areas are arranged. Calculating the amount of current flowing in each power feeding area and the potential drop in each power feeding area based on the type and number of the basic circuit cells arranged in each power feeding area, and based on the calculation result, the branch power wiring Set the wiring width of.

[0020]

According to the above-mentioned means (1), in the semiconductor integrated circuit device of the present invention, the wiring width of the branch power wiring differs depending on the type and number of basic circuit cells arranged in each power feeding area. That is, since the wiring width is set so that the potential drop is the same in each power supply area, a predetermined potential can be supplied to each circuit cell, and each basic circuit cell can be stably operated.

Further, since the wiring width of the power supply area having a small amount of current is narrowed, it is possible to allow a margin for the wiring width of the branch power supply wiring connected to the power supply area where the maximum amount of current flows. It is possible to improve the electron migration resistance even in a power supply area where there is no margin in width and the amount of current is large.

According to the above-mentioned means (2), the method for designing a semiconductor integrated circuit device of the present invention is such that the power supply area is selected based on the type and number of the circuit cells arranged in each power supply area. The amount of flowing current and the potential drop in each power supply area are calculated, and the wiring width of the branch power supply wiring is set based on the calculation result. In other words, since the branch power supply wiring having the wiring width satisfying the electron migration regulation is connected to each power supply area, the branch power supply wiring connected to the power supply area where the amount of current flowing is smaller has a smaller wiring width than the conventional one, and the wiring channel There is a margin to arrange the signal wiring in the area. As a result, it is possible to efficiently route the signal wiring.

The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device adopting the standard cell system.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0025]

This embodiment is an embodiment in which the present invention is applied to a semiconductor integrated circuit device designed by the standard cell system.

FIG. 1 is a chip layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the structure of the power supply area of the semiconductor integrated circuit device.

FIG. 3 is a layout diagram of the branch power supply wiring arranged in the fifth wiring layer of the semiconductor integrated circuit device.

FIG. 4 is a layout diagram of the trunk power supply wiring arranged in the sixth wiring layer of the semiconductor integrated circuit device.

FIG. 5 is a layout diagram of essential parts showing the structure of the branch power supply wiring.

As shown in FIG. 1, a semiconductor integrated circuit device adopting the standard cell system is mainly composed of a substrate 1 made of single crystal silicon having a rectangular planar shape. An internal logic circuit 2a, an input / output circuit 2b, a diagnostic circuit 2c, etc. are arranged in the central region of the main surface of the substrate 1.

As shown in FIG. 2, the basic circuit cell group arranged on the main surface of the substrate 1 is divided into a plurality of power feeding areas 4. The power supply area 4 includes a logic circuit cell 3a,
It is composed of an input / output circuit cell 3b, a diagnostic circuit cell 3c and a power supply circuit cell 3d which are arranged adjacent to the logic circuit cell 3a. On the main surface of the substrate 1, the power feeding areas 4 are aligned in the X and Y directions.

The internal logic circuit 2a is arranged in the X direction in FIG.
It is composed of a plurality of logic circuit cells 3a which are regularly arranged in any of the Y directions. The logic circuit cell 3a is provided with a macro cell (functional circuit block) having a predetermined logic function (or storage function) or a repeating basic circuit forming a part of this macro cell. A logic circuit (a macro cell or a part of a macro cell) such as a flip-flop circuit, a NAND gate, a NOR gate, an OR gate, and a NOT gate circuit is arranged in the logic circuit cell 3a.

The logic circuit cell 3a is mainly composed of a bipolar transistor. The bipolar transistor is, for example, a vertical structure npn excellent in high-speed circuit operation performance.
Composed of molds. In the logic circuit cell 3a, a plurality of resistance elements and the like are arranged in addition to the bipolar transistor.

The internal logic circuit 2a is divided into a plurality of parts in the Y direction in FIG. An input / output circuit 2b and a diagnostic circuit 2c are arranged between each of the plurality of divided internal logic circuits 2a.

The input / output circuit 2b is arranged in the X direction in FIG.
It is composed of a plurality of input / output circuit cells 3b arranged regularly in any of the Y directions. The input / output circuit 2b is used as an interface circuit between an external device and the logic circuit cell 3a arranged in the internal logic circuit 2a, and mainly performs level conversion of an input signal and an output signal.

The input / output circuit cell 3b is composed mainly of a bipolar transistor and a MISFET, and a basic circuit such as a NOT gate circuit and an AND gate circuit is arranged.

Further, the internal logic circuit 2a has the same structure as in FIG.
It is divided into a plurality of pieces in the X direction and arranged. A power supply circuit 2d is provided between each of the plurality of divided internal logic circuits 2a.
Is arranged. The power supply circuit 2d is divided into a plurality of parts, and a reference voltage generating circuit is arranged.

The power supply circuit 2d is divided into a plurality of parts in the X and Y directions, like the internal logic circuit 2a and the input / output circuit 2b. The power supply circuit 2d includes the logic circuit cell 3
a, a reference voltage used in each of the input / output circuit cell 3b and the like is generated.

The logic circuit cell 3a is mainly connected to the logic circuit cells 3a arranged in the same power supply area 4 to form a part of the internal logic circuit 2a. The internal logic circuit 2a is mainly the same. The input / output circuit cell 3b arranged in the power supply area 4 is connected. Further, the reference voltage is supplied to the basic circuit cells arranged in the power supply area 4 by the power supply circuit cells 3d arranged in the same power supply area 4.

The semiconductor integrated circuit device is mainly composed of the substrate 1 made of single crystal silicon as described above.
On one main surface of the substrate 1, the aforementioned bipolar transistor or M
A semiconductor element such as an ISFET is provided, and a wiring layer having a multi-layered structure is stacked on the substrate 1, which is an upper layer of the semiconductor element.

For example, in the case of a semiconductor integrated circuit device employing a so-called 6-layer wiring structure having 6 wiring layers, the first wiring layer is laminated on the semiconductor element with an interlayer insulating film interposed. Then, the first layer wiring is arranged. The first layer wiring is electrically connected to each electrode of the semiconductor element through a connection hole (contact hole) formed in the interlayer insulating film, and is mainly used as a connection between semiconductor elements, a so-called intra-cell connection. .

The second-layer wiring layer is laminated on the first-layer wiring layer with an interlayer insulating film interposed, and the second-layer wiring extending in the Y direction is arranged. The second-layer wiring has a first hole through a connection hole (through hole) formed in the interlayer insulating film.
It is electrically connected to the layer wiring and is mainly used as an in-cell connection.

The third wiring layer and the fourth wiring layer are
Mainly used as an inter-cell wiring layer (signal wiring layer) that connects basic circuit cells.

The third-layer wiring layer is laminated on the second-layer wiring layer with an interlayer insulating film interposed, and the third-layer wiring extending in the X direction is arranged. The third-layer wiring passes through the connection hole (through hole) formed in the interlayer insulating film to the second-layer wiring.
Electrically connect to the layer wiring.

The fourth wiring layer is laminated on the third wiring layer with an interlayer insulating film interposed, and the fourth wiring layer extending in the Y direction is arranged. The fourth-layer wiring is connected to the third-layer wiring through the connection hole (through hole) formed in the interlayer insulating film.
Electrically connect to the layer wiring.

The fifth wiring layer and the sixth wiring layer are mainly used as power supply wiring layers.

As shown in FIG. 3, the fifth wiring layer is
It is laminated on the fourth wiring layer with an interlayer insulating film interposed. In the fifth wiring layer, the branch power supply wiring 5 is arranged so as to extend in the X direction.

The branch power supply wiring 5 includes a terminal branch power supply wiring 5t,
There are three types of low-voltage branch power supply wiring 5e and ground branch power supply wiring 5c, and the terminal branch power supply wiring 5 is arranged in the Y direction in the fifth wiring layer.
t, the low-voltage branch power supply wiring 5e, and the ground branch power supply wiring 5c are repeatedly arranged in this order. The branch power supply wirings 5 are arranged one by one above each of the power supply area rows aligned in the X direction.

Each of the branch power supply lines 5 is connected to a logic circuit cell 3a in each power supply area 4 through a power supply line arranged in a lower wiring layer through a connection hole formed in an interlayer insulating film.
It is connected to the input / output circuit cell 3b, the diagnostic circuit cell 3c, and the power supply circuit cell 3d.

As shown in FIG. 4, the sixth wiring layer is
It is laminated on the fifth wiring layer with an interlayer insulating film interposed. In the sixth wiring layer, the trunk power supply wiring 6 is arranged so as to extend in the Y direction. The trunk power supply wiring 6 includes a grounded trunk power supply wiring 6c, a terminal trunk power supply wiring 6e, and a low-voltage trunk power supply wiring 6t.
c, the terminal trunk power supply wiring 6t, and the low-voltage trunk power supply wiring 6e are repeatedly arranged in this order in the Y direction.

Each of the trunk power supply wirings 6 is connected to the branch power supply wiring 5 through the connection hole (through hole) formed in the interlayer insulating film (the low-voltage trunk power supply wiring 6e is connected to the low-voltage branch power supply wiring 5e, and the terminal trunk power supply wiring is connected). 6t is connected to the terminal branch power supply wiring 5t, and the ground trunk power supply wiring 6c is connected to the ground branch power supply wiring 5c).

As shown in FIG. 5, the trunk power supply wiring 6 is connected to the branch power supply wiring through the connection hole 7a.
Supplies terminal voltage, low voltage, and ground voltage to the power supply area 4 through the connection hole 7b. The branch power supply wiring 5 has an arrow P
, The wiring width is different depending on the amount of current flowing in each power feeding area 4. The branch power supply wiring 5 having a wide wiring width is connected to the power supply area 4 having a large amount of flowing current, and the branch power supply wiring 5 having a small wiring width is connected to the power supply area 4 having a small amount of flowing current. The potential drop in the power supply wiring 5 can be made constant, and the electron migration resistance can be improved.

A final protective film is laminated on the sixth wiring layer. The sixth wiring layer is provided with external terminals electrically connected to the signal wiring and the main power supply wiring 6, and is drawn out onto the surface of the final protective film through the holes formed in the final protective film.

The semiconductor integrated circuit device is mounted on a mounting substrate such as a mother board, a baby board, and a printed wiring board (PCB) by the face down bonding method (CCB method).

Next, a method of designing a semiconductor integrated circuit device in which the present invention is applied to the standard cell system will be described.

FIG. 6 is a flow chart for explaining a method for designing a semiconductor integrated circuit device in which the present invention is applied to the standard cell system.

The semiconductor integrated circuit device adopting the standard cell system is almost entirely automatically designed by an automatic wiring arrangement system (DA: Design Automation) based on computer support.

As shown in FIG. 6, the order of designing the semiconductor integrated circuit device by the automatic wiring arrangement system is to first virtualize a two-dimensional plane corresponding to the main surface of the substrate 1 and the wiring layer on the memory of the computer. Then, the basic circuit cells are arranged on the two-dimensional plane corresponding to the main surface of the substrate (step 6).
1). This basic circuit cell is designed in advance and registered in the computer.

Next, the arranged basic circuit cell is divided into a plurality of power supply areas 4 (step 62). The power supply area 4
Is composed of a logic circuit cell 3a and an input / output circuit cell 3b, a diagnostic circuit cell 3c and a power supply circuit cell 3d which are arranged adjacent to the logic circuit cell 3a.

Next, in-cell wiring, inter-cell wiring (signal wiring), power supply wiring, etc. are arranged on a two-dimensional plane corresponding to the wiring layer (step 63). For example, when designing a semiconductor integrated circuit device including a wiring layer having a 6-layer wiring structure, the intra-cell wiring is mainly arranged in the first wiring layer and the second wiring layer, and the third wiring layer is arranged. Inter-cell wiring is mainly arranged in the wiring layer and the fourth wiring layer. Branch power supply wirings 5 are mainly arranged in the fifth wiring layer, and trunk power supply wirings 6 are arranged in the sixth wiring layer.

The branch power supply wiring 5 is connected to each of the power feeding areas 4
The wiring width is for supplying electric power to the device, and is arranged with a wiring width in consideration of electron migration and potential drop in accordance with the power supply area 4 where the mounting rate of the basic circuit cells is standard.

The inter-cell wiring (signal wiring) is mainly the third wiring.
It is arranged in the wiring layer of the fourth layer, the wiring layer of the fourth layer, but for efficient connection, part of the inter-cell wiring is arranged in the wiring layer of the fifth layer and the wiring layer of the sixth layer. To do.

Next, based on the type and number of arranged basic circuit cells, the amount of current required in each power feeding area 4 and the potential drop in each power feeding area 4 are calculated (step 64).

Next, the wiring width of the branch power supply wiring 5 is set for each power feeding area 4 based on the calculation result of (step 64) (step 65). That is, the wiring width of the branch power supply wiring 5 connected to the power feeding area 4 in which a large amount of current flows is increased,
The electromigration resistance is improved and the potential drop amount in all the power supply areas 4 is made constant.

Next, the branch power supply wiring 5 set in (step 65) is rearranged on the two-dimensional plane (step 6).
6). In this way, a semiconductor integrated circuit device that performs a predetermined operation is designed.

As described above, in the semiconductor integrated circuit device of the present invention, the wiring width of the branch power supply wiring 5 differs depending on the type and number of basic circuit cells arranged in each power feeding area 4. That is, since the wiring width is set so that the potential drop is the same in each power supply area 4, a predetermined potential can be supplied to each basic circuit cell, and each basic circuit cell can be operated stably. You can

The wiring width of the branch power supply wiring 5 differs depending on the type and number of basic circuit cells arranged in each power feeding area 4. That is, since the wiring width of the power feeding area 4 having a small current amount is narrowed, the wiring width of the branch power wiring connected to the power feeding area 4 in which the maximum current amount flows can be thickened to allow a margin. Even in the power supply area 4 where the wiring width is conventionally narrow, the electron migration resistance can be improved.

Further, the semiconductor integrated circuit device of the present invention calculates the amount of current flowing in each power feeding area 4 based on the type and number of the basic circuit cells arranged in each power feeding area 4,
The wiring width of the branch power supply wiring 5 is determined based on the current amount. That is, since the branch power supply wiring 5 having a wiring width satisfying the electron migration regulation is connected to each power supply area 4, the branch power supply wiring 5 connected to the power supply area 4 in which a small amount of current flows has a narrower wiring width than the conventional one. Since there is a free area in the wiring channel area, the signal wiring can be arranged there. As a result, it is possible to efficiently route the signal wiring.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device adopting any of the gate array system, standard cell system, custom system, semi-custom system, and master slice system.

[0072]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

1. The semiconductor integrated circuit device can be operated normally.

2. The electromigration resistance of the power supply wiring of the semiconductor integrated circuit device can be improved.

3. In designing semiconductor integrated circuit devices,
The signal wiring can be efficiently routed.

[Brief description of drawings]

FIG. 1 is a chip layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention,

FIG. 2 is a schematic diagram showing a configuration of a power supply area of the semiconductor integrated circuit device,

FIG. 3 is a layout diagram of branch power supply wirings arranged in a fifth wiring layer of the semiconductor integrated circuit device;

FIG. 4 is a layout diagram of a main power supply wiring arranged in a sixth wiring layer of the semiconductor integrated circuit device;

FIG. 5 is a layout diagram of a main part showing a configuration of power supply wiring of the semiconductor integrated circuit device;

FIG. 6 is a flowchart illustrating a method for designing a semiconductor integrated circuit device to which the present invention is applied in a standard cell system.

[Explanation of symbols]

1 ... Board, 2a ... Internal logic circuit, 2b ... Input / output circuit, 2
c ... Diagnostic circuit, 2d ... Power supply circuit, 3a ... Logic circuit cell,
3b ... I / O circuit cell, 3c ... Diagnostic circuit cell, 3d ... Power supply circuit cell, 4 ... Power supply area, 5e ... Low voltage branch power supply wiring, 5t ... Termination branch power supply wiring, 5c ... Ground branch power supply wiring, 6
e ... Low-voltage branch power supply wiring, 6t ... Termination branch power supply wiring, 6c ...
Ground branch power wiring, 7 ... Connection hole.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Miyamoto 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (2)

[Claims] 1. A semiconductor element is provided on a main surface of a semiconductor substrate, and a wiring layer having a laminated structure for arranging wiring such as branch power supply wiring, trunk power supply wiring and signal wiring is provided on the semiconductor element, and the semiconductor element is provided. The basic circuit cell group having a predetermined function is connected by the wiring, the basic circuit cell group is divided into a plurality of power supply areas, and the branch power supply wiring is connected to each of the power supply areas. Is a semiconductor integrated circuit device connected to an external power supply through the trunk power supply wiring, wherein the wiring width of the branch power supply wiring varies depending on the type and number of basic circuit cells arranged in each power feeding area. Semiconductor integrated circuit device. 2. A method for designing a semiconductor integrated circuit device, comprising: arranging predetermined basic circuit cells in a plurality of power supply areas arranged in a matrix, and arranging branch power supply wires for supplying a current to the power supply areas, The amount of current flowing in each power feeding area and the potential drop in each power feeding area are calculated based on the type and number of the basic circuit cells arranged in each power feeding area, and the branch power supply wiring is calculated based on the calculation result. A method of designing a semiconductor integrated circuit device, comprising setting a wiring width.