JPH05166932A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the reliability upon circuit actuation while accelerating the circuit actuation rate within the semiconductor integrated circuit device adopting the master slice system. CONSTITUTION:Within the semiconductor integrated circuit device adopting the master slice system, the power supply main lines 5 extending over an interface circuit 3 are physically and electrically separated in the boundary region between an input part 31 and an output part 32 so that these separated power supply main lines 5 may be respectively fed with power supply independently by outer terminals 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device adopting a master slice method.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device adopting a master slice method is characterized in that it is suitable for small-quantity production in a wide variety of products and can be developed in a short period of time.

A semiconductor integrated circuit device adopting the master slice method is basically composed of a semiconductor substrate (semiconductor pellet or semiconductor chip) having a rectangular planar shape. A logic circuit is arranged in a central region of the main surface of the semiconductor substrate, and an interface circuit is arranged in a region along each side of the main surface of the semiconductor substrate around the logic circuit.
Further, external terminals are arranged on the outer periphery of the interface circuit.

In a semiconductor integrated circuit device adopting a general master slice method, in the logic circuit, basic cells (basic cells) which are basic units of a repeating pattern having a basic design are regularly arranged in a matrix. To be done. In the logic circuit, a plurality of layers of wiring are connected within the regularly arranged basic cells and between the basic cells. A semiconductor integrated circuit device employing this type of master slice system can form various logic circuits simply by changing the wiring pattern.

Further, the interface circuit is usually provided with an input circuit cell and an output circuit cell having a basic design. The interface circuit is configured as an input unit, an output unit, or an input / output unit by connecting wires to either the input circuit cell or the output circuit cell or to the opposite side.

[0006] In the semiconductor integrated circuit device employing the master slice system, a logic circuit, connected to be applied to each of the interface circuits computer - automatic placement and routing system using the data: almost automatically formed by (DA D esign A utomation) To be done.

A power supply trunk line is arranged on the interface circuit. A plurality of interface circuits are arranged along one side of the main surface of the semiconductor substrate, and the plurality of arranged interface circuits are arranged on each side of the square. It is composed of a ring shape. The power supply main line is intended to supply power to each of the plurality of arranged interface circuits and also to supply power to the logic circuit. The power supply trunk line uses some of the external terminals arranged around the interface circuit as external terminals for power supply,
It is connected to this external terminal for power supply, and power is supplied from an external device. The power supply trunk line is generally a power supply voltage trunk line, for example, 5
[V] and the ground voltage main line, for example, 0 [V] are configured as one set.

A semiconductor integrated circuit device adopting a general master slice method is described in, for example, Nikkei Electronics, August 12, 1985, page 187 and subsequent pages.

[0009]

However, the present inventors have found the following problems in the semiconductor integrated circuit device adopting the above-mentioned master slice method.

(1) The semiconductor integrated circuit device adopting the master slice method is used as the output unit because the driving capability of the interface circuit (output circuit cell) used as the output unit is larger than that of the input unit. Due to the circuit operation of the interface circuit, a large power swing (noise) occurs in the power trunk line. This noise is connected to the power supply trunk line arranged on the interface circuit used as the output section and the power supply trunk line arranged on the interface circuit used as the input section. A malfunction occurs in the circuit operation of the circuit. Further, since the power of the logic circuit is supplied from the power supply main line arranged on the interface circuit, the noise also causes a malfunction in the circuit operation of the logic circuit.

The malfunction of the circuit operation of each of the interface circuit and the logic circuit used as the input section not only lowers the reliability of the circuit operation of the semiconductor integrated circuit device employing the master slice method, but also attenuates noise. If time is incorporated in the operating time, the circuit operating speed of the semiconductor integrated circuit device adopting the master slice method will be reduced.

(2) In order to solve the problem (1),
It is effective to apply the technique of arranging two different types of power supply trunk lines on a plurality of interface circuits to a semiconductor integrated circuit device adopting the master slice method. The two types of different power supply trunk lines are composed of a power supply trunk line that supplies power to the interface circuit used as an input unit and a power supply trunk line that supplies power to the interface circuit used as an output unit. Each of the two types of power supply trunk lines is opposed to each other and extends substantially in parallel on the interface circuit in the arrangement direction.

However, when noise is generated in the power supply main line that supplies power to the interface circuit used as the output unit, the two kinds of different power supply main lines are arranged substantially parallel to each other, so that the noise is generated. It is transmitted by crosstalk (coupling) to a power supply main line that supplies power to an interface circuit used as an input unit. Therefore, similar to the problem (1), in the semiconductor integrated circuit device adopting the master slice method,
The reliability of the circuit operation is reduced, and the circuit operation speed is reduced.

An object of the present invention is to provide a technique capable of improving reliability in circuit operation in a semiconductor integrated circuit device adopting a master slice system in which a power supply main line extends on an interface circuit. is there.

Another object of the present invention is to provide a technique capable of increasing the circuit operation speed in a semiconductor integrated circuit device adopting a master slice system in which a power supply trunk line extends on an interface circuit. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of interface circuits are regularly arranged in one direction on the main surface of the semiconductor substrate, and external terminals corresponding to the individual interface circuits are arranged along the arrangement of the plurality of interface circuits. In a semiconductor integrated circuit device employing a master slice method, in which a plurality of power supply main lines extending in the array direction of the interface circuits are arranged on the plurality of interface circuits. Among them, between the interface circuit used as the input unit and the interface circuit used as the output unit, the first power supply trunk line extending on the interface circuit used as the input unit is used as the output unit. Divide each of the second power supply trunk lines that extend above the interface circuit into First power supply mains, thereby connecting each of the second power supply mains to each of the mutually different independent external terminals for power supply are arranged in the first power supply trunk, areas that have been divided to each of the second power supply mains.

(2) Among the interface circuits used as the output section of the means (1), a plurality of interface circuits connected in parallel are connected to some of the corresponding external terminals. A second connected circuit that extends on the interface circuit used as the output unit on a plurality of interface circuits connected in parallel;
A third power supply trunk line separated from the power supply trunk line is arranged, and the third power supply trunk line is connected with another external terminal corresponding to a plurality of interface circuits connected in parallel as a power supply external terminal.

[0020]

According to the above-mentioned means (1), the following operational effects can be obtained in the semiconductor integrated circuit device adopting the master slice method.

(A) Even if noise is generated in the second power supply trunk line by the circuit operation of the interface circuit used as the output section, the noise is generated in the second power supply trunk line arranged on the interface circuit used as the output section. On the other hand, since the first power supply trunk line arranged on the interface circuit used as the input unit is physically and electrically separated, noise generated in the second power supply trunk line is transmitted to the first power supply trunk line. Therefore, it is possible to prevent malfunction of the interface circuit used as the input section due to noise (or malfunction of the internal circuit).

(B) As in the case of the above-mentioned effect (A), the second
Even if noise is generated in the power supply trunk line, since the second power supply trunk line and the first power supply trunk line do not extend in parallel with each other, the noise generated in the second power supply trunk line is transmitted to the first power supply trunk line. It is possible to prevent the crosstalk due to noise, and to prevent the malfunction of the interface circuit used as the input section due to the noise.

(C) Based on the above-mentioned effects (A) and (B), the reliability of the circuit operation of the semiconductor integrated circuit device adopting the master slice method can be improved (noise margin can be improved). Further, the circuit operating speed of the semiconductor integrated circuit device adopting the master slice method can be increased.

According to the above-mentioned means (2), in the semiconductor integrated circuit device adopting the master slice method,
The following effects can be obtained.

(A) Among the interface circuits used as the output section, the interface circuits connected in parallel (double buffer output circuit) have a high probability of generating noise in the circuit operation, and the interface circuit used as the output section. Since the third power supply main line arranged on the interface circuit connected in parallel is physically and electrically separated from the second power supply main line arranged on the circuit,
The noise generated in the third power supply trunk line is not transmitted to the second power supply trunk line and prevents malfunction of the interface circuit used as the output unit (or malfunction of the interface circuit used as the input unit). it can.

(B) As in the case of the above effect (A), the third
Even if noise is generated in the power supply trunk line, since the third power supply trunk line and the second power supply trunk line do not extend parallel to each other, the noise generated in the third power supply trunk line is transmitted to the second power supply trunk line. It is possible to prevent crosstalk due to noise, and prevent malfunction of the interface circuit used as the output section due to noise.

(C) Based on the above-mentioned effects (A) and (B), it is possible to improve the reliability of the circuit operation of the semiconductor integrated circuit device adopting the master slice method (improve the noise margin).

(D) The interface circuits connected in parallel can output an output signal from some of the corresponding external terminals, and the other external terminals of the plurality are vacant terminals. Other external terminals can be effectively used as external terminals for power supply.

The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device adopting a master slice method.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and their repeated description will be omitted.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (layout diagram) shows the structure of a semiconductor integrated circuit device adopting a master slice method according to an embodiment of the present invention.

As shown in FIG. 1, a semiconductor integrated circuit device 1 adopting the master slice method is mainly composed of a semiconductor pellet having a rectangular plane (for example, a single crystal silicon substrate). In the semiconductor integrated circuit device 1 adopting the master slice method, a plurality of interface circuits (buffer circuits) 3 and a plurality of external terminals (bonding pads) 2 are arranged in a region along one side of a rectangular shape. The plurality of interface circuits 3 and the plurality of external terminals 2 are arranged on each side of the rectangular shape. That is, in the semiconductor integrated circuit device 1 adopting the master slice method, the interface circuit 3 and the external terminal 2 are arranged along almost all sides of the rectangular shape.

In the present embodiment, although not limited to this number of wiring layers, the semiconductor integrated circuit device 1 adopting the master slice method has a two-layer wiring structure. Usually, the external terminals 2 are formed in the uppermost wiring layer (second wiring layer). The wiring arranged in each wiring layer is composed of a single layer of an aluminum film or an aluminum alloy film or a laminated layer mainly including the aluminum film or aluminum alloy film. The aluminum alloy film is an aluminum film to which at least one of Cu that improves migration resistance and Si that improves alloy spike resistance is added. As the laminated wiring, for example, TiW
Wiring in which an aluminum alloy film is laminated on a film, a W film or a TiN film is used.

The interface circuit 3 is arranged inside the external terminal 2 at a position corresponding to one (or a plurality of) external terminals 2. The interface circuit 3 is composed of an input circuit cell and an output circuit cell, although its structure is not shown in detail. The input circuit cell is, for example, a complementary MI.
The interface circuit 3 is composed of an SFET (CMOS) and is arranged in the wiring layer of the first wiring layer of the two wiring layers and is connected as the interface circuit 3 used as an input unit. Further, in the input circuit cell, a protective resistance element and a clamp MISFET which form an electrostatic breakdown prevention circuit are arranged. The output circuit cell is composed of a complementary MISFET (and a bipolar transistor), and similarly, is connected as an interface circuit 3 used as an output section in a wiring arranged in the first wiring layer.

A power supply trunk line 5 is arranged above the interface circuit 3. This power supply trunk line 5 extends in the same direction as the arrangement direction of the plurality of interface circuits 3,
As shown in FIG. 1, the planar shape is a ring shape. The power supply trunk line 5 supplies power to the interface circuit 3 and also to a logic circuit (4) described later. The power supply trunk line 5 is arranged in the second wiring layer because the wiring arranged in the first wiring layer is used for connecting the input circuit cells or the output circuit cells of the lower interface circuit 3. It is composed of wiring.

The power supply trunk line 5 includes two reference voltage trunk lines 5.
A and 5C, two power supply voltage trunk lines 5B and 5D, total 4
Books are extended and organized. These reference voltage trunk lines 5A,
5C and power supply voltage trunk lines 5B and 5D are separated from each other by a predetermined distance in the wiring width direction and extend substantially parallel to each other in the wiring length direction. Each of the reference voltage trunk line 5A and the power supply voltage trunk line 5B arranged outside the power supply trunk line 5, that is, on the side of the external terminal 2 is used as an output unit 32 in a region surrounded by a dashed line in FIG. Power is supplied mainly to the interface circuit 3 that operates. Reference voltage main line 5 arranged inside power supply main line 5, that is, on the side of logic circuit 4
Each of C and the power supply voltage main line 5D supplies power mainly to the interface circuit 3 used as the input unit 31 in the area surrounded by the alternate long and short dash line in FIG.

Each of the reference voltage trunk lines 5A and 5C is externally supplied with a reference voltage, for example, the ground potential 0 [V] of the circuit through the reference voltage external terminal 2. Also, the power supply voltage trunk line 5
A reference voltage, for example, a power supply potential 5 [V] of the circuit is supplied to each of B and 5D from the outside through the power supply voltage external terminal 2. The reference voltage main line 5A is connected to the reference voltage external terminal 2 through a wiring arranged in the same wiring layer (second wiring layer). The other reference voltage trunk lines 5C are connected to the reference voltage external terminals 2 through the wirings arranged in the first wiring layer, and the power supply voltage trunk lines 5B and 5D are also arranged in the first wiring layer. Power supply voltage external terminal 2
Are connected to each.

The power supply main line 5 thus configured is shown in FIG.
As shown in, the boundary area between the input unit 31 and the output unit 32 is physically and electrically separated. That is, each of the reference voltage trunk lines 5A and 5C and the power source voltage trunk lines 5B and 5D of the power supply trunk line 5 is divided in the boundary region.

As a result, the reference voltage trunk line 5C and the power supply voltage trunk line 5D, which are arranged in the area of the input section 31 and mainly supply power to the interface circuit 3 of the input section 31, are in the area of the output section 32. Reference voltage trunk line 5
C, not directly connected to each of the power supply voltage main lines 5D. Moreover, the reference voltage trunk line 5 arranged in the area of the input unit 31
C, the power supply voltage main line 5D, the reference voltage main line 5C arranged in the area of the output section 32, the reference voltage external terminal 2 arranged independently of the power supply voltage main line 5D, the power supply voltage external Connected to each of the terminals 2.

On the contrary, it is arranged in the area of the output unit 32,
Each of the reference voltage trunk line 5A and the power supply voltage trunk line 5B that mainly supplies power to the interface circuit 3 of the output section 32 is
It is not directly connected to each of the reference voltage main line 5A and the power supply voltage main line 5B arranged in the area of the input unit 31. Moreover, the reference voltage trunk line 5A and the power supply voltage trunk line 5B arranged in the area of the output unit 32 are independent of the reference voltage trunk line 5A and the power supply voltage trunk line 5B arranged in the region of the input unit 31, respectively. Are connected to the reference voltage external terminal 2 and the power supply voltage external terminal 2, respectively.

FIG. 2 (layout diagram of the power supply trunk line) shows the layout of the power supply trunk line 5 with respect to the interface circuit 3, and the interface circuit 3 located at the array end of the input section 31 forming the boundary area is shown in FIG. Figure 2
The power supply trunk line 5 having the divided area shown in any of (C) (having the end of the power supply trunk line) is arranged. Similarly, the interface circuit 3 located at the array end of the output section 32 forming the boundary area is provided with the power supply trunk line 5 having a divided area as shown in either of FIG. 2B and FIG. 2C. In the interface circuit 3 arranged in a region other than the arrangement end of the input unit 31 and the arrangement end of the output unit 31, the power supply trunk line 5 having connectivity shown in FIG. 2A is arranged.

As shown in FIG. 1, a logic circuit 4 is arranged in the central area of the semiconductor integrated circuit device 1 employing the master slice method, that is, in the area surrounded by the interface circuit 3. The logic circuit 4 is not shown in detail in its configuration, but is formed by regularly arranging a plurality of basic cells (basic cells) having a basic design in a matrix. This basic cell is, for example, a complementary MISFET.
It is composed mainly of.

Next, a method for forming the semiconductor integrated circuit device 1 adopting the above-mentioned master slice method will be briefly described with reference to FIG. 3 (process flow diagram).

First, the logic function to be mounted on the semiconductor integrated circuit device 1 adopting the master slice method is designed and a logic circuit diagram is created <22>.

Next, the layout positions of the terminals of the semiconductor integrated circuit device 1 adopting the master slice method are designed and a layout layout diagram of the terminals is prepared <23>. The design of the arrangement position of the terminals determines the function of each of the plurality of external terminals 2, and also determines whether each of the plurality of interface circuits 2 is used for the input unit 31 or the output unit 32.

Next, based on the logic circuit diagram and the layout layout diagram of terminals, the layout of logic circuits, the layout of terminals, and the wiring are automatically performed by an automatic layout and wiring system (DA) using a computer.

First, based on the logic circuit diagram and the layout layout diagram of terminals, this information is input to the automatic layout and routing system as information that can be handled by the automatic layout and routing system.

Next, based on the information (terminal arrangement information) input to the automatic placement and routing system, in the arrangement of the plurality of interface circuits 3, the boundary area between the input section 31 and the output section 32 is determined. Search automatically <2
4>.

Next, based on the search information of this boundary area,
It is confirmed whether the external terminal 2 that can be connected to the power supply main line exists between the boundary regions, that is, in the region of the one input unit 31 or the one output unit 32 <25>. If the presence of this external terminal 2 cannot be confirmed, the layout of the terminal is reexamined. If the presence of the external terminal 2 is confirmed, the interface circuit 3 including the power supply trunk line 5 having the divided areas shown in each of FIG. 2B and FIG. The interface circuit 3 including the power supply main line 5 having the connectivity shown in FIG.

Next, the basic cells are arranged in the logic circuit (basic cell array) 4 based on the information (logic circuit information) input to the automatic placement and routing system <2.
7>.

Next, in the input circuit cell or the output circuit cell of the interface circuit 3 and in the basic cell of the logic circuit 4, wiring is automatically made, and the interface circuit 3 and the logic circuit 4 are connected. Wiring is automatically applied <28>. As a result, the semiconductor integrated circuit device 1 employing the master slice method is completed in the automatic placement and routing system.

Next, the information of the semiconductor integrated circuit device 1 adopting the master slice method completed by the automatic placement and routing system is converted into mask making data based on the design rule in this automatic placement and routing system. <2
9>.

Next, based on the mask making data,
A connection mask is formed with an electron beam drawing apparatus <30>.

Next, using the connection mask, a device process is performed <40> to complete the semiconductor integrated circuit device 1 employing the master slice method having a predetermined logic function.

Further, in the semiconductor integrated circuit device 1 adopting the master slice method, as shown in FIG. 4 (a layout diagram of a main part), the power supply trunk line 5 arranged on a specific interface circuit 3 is replaced with another power supply trunk line 5. You may divide from. Specifically, of the interface circuit 3 used as the output unit 32, the driving capability (drivability)
When the output circuit cells of two adjacent interface circuits 3 are electrically connected in parallel for the purpose of increasing
The power supply trunk line 5 that supplies power to the two interface circuits 3 and is arranged above is separated from the power supply trunk line 5 of the output unit 32. These two interface circuits 3
Is a so-called double buffer circuit and can enhance the driving capability, but on the contrary, the noise generated in the power supply main line 5 becomes large. The two interface circuits 3 are connected to one external terminal 2 of the two corresponding external terminals 2, and the other one external terminal 2 is connected to the power supply trunk line 5 as the power supply external terminal 2. .. In the present embodiment, the reference voltage trunk line 5A, which causes a particularly large fluctuation of the power supply, is connected to the external terminal 2.

As described above, according to the semiconductor integrated circuit device 1 adopting the master slice method of this embodiment, the following operational effects can be obtained.

(1) A plurality of interface circuits 3 are regularly arranged in one direction on the main surface of the semiconductor substrate, and each interface circuit 3 is arranged along the arrangement of the plurality of interface circuits 3. In a semiconductor integrated circuit device 1 adopting a master slice method, a plurality of external terminals 2 are arranged, and a power supply trunk line 5 extending in the arrangement direction of the interface circuits 3 is arranged on the plurality of interface circuits 3. Among the plurality of interface circuits 3, between the interface circuit 3 used as the input unit 31 and the interface circuit 3 used as the output unit 32, on the interface circuit 3 used as the input unit 31. Power supply trunk line 5 extending to the above, on the interface circuit 3 used as the output unit 32 Each of the extending power supply trunk lines 5 was divided, each of the divided power supply trunk lines 5 was connected to each of the independent external power source terminals 2 different from each other, and the divided power supply trunk lines 5 were divided. Place in the area. With this configuration, (A) even if noise occurs in the power supply trunk line 5 due to the circuit operation of the interface circuit 3 used as the output section 32, the power supply arranged on the interface circuit 3 used as the output section 32 Trunk line 5
On the other hand, since the power supply main line 5 arranged on the interface circuit 3 used as the input unit 31 is physically and electrically separated, the noise generated in the power supply main line 5 of the output unit 32 is generated by the input unit 31. Malfunction due to noise of the interface circuit 3 used as the input unit 31 without being transmitted to the power supply main line 5 (or malfunction of internal circuit)
Can be prevented. (B) Similar to the action and effect (A), even if noise is generated in the power supply trunk line 5 of the output unit 32, the power supply trunk line 5 and the power supply trunk line 5 of the input unit 31 extend parallel to each other. Since it does not exist, it is possible to prevent crosstalk in which noise generated in the power supply trunk line 5 of the output section 32 is transmitted to the power supply trunk line 5 of the input section 31, and prevent malfunction of the interface circuit 3 used as the input section 31 due to noise. it can. (C) The reliability of the circuit operation of the semiconductor integrated circuit device 1 employing the master slice method can be improved (the noise margin can be improved) based on the above-mentioned effects (A) and (B). Further, the circuit operating speed of the semiconductor integrated circuit device 1 adopting the master slice method can be increased.

(2) Among the interface circuits 3 used as the output section 32 of the means (1), a plurality of interface circuits 3 connected in parallel are some of the plurality of external terminals 2 corresponding thereto. The power supply trunk line 5 connected to the external terminal 2 of the power supply main line 5 and separated from the power supply trunk line 5 extending on the interface circuit 3 used as the output section 32 on the interface circuit 3 connected in parallel.
The divided power supply trunk lines 5 are connected to other external terminals 2 corresponding to the interface circuits 3 connected in parallel as power supply external terminals 2. With this configuration, (A) of the interface circuits 3 used as the output section 32, the interface circuit (double buffer output circuit) 2 connected in parallel has a high probability of generating noise during circuit operation, and the output section 32 Interface circuit 3 connected in parallel to power supply trunk line 5 arranged on interface circuit 32 used as
Since the power supply trunk line 5 arranged above is physically and electrically separated, noise generated in this separated power supply trunk line 5 is not transmitted to other power supply trunk lines 5 and is used as the output unit 32. It is possible to prevent malfunction of the interface circuit 3 due to noise (or malfunction of the interface circuit 3 used as the input unit 31). (B) Similar to the action and effect (A), even if noise occurs in the divided power supply trunk line 5, the power supply trunk line 5 and the power supply trunk line 5 of the output unit 32
Since each of them is opposed to each other and does not extend in parallel, it is possible to prevent crosstalk in which noise generated in the divided power supply trunk line 5 is transmitted to the power supply trunk line 5 of the output unit 32, and the interface used as the output unit 32. A malfunction due to noise of the circuit 3 can be prevented. (C) The reliability of the circuit operation of the semiconductor integrated circuit device 1 employing the master slice method can be improved (the noise margin can be improved) based on the above-mentioned effects (A) and (B). Further, the circuit operating speed of the semiconductor integrated circuit device 1 adopting the master slice method can be increased. (D) The interface circuits 3 connected in parallel can output an output signal from some of the corresponding external terminals 2, and the other external terminals 2 of the plurality become empty terminals. The other external terminal 2 can be effectively used as the power supply external terminal 2.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, the present invention can also be applied to the semiconductor integrated circuit device 1 adopting the master slice method, which adopts a three-layer wiring structure or a multilayer wiring structure of more than three layers.

The present invention is not limited to the master slice system, but can be widely applied to ASICs (application-specific ICs) such as semiconductor integrated circuit devices adopting the gate array system and the standard cell system.

[0062]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the semiconductor integrated circuit device adopting the master slice method in which the power supply main line extends on the interface circuit, the reliability in circuit operation can be improved.

In the semiconductor integrated circuit device adopting the master slice method in which the power supply trunk line extends on the interface circuit, the circuit operation speed can be increased.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit device adopting a master slice method according to an embodiment of the present invention.

FIG. 2 is a layout diagram of a power supply main line of a semiconductor integrated circuit device adopting the master slice method.

FIG. 3 is a process flow diagram of a semiconductor integrated circuit device adopting the master slice method.

FIG. 4 is a layout diagram of a main part of a semiconductor integrated circuit device adopting a master slice method according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit device, 2 ... External terminal, 3 ... Interface circuit, 4 ... Logic circuit, 5 ... Power supply trunk line, 31 ... Input part, 32 ... Output part.

Claims (2)

[Claims] 1. A plurality of interface circuits are regularly arranged in one direction on a main surface of a semiconductor substrate, and an external terminal corresponding to each interface circuit is arranged along the arrangement of the plurality of interface circuits. A semiconductor integrated circuit device employing a master slice method, wherein a plurality of interface circuits are arranged and a power supply trunk line extending in the arrangement direction of the interface circuits is arranged on the plurality of interface circuits. , Interface circuit used as input part,
A first power supply trunk line extending on the interface circuit used as the input unit and a second power supply trunk line extending on the interface circuit used as the output unit between the interface circuits used as the output units. Each of the first power supply trunk line and the second power supply trunk line are connected to respective independent external power supply external terminals, and the first power supply trunk line and the second power supply trunk line are separated from each other. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is arranged in a region. 2. The interface circuit used as the output unit according to claim 1, wherein a plurality of interface circuits connected in parallel are connected to some of the corresponding external terminals. A second connected circuit that extends on the interface circuit used as the output unit on a plurality of interface circuits connected in parallel;
A third power supply trunk line separated from the power supply trunk line is arranged, and the third power supply trunk line is connected with another external terminal corresponding to a plurality of interface circuits connected in parallel as a power supply external terminal.