JPH053252A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize the high speed circuit operation and the high integrity of an ASIC and improve the reliability of the circuit operation. CONSTITUTION:Macro-cells 7, 8 and 10 of an ASIC with which a high speed operation is achieved are connected to each other with first layer wirings 19 in a basic cell 12 or a basic cell 13. At the same time, the basic cells arranged along a second direction are connected to each other with the first layer wirings 19 and the basic cells arranged along a first direction are connected to each other with second layer wirings 21.

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, ASIC (A pplication S pecific I nte
grated C ircuit or A pplication S pecific Standar
d Product: A technology that is effective when applied to a specific purpose IC).

[0002]

The semiconductor integrated circuit device employing the standard cell system included in the design concept of the Related Art ASIC, automatic placement and routing using a computer system (DA: D esign
Based on the support of A utomation), design and development is carried out.
The standard cell method is generally a plurality of types of macro cells (functional circuit blocks) that have been optimally designed in advance.
Is registered in the automatic placement and routing system, some macro cells are placed as required, and some of these macro cells are connected to each other. Therefore, the semiconductor integrated circuit device adopting the standard cell system has characteristics that the design and development period is short, the integration density and the circuit performance are relatively high, and is suitable for high-mix low-volume production.

As a semiconductor integrated circuit device adopting this type of system, a technique which enables high integration density and high-speed circuit operation has been reported, for example, in the following documents. 19
89 years, Sea Eye Sea Sea (CICC: C ustom I n
tegrated C ircuits C onference), 8.2 Section "0.8
μm 1.4 MTr. CMOS SOG based on Column
Macro-cell ".

The semiconductor integrated circuit device reported in this technique adopts a two-layer wiring structure, and two first-layer power supply voltage wirings and a first wiring which are separated from each other and extend in the same first direction.
A second-layer reference voltage wiring, two second-layer power supply voltage wirings and two second-layer reference voltage wirings that are separated from each other and extend in a second direction orthogonal to the first direction are arranged. That is, the first
The power supply wirings of the first-layer power supply voltage wiring, the first-layer reference voltage wiring, the second-layer power supply voltage wiring, and the second-layer reference voltage wiring are arranged in a grid pattern.

Power supply wiring arranged in a grid pattern
Within each defined and enclosed area are multiple repeating groups.
The basic cells (unit cells) that will be the circuit pattern are distributed.
Placed. A plurality of basic cells are connected in series p
Channel MOSFET (MetalOxideSemiconductor
FieldEffectTransistor) and several connected in series
N-channel MOSFET, that is, a plurality of CMOSs
(Complemantary MOS). Basic set
Multiple p-channel MOSFETs, multiple n-channel
Any gate length direction of the channel MOSFET is the second layer.
Direction of extension of power supply voltage wiring and second layer reference voltage wiring
It is arranged in conformity with (the second direction).

The connection between the plurality of MOSFETs arranged in the basic cell (interconnection in the basic cell) is performed by the first layer signal wiring. Power is supplied to the plurality of MOSFETs arranged in the basic cell mainly by using either the second-layer power supply voltage wiring or the second-layer reference voltage wiring.

Between the basic cells adjacent to each other, the first-layer signal wiring used as a connection in the basic cell is used, and the first-layer signal wiring (in the same wiring layer) integrally formed with the basic cell is connected. . The first-layer signal wiring that connects the basic cells is formed in a wiring layer that is independent of both the second-layer power supply voltage wiring and the second-layer reference voltage wiring. Can extend transversely. Further, the first-layer signal wiring cannot be extended in the second direction because the first-layer power supply voltage wiring and the first-layer reference voltage wiring are arranged in the same wiring layer as the first-layer signal wiring. That is, the basic cells can be connected only in the first direction, and a plurality of basic cells can be combined in the first direction to form a macro cell having a predetermined logic function.

When connecting the above-mentioned basic cells, since the first-layer signal wiring integrated with the first-layer signal wiring used for connecting in the basic cell is used, the second-layer signal wiring is used. Is provided and there is no intervening region for connecting to the second layer signal wiring, a so-called wiring channel region. In other words, the semiconductor integrated circuit device reported in the above-mentioned technique eliminates the wiring channel region between the basic cells in the macro cell and can shorten the wiring length between the basic cells as compared with the case where this wiring channel region exists. So
The signal transmission speed can be increased and the macrocell can operate at high speed. Further, in the semiconductor integrated circuit device reported in the above-mentioned technique, since the wiring channel region between the basic cells in the macro cell is abolished, the area occupied by the macro cell can be reduced and high integration can be achieved.

[0009]

However, the semiconductor integrated circuit device to which the above-mentioned reported technique is applied is not considered in the following points.

(A) In the above-described macro cell, the extending direction of the first layer signal wiring is restricted, and the extending is possible only in the first direction. Therefore, the connection between the basic cells is limited to this first direction. When designing a macro cell, a circuit is sequentially assigned to each basic cell arranged in the first direction.
In the first direction, when the unused MOSFETs are left unconnected in the basic cell after the circuit is allocated, the basic cells in which the unused MOSFETs exist are adjacent to each other in the first direction, or are relatively close to each other. Several unused MOSFETs can be used when placed at a distance.

However, the first-layer signal wiring is
Since the first-layer power supply voltage wiring and the first-layer reference voltage wiring are arranged, they cannot extend in the second direction. In other words, if there is an unused MOSFET in the basic cell, the first
Unused MOs in adjacent basic cells or in relatively close basic cells in the direction
Even when the SFET does not remain and the unused MOSFET remains in the basic cell arranged in the second direction, the unused MOSFET in the basic cell becomes a completely useless element. Therefore, the unused M in the macro cell
Since the probability that the OSFET remains will increase (the effective utilization of the element will decrease) and the area occupied by the macro cell will increase,
The degree of integration of the semiconductor integrated circuit device is reduced.

(B) When a large number of unused MOSFETs remain in the macro cell, the connection length in the basic cell and the connection length between the basic cells are unused MOSFs.
It becomes longer as it passes or avoids ET. For this reason, the signal transmission speed in the macro cell becomes slow, and the circuit operation speed of the macro cell decreases.

(C) Further, with the progress of high integration and high-speed operation circuits, the number of MOSFETs arranged per unit area increases, and the power consumption increases in proportion to the increase in power supply capacity. Is required. To increase the power supply capacity, simply increase the wiring width of each power supply wiring of the first layer power supply voltage wiring, the first layer reference voltage wiring, the second layer power supply voltage wiring, and the second layer reference voltage wiring. It can be handled by increasing (decreasing current density).

However, an increase in the wiring width of the power supply wiring reduces the number of MOSFETs arranged in the basic cell, so that the degree of integration of the semiconductor integrated circuit device decreases. In addition, an increase in the wiring width of the power supply wiring reduces the number of connections within the basic cell and the number of connections between the basic cells (the number of first-layer signal wires), and the unused MOSFETs that cannot be connected due to the insufficient number of connections. Is increased (the effective utilization of the element is reduced), the integration degree of the semiconductor integrated circuit device is reduced. Furthermore, when the number of connections in the basic cell or the number of connections between the basic cells is small, it is necessary to dispose the wiring channel region in another region. The degree of integration of the integrated circuit device is reduced.

(D) Further, with the progress of high integration and high speed operation circuits, the number of signal lines arranged per unit area increases. Therefore, a lot of crosstalk noise (coupling noise) is generated between adjacent signal lines,
The reliability of the circuit operation of the semiconductor integrated circuit device decreases.

The objects of the present invention are as follows. (A) A high-speed circuit operation is achieved in the ASIC. (B) In the ASIC, increase the degree of integration. (C) In the ASIC, reliability in circuit operation is improved.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of basic cells including a plurality of MISFETs whose gate length direction coincides with the first direction are regularly arranged in the first direction and a second direction intersecting with the first direction. In a semiconductor integrated circuit device (ASIC) in which a macro cell having a predetermined function is configured by connecting between the MISFETs and some of the plurality of basic cells, and between the MISFETs in each of the basic cells in the macro cell. Are connected by the first-layer signal wiring arranged in a layer above the gate electrode of the MISFET in this basic cell, and between the basic cells arranged adjacent to each other in the second direction in the macro cell, Of the first-layer signal wirings, they are connected by the first-layer signal wirings extending in the second direction, and are connected in the macrocell in the first direction. The basic cells arranged in the same manner are arranged in a layer above the first layer signal wiring and are connected by the second layer signal wiring extending in the first direction, and are connected in the first direction. The MISFETs in the respective basic cells arranged adjacent to each other are supplied with power from the second-layer power supply wiring which is in the same layer as the second-layer signal wiring and extends in the same first direction. The macro cell is one of a floating point arithmetic circuit, an integer arithmetic circuit, and a store buffer circuit. Also, the macro cell is configured by a standard cell method.

(2) The power supply wiring of the second layer of the above-mentioned means (1) has a wiring width dimension almost equal to the gate width dimension of this MISFET on the upper layer of the MISFET in the basic cell, and has a first direction. Extend to.

(3) The source region or the drain region of the MISFET in the basic cell according to the means (1) or (2) is the same wiring layer as the first layer signal wiring connecting the MISFETs in the basic cell. Is shunted with the wiring for the first layer shunt.

(4) The first layer signal wiring according to any one of the means (1) to (3) is composed of a refractory metal film,
The second-layer signal wiring and the second-layer power wiring may be a single layer of an aluminum film or an aluminum alloy film, or the high melting point metal film, a high melting point metal alloy film, It is composed of a laminate in which any of the melting point metal nitride films is formed.

(5) An upper layer of the basic cell in the macrocell according to any one of the means (1) to (4), which is arranged above the second layer signal wiring and extends in the second direction. While the third-layer signal wiring extends, this third
A fourth-layer signal wiring and a fourth-layer power supply wiring, which are arranged in a layer above the fourth-layer signal wiring and extend in the first direction, extend.

(6) The fourth layer power wiring is arranged on the second layer signal wiring of the means (5), and the fourth layer signal wiring is arranged on the second layer power wiring. Will be placed.

[0025]

According to the above-mentioned means (1), the following operational effects can be obtained.

(A) The first-layer signal wiring in the same layer as the first-layer signal wiring (inter-basic cell wiring) connecting the MISFETs in each basic cell in the macro cell extends in the second direction. (The wiring in the basic cell is used as it is as the wiring between basic cells), and the signal wiring other than the signal wiring of the first layer is arranged between the basic cells arranged adjacent to each other in the second direction and Since there is no wiring channel region connecting the signal wiring and the other signal wiring, the area occupied by the macro cell can be reduced and the integration degree of the semiconductor integrated circuit device can be improved.

(B) A basic cell (or MISFE in the basic cell) in which the second-layer signal wiring and the second-layer power supply wiring extend in the first direction and are arranged in the first direction.
T) can be used to sequentially arrange the circuits in the first direction, and the probability of occurrence of unused (useless) basic cells (or MISFETs in the basic cells) that are not used as circuits in the first direction can be determined. Since this can be reduced, the area occupied by the macro cell can be reduced by effectively using the basic cell, and the degree of integration of the semiconductor integrated circuit device can be improved.

(C) Based on the function and effect (A), the wiring length of the first-layer signal wire extending in the second direction in the macro cell can be shortened, and similarly, based on the function and effect (C), Since the second signal wiring layer extending in the first direction in the macro cell can be shortened, the operating speed of the macro cell can be increased, and as a result, the operating speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (2), the second-layer power supply wiring is formed in another independent wiring layer with respect to the first-layer signal wiring connecting the MISFETs in the basic cell. Without being restricted by the signal wiring of the first layer, the wiring width dimension of the second layer power source wiring is close to the gate width dimension of the MISFET (to be precise, the terminal on one end side and the other end side of the gate electrode of the MISFET). Since it can be increased to an allowable dimension between the terminals and the terminals, the resistance value of the second layer power supply wiring is reduced to improve the power noise absorption performance (as a result, the waiting time of the circuit operation is shortened), and the semiconductor The operating speed of the integrated circuit device can be increased.

According to the above-mentioned means (3), the resistance value of the source region or the drain region of the MISFET in the basic cell can be reduced and the power supply speed or the signal transmission speed can be increased. Therefore, the operating speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (4), interdiffusion between Si of the drain region or source region of the MISFET in the basic cell and Al of the second layer signal wiring or the second layer power source wiring is carried out. Since the connection resistance value between the drain region or the source region and the second layer signal wiring or the second layer power supply wiring can be reduced by the first layer signal wiring as the intermediate layer, the operating speed of the macrocell can be reduced. As a result, the operating speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (5), the third layer signal for connecting between the basic cells or between the macro cells by utilizing the empty region of the upper layer of the basic cell (apparently within the occupied area of the basic cell) Since the wiring channel region for arranging the wiring and the fourth layer signal wiring and arranging the third layer signal wiring and the fourth layer signal wiring between the basic cells is eliminated, the macro cell corresponding to this wiring channel region is excluded. Alternatively, the occupation area between the macro cells can be reduced and the integration degree of the semiconductor integrated circuit device can be improved.

As a result, the intervals of the basic cells and the intervals of the macro cells in the macro cell can be reduced, and the wiring lengths of the third-layer signal wiring and the fourth-layer signal wiring can be shortened. The speed can be increased and the operating speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (6), as compared with the case where the fourth layer signal wiring is arranged on the upper layer of the second layer signal wiring, the second layer signal wiring and the fourth layer signal wiring are arranged. Since it is possible to increase the distance between the second layer signal wiring and the fourth layer signal wiring, it is possible to reduce the crosstalk noise (coupling noise) between the second layer signal wiring and the fourth layer signal wiring. The reliability can be improved.

The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device adopting the standard cell system included in the design concept of ASIC.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (layout diagram) shows the configuration of a semiconductor integrated circuit device adopting a standard cell system according to an embodiment of the present invention.

As shown in FIG. 1, a semiconductor integrated circuit device 1 adopting the standard cell system is composed of a single crystal silicon substrate having a substantially square planar shape. A plurality of external terminals (bonding pads) are provided in the peripheral region of the element forming surface along each square side of the semiconductor integrated circuit device 1.
2 are arranged.

Inside and close to the external terminal 2.
Element formation of the semiconductor integrated circuit device 1 in the contacted region
The input / output buffer circuit 3 is arranged on the surface. I / O bag
The circuit 3 corresponds to the arrangement of the external terminals 2 (for example, 1: 1 pair).
It is arranged accordingly. The input / output buffer circuit 3 has a detailed
Input buffer circuit cell and output (not shown)
Buffer circuit cells are arranged. Input buffer circuit cell
Is, for example, a complementary MISFET forming an input first-stage circuit
(MetalInsulatorSemiconductorFieldEffect
Transistor), a resistance element that constitutes an electrostatic breakdown prevention circuit
And clamp MISFETs are arranged. Output buffer
Circuit cell is, for example, a complementary type M that constitutes the final output stage circuit.
ISFET, bipolar transistor, etc. are arranged.
The input / output buffer circuit 3 is provided for each of the input buffer circuit cells.
Between semiconductor elements, between semiconductor elements in output buffer circuit cell
Selectively connect any of the two, input buffer circuit, output
Any of the buffer circuits can be configured.

Within the cell region surrounded by the input / output buffer circuit 3, a plurality of macro cells (also called logic circuit blocks or functional circuit blocks) 4 are provided in the central portion of the element formation surface of the semiconductor integrated circuit device 1. ~ 11 are arranged. The macro cell 4 is a translation lookaside buffer (TLB) circuit. The macro cell 5 is an address array circuit. The macro cell 6 is an instruction cache memory circuit. The macro cell 7 is an integer arithmetic circuit. The macro cell 8 is a store buffer circuit. The macro cell 9 is a random control logic circuit. The macro cell 10 is a floating point arithmetic circuit. The macro cell 11 is a data cache memory circuit.

Each of these macro cells 4 to 11 is constructed by combining a plurality of basic cells (basic cells) as a basic circuit pattern of a minimum unit which is repeatedly used. The basic cell is a basic circuit for assembling any of the macro cells 4 to 11, for example, an OR circuit, an AND circuit, and a NAN.
A logic circuit such as a D circuit and an EOR circuit, and a functional circuit such as a flip-flop circuit, a half adder, and a delay latch circuit can be formed.

The semiconductor integrated circuit device 1 adopting the standard cell method of the present embodiment is a so-called spread method (SOG: S ea o f g ates) in which basic cells are regularly arranged in a matrix in almost the entire cell area. ). The laying method is basically used in the macro cell as a wiring channel region that connects the basic cells on the region of the basic cell to which the basic circuit is not assigned. Similarly, in the spread method, an area in which no macro cell is arranged is used as a wiring channel area for connecting macro cells in the cell area.

Macro cells 4-1 mounted on the semiconductor integrated circuit device 1 adopting the standard cell system shown in FIG.
The macro cell (integer arithmetic circuit) 7, the macro cell (store buffer circuit) 8 and the macro cell (floating point arithmetic circuit) 10 among 1 are operated at high speed and are different from the other macro cells 4, 5, 6, 9 and 11. The design is done.

Next, in the semiconductor integrated circuit device 1 adopting the above-mentioned standard cell system, the structure of the basic cell used for each of the macro cells 7, 8 and 10 in which the high speed circuit operation is performed is shown in FIG. (Fig.) Will be used for brief explanation.

The basic cell 12 shown in FIG. 3 is composed of, but not limited to, seven complementary MISFETs. One complementary MISFET is one p-channel M
It is composed of an ISFET and one n-channel MISFET. Basic cell 12 does not actually exist,
For the sake of convenience, reference numeral 12 is assigned to FIG. 3 to define the area surrounded by the alternate long and short dash line (the same applies to the basic cell 13 described later).

Complementary MISF of the basic cell 12
The p-channel MISFET Qp of ET is formed in the main surface of the n-type well region formed in the main surface portion of the p-type single crystal silicon substrate in the region defined by the element isolation insulating film 14. The p-channel MISFET Qp is mainly composed of an n-type well region which is a channel forming region, a gate insulating film, a gate electrode 15, and a pair of p-type semiconductor regions 17 which are a source region and a drain region.

The plurality of p-channel MISFETs Qp in the basic cell 12 are arranged so that their respective gate length directions (first direction) coincide with each other, and most of them (6 out of 7) are arranged.
Are arranged in a straight line along the gate length direction. Of the plurality of p-channel MISFETs Qp, two p-channel MISFETs Qp adjacent to each other in the gate length direction are provided.
Are integrally formed (electrically connected) with one p-type semiconductor region 17 and shared.

Complementary MISFET of basic cell 12
The n-channel MISFET Qn of the device isolation insulating film 14
In the region whose periphery is defined by, the main surface of the p-type well region is formed in the main surface portion of the p-type single crystal silicon substrate. The n-channel MISFET Qn includes a p-type well region which is a channel forming region, a gate insulating film, and a gate electrode 1.
5, a pair of n-type semiconductor regions 16 which are a source region and a drain region are mainly formed.

The plurality of n-channel MISFETs Qn in the basic cell 12 include a plurality of p-channel MISFEs.
Similar to the arrangement of TQp, the respective gate length directions are arranged so as to coincide with each other, and most of them (6 of 7) are arranged substantially in a straight line along the gate length direction. Two n-channel MISFETs Qn adjacent to each other in the gate length direction among the plurality of n-channel MISFETs Qn form one n-type semiconductor region 16 integrally (electrically connected) and are shared. In the basic cell 12, each of the plurality of n-channel MISFETs Qn has a plurality of p-types.
The channel MISFETs Qp are arranged substantially straight in the gate width direction (second direction) thereof.

P-channel MI of the basic cell 12
The gate insulating film of each of the SFET Qp and the n-channel MISFET Qn is formed of, for example, a silicon oxide film.

The gate electrode 15 is not limited to this structure, but is a laminated film in which a refractory metal silicide film (WSi ₂ film in this embodiment) is laminated on a polycrystalline silicon film for the purpose of increasing the operation speed. It is formed. The gate electrode 15 is formed in the first layer gate material forming step of the manufacturing process of the semiconductor integrated circuit device 1 adopting the standard cell method,
Although not limited to this value, the gate length is 0.5 [μ
m].

Both the gate electrodes 15 of the p-channel MISFET Qp and the n-channel MISFET Qn are drawn out to the element isolation insulating film 14 in the gate width direction to form a terminal. This terminal constitutes a connection area (corresponding to the terminal of the basic cell 12) with the signal wiring (19) in the upper layer. The terminal of the gate electrode 15 is led out in the gate length direction from the position where the gate electrode 15 is arranged to a position where it can be connected to either the p-type semiconductor region 17 or the n-type semiconductor region 16 by a straight line extending in the second direction. To be done. That is, the terminal of the gate electrode 15 has a plurality of p-channel MISFETs Q.
p, the gate electrodes 15 of the plurality of n-channel MISFETs Qn are arranged at an interval substantially similar to the interval (gate electrode pitch) of the gate electrodes 15 in the gate length direction, and are ½ of the interval of the gate electrodes 15. It is configured at a position shifted in the gate length direction by an amount corresponding to the dimension.

[0053] The p-channel MISFET Qp, the n-channel MISFETQn each is not limited to this structure, and a LDD (L ightly D oped D rain ) structure. P-channel MISFE adopting this LDD structure
Each of the TQp and the n-channel MISFETQn has a high hot carrier breakdown voltage and has a characteristic that the short channel effect can be reduced.

The basic cell 12 configured in this way
For example, as shown in FIG. 2 (delay latch circuit diagram), a delay latch circuit, which is one basic circuit configuring any of the macrocells 7, 8, and 10, is assigned. The delay latch circuit shown in FIG. 2 includes seven p-channel MISFETs Qp1 to Qp7 and seven n-channel MIs.
SFET Qn1 to Qn7, a total of 7 complementary MISFE
Composed of T. CK is a reference clock signal, IN is an input signal, and OUT is an output signal. p channel MISFE
A power supply voltage Vcc is supplied to the source region of TQp, and as the power supply voltage Vcc, for example, a circuit operating voltage 5 [V] or a step-down power supply voltage 3.3 [V] or 3.0 [V] is used. A reference voltage GND is supplied to the source region of the n-channel MISFET Qn, and for example, the ground voltage 0 [V] of the circuit is used as the reference voltage GND.

The basic cell 12 shown in FIG. 3 shows a state in which the delay latch circuit shown in FIG. 2 is assigned. The semiconductor integrated circuit device 1 adopting the standard cell method of the present embodiment has a four-layer wiring structure. The first-layer wiring is shown in FIG. 3, the second-layer wiring is shown in FIG. 5 (main part plan view) shows a state in which each of the third layer wiring and the fourth layer wiring is arranged.

As shown in FIG. 3, the complementary MISFET in the basic cell 12 is basically the first layer signal wiring 1
Connected at 9 (wiring in the basic cell). The first-layer signal wiring 19 is arranged above the complementary MISFET (more accurately, the gate electrode 15 and an emitter extraction electrode 34 described later) with an interlayer insulating film interposed. The first-layer signal wiring 19 passes through the connection hole (contact hole) 18 formed in the interlayer insulating film, the terminal of the gate electrode 15, the p-type semiconductor region 17 of the p-channel MISFET Qp, and the n-type semiconductor of the n-channel MISFET Qn. It is connected to any of the regions 16.

The first-layer signal wiring 19 is allowed to extend in either the first direction or the second direction in the basic cell 12, most of which are on the terminal of the gate electrode 15 and p-type. It passes through either the semiconductor region 17 or the n-type semiconductor region 16 and is connected to either one at a predetermined position.

The first-layer signal wiring 19 is formed in the first-layer wiring material forming step of the manufacturing process, and for example, electromigration resistance (EMD) is improved, stress migration resistance (SMD) is improved, and miniaturization is performed. For the main purpose, the resistance value is about one digit higher than that of the aluminum film or aluminum alloy film, but the allowable current density is 3
It is formed of a refractory metal film which is about 4 times larger. As the refractory metal film, a W film deposited by a sputtering method on the W film deposited by the CVD method for the purpose of improving the step coverage on the step difference of the underlying layer such as the connection hole 18 and on the W film deposited by the sputtering method for the purpose of improving the adhesion to the underlying layer. A W film having a double structure is used. First
In the case of the above W film, the layer signal wiring 19 has a film thickness of about 0.3 to 0.5 [μm] and a wiring width of about 1.0, for example.
Each is set to about [μm].

In the basic cell 12, the p-type semiconductor region 17 serving as the source region of the p-channel MISFET Qp supplied with the power supply voltage Vcc is the first layer formed in the same wiring layer as the first layer signal wiring 19. The eye shunt wiring 19 is electrically connected through a plurality of connection holes 18 arranged in the second direction (gate width direction). Similarly, the n-channel MISFE to which the reference voltage GND is supplied is supplied.
The n-type semiconductor region 16 serving as the source region of TQn is electrically connected through a connection hole 18 in which a plurality of first layer shunt wirings 19 are arranged. The first-layer shunt wiring 19 can reduce the resistance value of each of the p-type semiconductor region 17 and the n-type semiconductor region 16. The first-layer shunt wiring 19 and the first-layer signal wiring 19 each have a function as a barrier metal film, and the second-layer wiring (2
1) Al, p-type semiconductor region 17, and n-type semiconductor region 16
Alloy spikes due to interdiffusion with any of Si can be reduced.

Complementary MIS in the basic cell 12
First layer signal wiring 19 used as a connection between FETs
Is a first-layer signal wiring 19 that connects between the basic cells 12 arranged adjacent to each other in the second direction (gate width direction) (or between basic circuits formed by the basic cells 12).
Also used as. As will be described later, the first-layer signal wiring 19 passes through the upper layer of the basic cell 12 and supplies power to the basic cell 12 directly. The second-layer power supply voltage wiring (Vcc) 21 and the second-layer reference voltage. Wiring (GN
D) is formed in a wiring layer different from that of 21 and independently (second)
If it extends in the direction, it is not restricted by the arrangement position or the extending direction). That is, the first-layer signal wiring 19 connecting between the basic cells 12 is the complementary MI in the basic cells 12.
It is integrally formed with and electrically connected to the first-layer signal wiring 19 that connects between the SFETs (the connection inside the basic cell 12 is directly drawn out in the second direction and the basic cell 1 is connected).
You can connect between the two). Therefore, when connecting the basic cells 12 arranged adjacent to each other in the second direction, another wiring layer, for example, a second layer wiring is arranged and a wiring channel region serving as a connection region with the second layer wiring. Is not necessary.

The first-layer signal wiring 19 and the first-layer shunt wiring 19 are not limited to the W film described above, but may be a refractory metal film such as a Mo film, a WSi ₂ film, or a MoSi ₂ film.
A high melting point metal silicide film such as a film, a high melting point metal film or a laminated film in which a high melting point metal silicide film is laminated on a polycrystalline silicon film may be formed.

In the upper layer of the signal wiring 19 of the first layer, as shown in FIG.
Second layer signal wiring (S) 21, second layer power supply voltage wiring (Vc
c) and the second layer reference voltage wiring (GND) are arranged. These second-layer wirings are arranged on the first-layer signal wirings 19 with an interlayer insulating film interposed, and are connected to the first-layer wirings through connection holes (through holes) 20 formed in the interlayer insulating film. It is electrically connected. The second layer wiring is basically used as a wiring extending in the first direction (gate length direction).

The second-layer power supply voltage wiring 21 is composed of a plurality of p-channel MISFETs Qp in the basic cell 12.
In the upper layer, the plurality of p-channel MISFETs
It extends along the arrangement direction (first direction) of Qp. The second layer power supply voltage wiring 21 is a p-channel M having a large driving capacity (large size) mainly for the purpose of reducing its resistance value.
The wiring width dimension is the same as or close to the gate width dimension of the ISFET Qp. In other words, the second-layer power supply voltage wiring 21 has the maximum wiring width dimension within the allowable range between the terminals drawn to one end and the other end of the gate electrode 15 of the p-channel MISFET Qp. Largely composed.

Similarly, the second-layer reference voltage wiring 21 is composed of a plurality of n-channel MISFETs in the basic cell 12.
In the upper layer of Qn, the wiring width dimension is the same as or close to the gate width dimension of the n-channel MISFET Qn that extends in the first direction and has a large driving capability.

In the basic cell 12, the second-layer signal wiring 21 is provided between the second-layer power supply voltage wiring 21 and the second-layer reference voltage wiring 21 (p channel MISFET Qp).
And the n-channel MISFETQn), the outside of the second layer power supply voltage wiring 21 (upper side in FIG. 4) and the outside of the second layer reference voltage wiring 21 (lower side in FIG. 4). Is located in. The second layer signal wiring 21 is
It is used for connection between the basic cells 12 adjacent to each other in the direction (gate length direction) or between the basic circuits formed by the basic cells 12 (this basic circuit is also a macro cell which is smaller than the macro cells 4 to 11 described above).

The second layer wiring 21 is the second wiring of the second manufacturing process.
It is formed in the step of forming the first layer wiring material, for example, TiW
The film, the aluminum alloy film, and the TiW film are sequentially laminated to form a three-layer laminated film. The lower TiW film has a function as a barrier metal film and is effective for both EMD and SMD. The upper TiW film can prevent aluminum hillocks and can prevent reflection on the surface of the aluminum alloy film (reduce diffraction development during exposure when forming a mask of a photolithography technique). Aluminum alloy film is used as a base material for effective wiring,
Aluminum to which at least one of Cu that can improve both D and SMD and Si that can reduce the alloy spike phenomenon is added is used. The second layer wiring 21 is
For example, a relatively thin film thickness of about 0.5 to 0.7 [μm] is formed for the purpose of leveling the surface of the underlying interlayer insulating film of the upper wiring. The second layer power supply voltage wiring 21, the second
Each of the layer reference voltage wirings 21 is, for example, 8.5 to 9.0 [μ
[m]] and the second layer signal wiring 2
1 has a wiring width dimension of, for example, about 1.0 [μm].

When the second-layer power supply voltage wiring 21 is connected to the p-type semiconductor region 17 corresponding to the source region of the p-channel MISFET Qp of the basic cell 12, the first
The wiring 19 for the layer shunt is interposed. Similarly, when the second-layer reference voltage wiring 21 is connected to the n-type semiconductor region 16 corresponding to the source region of the n-channel MISFET Qn of the basic cell 12, the first-layer shunt wiring 19 is formed.
Is intervened. The wiring 19 for the first layer shunt is basically the same as the power supply wiring 21 for the second layer and the p-type semiconductor region 17.
Between the second-layer reference voltage wiring 21 and the n-type semiconductor region 1
6 and 6 each have a function as a barrier metal film.

As the second layer wiring 21, for example, a TiN film may be used instead of the lower and upper TiW films, and an aluminum film may be used instead of the intermediate aluminum alloy film.

In the upper layer of the second layer wiring 21, on the basic cell 12, the third layer signal wiring (S) 23 as shown in FIG. 5 and the third layer shown in FIG. 12 (main part plan view). Third power supply voltage wiring (Vcc) and third layer reference voltage wiring (G
ND) is arranged. These third layer wirings are arranged on the second layer wirings 21 with an interlayer insulating film interposed, and are electrically connected to the second layer wirings through connection holes (through holes) 22 formed in the interlayer insulating film. Connected. The third layer wiring is basically used as a wiring extending in the second direction (gate width direction).

The third-layer signal wiring 23 includes the macrocells 4 to 4.
In FIG. 11, it is used as a connection between the basic cells 12 arranged in the second direction or between the basic circuits formed by the basic cells 12. In addition, the third-layer signal wiring 23 is also used as a connection of each of the macro cells 4 to 11 in the first direction.

As shown in FIG. 12, the third-layer power supply voltage wiring 23 and the third-layer reference voltage wiring 23 are separated from each other in the first direction by a predetermined dimension and extend substantially parallel to the second direction. Exists The third-layer power supply voltage wiring 23 is composed of a lower-layer second-layer power supply voltage wiring 21 and an upper-layer fourth-layer power supply voltage wiring (Vc).
c) It is configured for the purpose of connecting between 25 and. Similarly,
The third-layer reference voltage wiring 23 is formed for the purpose of connecting the lower-layer second-layer reference voltage wiring 21 and the upper-layer fourth-layer reference voltage wiring (GND) 25.

The third layer wiring 23 is the third wiring of the manufacturing process.
It is formed in the step of forming the wiring material for the second layer, and basically has the same structure as that of the wiring for the second layer.
It is formed with a relatively thin film thickness of about [μm]. The third
Each of the third-layer power supply voltage wiring 23 and the third-layer reference voltage wiring 23 has a wiring width of, for example, about 8.5 to 9.0 [μm], and the third-layer signal wiring 21 has, for example, about 1. 0 [μ
[m]].

As shown in FIGS. 5 and 12, the upper part of the basic cell 12 in the upper layer of the third layer wiring 23 is as follows.
Fourth layer signal wiring (S) 25, fourth layer power supply voltage wiring 2
The fifth and fourth layer reference voltage wirings 25 are arranged. These fourth layer wirings are arranged on the third layer wirings 23 with an interlayer insulating film interposed, and are electrically connected to the third layer wirings through connection holes (through holes) 24 formed in the interlayer insulating film. Connected. The fourth layer wiring is basically used as a wiring extending in the first direction (gate width direction).

The fourth layer signal wiring 25 includes macro cells 4 to
In FIG. 11, it is used as a connection between the basic cells 12 arranged in the first direction or between the basic circuits formed by the basic cells 12. In addition, the fourth-layer signal wiring 25 is also used as a connection for each of the macro cells 4 to 11 in the first direction. The fourth layer signal wiring 25 is also used as a critical path wiring for a reference clock signal or the like.

The fourth-layer power supply voltage wiring 25 and the fourth-layer reference voltage wiring 25 are separated from each other in the second direction with a predetermined dimension and extend substantially parallel to each other in the first direction. The fourth layer power supply voltage wiring 25 supplies the power supply voltage to the lower third layer power supply voltage wiring 23. The fourth-layer reference voltage wiring 25 supplies a reference voltage to the lower-layer third-layer reference voltage wiring 23.

The fourth layer wiring 25 is the fourth wiring of the manufacturing process.
A comparatively thick film of about 1.0 [μm], which is formed in the layer wiring material forming step and basically has a structure similar to that of each of the second layer wiring 21 and the third layer wiring 23, for example. Formed in thickness. Each of the fourth layer power supply voltage wiring 25 and the fourth layer reference voltage wiring 25 has, for example, 4.0 to 4.5 [μ].
[m]] and the fourth layer signal wiring 2
5 has a wiring width dimension of, for example, about 2.0 to 2.5 [μm].

Of the fourth layer wiring 25, the fourth layer power supply voltage wiring 25 and the fourth layer reference voltage wiring 25 are respectively
Second lower layer signal wiring 21 extending in the same direction as that
Placed in the upper layer of. In addition, the fourth layer signal wiring 2
5 is arranged in the upper layer of each of the lower layer second layer power supply voltage wiring 21 and the second layer reference voltage wiring 21 extending in the same direction. That is, the line connecting the arrangement position of the second layer signal wiring 21 and the arrangement position of the fourth layer signal wiring 25 is the arrangement position of the second layer power supply voltage wiring 21 and the second layer reference voltage wiring 21. Fourth layer power supply voltage wiring 25 and fourth layer
Intersects the line connecting the placement position of the layer reference voltage wiring 25,
Arrangement position of the second layer signal wiring 21, the fourth layer signal wiring 2
The distance between each of the arrangement positions of 5 is larger than that in the case where they are stacked vertically. As a result, the second-layer signal wiring 2
Crosstalk noise (coupling noise) generated between the first and fourth layer signal wirings 25 can be reduced.

Further, the configuration of a basic cell other than the basic cell 12 used for each of the macro cells 7, 8 and 10 in which the high speed circuit operation described above is performed is shown in FIG.
To explain briefly.

The basic cell 13 shown in FIG. 7 is not limited to this number, but includes three p-channel MISFETs Q.
p, eight n-channel MISFETs Qn and one vertical npn-type bipolar transistor Tr. P channel MISFET of this basic cell 13
The structures of the Qp and n-channel MISFETQn are basically the p-channel MIS of the basic cell 12 described above.
The same applies to the FET Qp and the n-channel MISFET Qn.

The npn-type bipolar transistor Tr of the basic cell 13 is composed of an n-type collector region, a p-type base region and an n-type emitter region in a region surrounded by the element isolation region. The n-type collector region is
An n-type well region used as an intrinsic collector region, a buried n-type semiconductor region 30 used as a graft collector region, and an n-type semiconductor region 31 for raising collector potential. The p-type base region is composed of the p-type semiconductor region 32. The n-type emitter region is composed of the n-type semiconductor region 33. An emitter extraction electrode 34 is connected to the n-type emitter region through an emitter opening (not shown). The emitter extraction electrode 34 is formed in the second layer gate material forming step of the manufacturing process, and is formed of, for example, a polycrystalline silicon film. This polycrystalline silicon film is introduced with an n-type impurity during or after its deposition to reduce the resistance value and form an n-type emitter region.

The npn-type bipolar transistor Tr
The element isolation region surrounding the periphery of is mainly composed of a p-type single crystal silicon substrate, a buried p-type semiconductor region, a p-type well region and an element isolation insulating film 14.

The basic cell 13 thus configured
For example, as shown in FIG. 6 (two-input NAND gate circuit diagram), a two-input NAND gate circuit, which is one basic circuit forming one of the macrocells 7, 8, and 10, is assigned. The delay latch circuit shown in FIG. 6 is composed of three p-channel MISFETs Qp8 to Qp10, eight n-channel MISFETs Qn8 to Qn15, and one npn-type bipolar transistor Tr. IN1, I
N2 is an input signal and OUT is an output signal.

The basic cell 13 shown in FIG. 7 shows a state in which the delay latch circuit shown in FIG. 6 is assigned. P channel MISF arranged in this basic cell 13
Each of the ETQp, the n-channel MISFETQn, and the npn-type bipolar transistor Tr is basically connected by the first layer wiring 19 shown in FIG. 7, as in the basic cell 12 described above. The basic cell 13 is shown in FIG.
Second layer power supply voltage wiring 21, second
Power is supplied from each of the second-layer reference voltage wirings 21, and the basic cells 13 are basically connected by the second-layer signal wirings 21. In the upper layer of the basic cell 13, the third layer wiring 23 and the fourth layer wiring 25 shown in FIG. 9 (plan view of relevant parts) are arranged.

The basic cell 1 configured in this way
2. As shown in FIG. 10 (plan view of relevant parts), each of the basic cells 13 is regularly arranged and spread in both the first direction and the second direction to cover the cell region shown in FIG. Constitute. Basic cells 12 and 13 shown in FIG.
11A and 11B show a state in which the first-layer wiring 21 is arranged,
(Main part plan view) shows a state in which the second layer wiring 21 is arranged,
FIG. 12 shows the third layer wiring 23 and the fourth layer wiring 25, respectively.

In the semiconductor integrated circuit device 1 adopting the standard cell system, the macro cells 7, 8 and 10 in which the high speed circuit operation is performed are shown in FIG. 10, FIG. 11 and FIG.
2 and FIG. 13 (schematic wiring diagram), the basic cell 1 is basically arranged in the first direction (gate length direction).
A basic circuit is sequentially assigned to each of 2 and 13, and the basic circuit or the macro cell 40 is assembled. The basic circuit or macro cell 40 is disposed between the basic cell 12 and the basic cell 13 that are adjacent to each other in the first direction or are separated from each other by a relatively short distance (basic cell 12).
Or between the basic cells 13) may be connected by the second-layer signal wiring 21 for assembly.

Basic cells 12 adjacent in the second direction,
Each of the 13 or basic circuits or macrocells 40 adjacent in the second direction are connected by a first layer signal wiring 19. The basic circuits or macro cells 40 adjacent to each other in the second direction, or the macro cells 40 separated by a relatively short distance in the second direction are connected by the third-layer signal wiring 23.

These basic circuits or macro cell 40
For example, the macro cell 10 and the macro cell 9 shown in FIG. 13 assembled in step 3 are connected by the third-layer signal wiring 23 directly or by the third-layer signal wiring 23 and the fourth-layer signal wiring 25.

In the semiconductor integrated circuit device 1 adopting the standard cell system configured as above, the macrocells 7, 8 and 10 in which high-speed circuit operation is performed are basically wiring layers of a four-layer wiring structure. Using all of the above, the power supply capability is improved, the wiring channel region is eliminated as much as possible, the connection length is shortened as much as possible, and the crosstalk noise is designed as much as possible. Most of the semiconductor integrated circuit devices 1 adopting the standard cell method are automatically designed by an automatic placement and routing system, but the macro cells 7, 8 and 10 in which this high speed circuit operation is performed are manually or semi-manually operated. Design by. Further, regarding the other macro cells 4, 5, 6, and 11, basically, the first layer wiring 19 and the second layer wiring 21 of the four-layer wiring structure are basically provided.
The main design is to connect and to design automatically based on the support of the automatic placement and routing system.

As described above, the semiconductor integrated circuit device 1 adopting the standard cell system of the present embodiment has the operational effects based on the following configuration.

(1) A plurality of basic cells 12 (or 13) including a plurality of MISFETs Q whose gate length direction coincides with the first direction are regularly arranged in the first direction and a second direction intersecting with the first direction. , A standard cell system in which the macro cells 10 (or 7, 8 or 40) having a predetermined function are connected by connecting the MISFETs Q in the basic cell 12 and some basic cells 12 of the plurality. In the semiconductor integrated circuit device 1 according to the present invention, each basic cell 1 in the macro cell 10 is
The MISFETs Q in 2 are connected by the first-layer signal wiring 19 arranged in a layer higher than the gate electrode 15 of the MISFET Q in the basic cell 12 and are adjacent to each other in the second direction in the macrocell 10. The arranged basic cells 12 are connected by the first-layer signal wiring 19 of the first-layer signal wiring 19 extending in the second direction, and are connected to each other in the macrocell 10 in the first direction. Between the arranged basic cells 12 is the signal wiring 1 of the first layer.
9 is arranged in a layer above 9 and is connected by a second layer signal wiring 21 extending in the first direction,
MISFETQ in each of the basic cells 12 arranged adjacent to each other in the same direction as the second-layer power supply wiring 2 in the same layer as the second-layer signal wiring 21 and extending in the same first direction.
Power is supplied from 1. With this configuration, the macro cell 1
Signal wiring of the first layer for connecting between MISFETQ in each basic cell 12 in 0 (wiring in basic cell)
The first layer signal wiring 19 of the same layer as 19 extends in the second direction (the wiring in the basic cell is used as it is as the wiring between basic cells), and between the basic cells 12 arranged adjacent to each other in the second direction. Since the signal wirings other than the first-layer signal wiring 19 are arranged in and the wiring channel region connecting the first-layer signal wiring 19 and the signal wirings other than the first-layer signal wiring 19 is not interposed, the area occupied by the macrocell 10 is Can be reduced and the integration degree of the semiconductor integrated circuit device 1 adopting the standard cell system can be improved. Further, the second layer signal wiring 21 and the second layer power supply wiring 21 are extended in the first direction, and the basic cell 12 (or MISFET in the basic cell) arranged in the first direction is used. Since the basic circuits can be sequentially arranged in the first direction, and the occurrence probability of the unused (useless) basic cell 12 (or MISFET in the basic cell) that is not used as the basic circuit in the first direction can be reduced, The occupied area of the macro cell 10 can be reduced by effectively using the basic cell 12, and the integration degree of the semiconductor integrated circuit device 1 adopting the standard cell system can be improved. Further, the wiring length of the first-layer signal wiring 19 extending in the second direction in the macro cell 10 can be shortened, and similarly, the second-layer signal wiring layer 21 extending in the first direction in the macro cell 10 can be shortened. Therefore, the operating speed of the macro cell 10 can be increased, and as a result, the operating speed of the semiconductor integrated circuit device 1 adopting the standard cell system can be increased.

(2) The second-layer power supply wiring 21 has a wiring width dimension almost equal to the gate width dimension of the MISFET Q on the upper layer of the MISFET Q in the basic cell 12 and extends in the first direction. To do. With this configuration, the second-layer power supply wiring 21 is connected to the MISF in the basic cell 12.
The first-layer signal wiring 19 is formed in another independent wiring layer with respect to the first-layer signal wiring 19 connecting between ETQs.
Without being restricted by the above, until the wiring width dimension of the second layer power supply wiring 21 is close to the gate width dimension of the MISFETQ (to be precise, there is a difference between the terminal on one end side and the terminal on the other end side of the gate electrode 15 of the MISFETQ). The size of the standard cell system can be increased by the standard cell method because the resistance value of the second layer power supply wiring 21 is reduced to improve the power supply noise absorption performance (as a result, the standby time of the circuit operation is shortened). The operating speed of the adopted semiconductor integrated circuit device 1 can be increased.

(3) MIS in the basic cell 12
The source region or drain region (p-type semiconductor region 17 or n-type semiconductor region 16) of the FETQ is a first-layer shunt of the same wiring layer as the first-layer signal wiring 19 connecting between the MISFETQ in the basic cell 12. Wiring 19
Be shunted at. With this configuration, the resistance value of the source region or the drain region of the MISFET Q in the basic cell 12 can be reduced, and the power supply speed or the signal transmission speed can be increased. Therefore, the operating speed of the macro cell 10 can be increased and the standard cell system can be used. The operating speed of the adopted semiconductor integrated circuit device 1 can be increased.

(4) The first layer signal wiring 19 is formed of a refractory metal film, and the second layer signal wiring 21 and the second layer are formed.
The first-layer power supply wiring 21 is made of either a single layer of an aluminum film or an aluminum alloy film, or one of the refractory metal film, the refractory metal alloy film, and the refractory metal nitride film as the base of these films. It is composed of the formed stack. With this configuration, the interdiffusion between Si in the drain region or the source region of the MISFET Q in the basic cell 12 and the Al in the second-layer signal wiring 21 or the second-layer power wiring 21 serves as the first intermediate layer. Since it can be reduced by the first layer signal wiring 19 or the first layer shunt wiring 19 and the connection resistance value between the drain region or the source region and the second layer signal wiring 21 or the second layer power supply wiring 21 can be reduced. The operating speed of the macro cell 10 is increased, and as a result, the operating speed of the semiconductor integrated circuit device 1 adopting the standard cell system can be increased.

(5) On the upper layer of the basic cell 12 in the macro cell 10, the third-layer signal wiring 2 which is arranged above the second-layer signal wiring 21 and extends in the second direction.
3 extends, and the fourth-layer signal wiring 25 and the fourth-layer power supply wiring 25, which are arranged above the third-layer signal wiring 23 and extend in the first direction, also extend. With this configuration, the empty layer in the upper layer of the basic cell 12 (apparently, within the occupied area of the basic cell) is used to connect the basic cells 12 or the basic circuit or the macrocell 40 to the third layer signal wiring 23 and Since the wiring channel region in which the fourth-layer signal wiring 25 is arranged and the third-layer signal wiring 23 and the fourth-layer signal wiring 25 between the basic cells 12 are arranged is excluded, the portion corresponding to this wiring channel region is eliminated. The area occupied by the macro cells 40 or between the macro cells 40, that is, the area occupied by the macro cells 10 can be reduced, and the integration degree of the semiconductor integrated circuit device 1 adopting the standard cell system can be improved. As a result, the intervals between the basic cells 12 and the macro cells 40 in the macro cell 10 are reduced, and the third layer signal wiring 23 and the fourth layer signal wiring 25 are formed.
Since any of the wiring lengths can be shortened, the signal transmission speed can be increased and the operation speed of the semiconductor integrated circuit device 1 adopting the standard cell system can be increased.

(6) The fourth layer power supply wiring 25 is arranged on the upper layer of the second layer signal wiring 21, and the fourth layer signal wiring 25 is arranged on the upper layer of the second layer power supply wiring 21. To be done. With this configuration, as compared with the case where the fourth layer signal wiring 25 is arranged on the upper layer of the second layer signal wiring 21, the separation between the second layer signal wiring 21 and the fourth layer signal wiring 25 is made. Since the size can be increased and crosstalk noise (coupling noise) between the second-layer signal wiring 21 and the fourth-layer signal wiring 25 can be reduced, the semiconductor integrated circuit device 1 adopting the standard cell method can be reduced. The reliability in circuit operation can be improved.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

The present invention is not limited to the standard cell system, but can be applied to a semiconductor integrated circuit device employing any of a custom system, a full custom system, a gate array system, and a master star rice system, that is, ASIC in general.

[0098]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (A) In the ASIC, high-speed circuit operation can be achieved. (B) High integration can be achieved in the ASIC. (C) In the ASIC, reliability in circuit operation can be improved.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit device adopting a standard cell system which is an embodiment of the present invention.

FIG. 2 is a basic circuit diagram of a macro cell.

FIG. 3 is a plan view of a main part of a basic cell.

FIG. 4 is a plan view of a main part of a basic cell.

FIG. 5 is a plan view of a main part of a basic cell.

FIG. 6 is a basic circuit diagram of a macro cell.

FIG. 7 is a plan view of a main part of a basic cell.

FIG. 8 is a plan view of a main part of a basic cell.

FIG. 9 is a plan view of a main part of a basic cell.

FIG. 10 is a plan view of a main part of a macro cell.

FIG. 11 is a plan view of a main part of a macro cell.

FIG. 12 is a plan view of a main part of a macro cell.

FIG. 13 is a connection diagram of a macro cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit device adopting standard cell system, 4-11 ... Macro cell, 12, 13 ... Basic cell, 15 ... Gate electrode, 16, 17 ... Semiconductor region, 1
9, 21, 23, 25 ... Signal wiring or power wiring,
20, 22, 24 ... Connection hole, 40 ... Basic circuit or macrocell, Q ... MISFET, Tr ... Bipolar transistor.

Claims (8)

[Claims] 1. A plurality of basic cells including a plurality of MISFETs whose gate length direction coincides with a first direction are regularly arranged in the first direction and a second direction intersecting with the first direction, and the basic cells are arranged in the basic cell. In a semiconductor integrated circuit device in which a MISFET and some basic cells among the plurality of MISFETs are connected to each other to form a macro cell having a predetermined function, the MISFETs in the respective basic cells in the macro cell are connected to each other by the basic cell. MIS in the cell
The second layer in the macrocell is connected with the first-layer signal wiring arranged in a layer higher than the gate electrode of the FET and connected.
The basic cells arranged adjacent to each other in the direction are connected by the first-layer signal wiring that extends in the second direction among the first-layer signal wirings, and are adjacent to each other in the first direction in the macro cell. The basic cells are arranged in a layer above the first-layer signal wiring and connected by a second-layer signal wiring extending in the first direction, and the first cell is also connected to the first-layer signal wiring.
In each basic cell arranged adjacent to each other in the direction
A semiconductor integrated circuit device characterized in that the ISFET is supplied with power from a second layer power supply wiring which is in the same layer as the second layer signal wiring and extends in the same first direction. 2. The second layer power supply wiring according to claim 1, wherein the second layer power supply wiring has a wiring width dimension almost equal to a gate width dimension of the MISFET in an upper layer of the MISFET in the basic cell, and has a first direction. A semiconductor integrated circuit device characterized in that it extends to. 3. The source region or the drain region of the MISFET in the basic cell according to claim 1 or 2 is in the same wiring layer as the first-layer signal wiring connecting between the MISFETs in the basic cell. A semiconductor integrated circuit device characterized by being shunted with a wiring for a first layer shunt. 4. The first-layer signal wiring according to claim 1, wherein the first-layer signal wiring is composed of a refractory metal film, and the second-layer signal wiring and the second-layer power wiring are A single layer of an aluminum film or an aluminum alloy film, or a laminated layer in which any one of the refractory metal film, the refractory metal alloy film, and the refractory metal nitride film is formed as a base of these films. A semiconductor integrated circuit device characterized by the above. 5. The basic cell upper layer in the macro cell according to claim 1, wherein the third layer is arranged above the second layer signal wiring and extends in the second direction. The fourth-layer signal wiring extends and the fourth-layer signal wiring and the fourth-layer power supply wiring, which are arranged in an upper layer than the third-layer signal wiring and extend in the first direction, also extend. Semiconductor integrated circuit device. 6. The fourth-layer power supply wiring is arranged on an upper layer of the second-layer signal wiring according to claim 5, and the fourth-layer signal wiring is arranged on an upper layer of the second-layer power supply wiring. A semiconductor integrated circuit device characterized by being arranged. 7. The semiconductor integrated circuit device according to claim 1, wherein the macro cell is one of a floating point arithmetic circuit, an integer arithmetic circuit, and a store buffer circuit. 8. The semiconductor integrated circuit device according to claim 7, wherein the macro cell is configured by a standard cell system.