JP2676801B2 - Semiconductor integrated circuit device having output buffer circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a CMOS output buffer circuit.

[Conventional technology]

Conventionally, the output buffer circuit of a CMOS semiconductor integrated circuit is always used for the interface between the internal circuit and the outside and for protection, and as shown in FIG. The I / O cell 20 including the output buffer circuit is arranged around the semiconductor chip so as to surround the internal cell 21 used to form the internal logic circuit. FIG. 3 shows an example of the circuit of the output buffer circuit. The P-channel type MOS transistors 3 and 3'are integrally connected to the N-channel type MOS transistors 4 and 4'in series between the power source 10 and the ground potential 11. The input terminal 1 is connected to each gate and the output terminal 2 is connected to each drain.
FIG. 4 shows a layout example of the output buffer circuit of FIG. In the figure, 5 is a P ⁺ diffusion layer, 6 is an N ⁺ diffusion layer, and 7 is a polysilicon gate. Reference numeral 8 is a contact hole for connecting to a polysilicon gate or a diffusion layer, and 9 and 9'are aluminum wirings. Also, 10 and 11 are connected to the power supply and GND. The P ⁺ diffusion layer 5 and the polysilicon gate 7 together form a P-channel MOS transistor, and N ^+.
N-channel MO with diffusion layer 6 and polysilicon gate 7
An S transistor is formed, and these drains are commonly connected to the output terminal 2 by an aluminum wiring 9 '.

[Problems to be solved by the invention]

Generally, the output buffer circuit has a maximum number of 10
Since a peak current of about 100mA flows from mA, each of them is used to prevent electromigration of aluminum wiring.
The wiring between the drains of the MOS transistors and the wiring 9'to the output terminal 2 must be made sufficiently thick, and usually the wiring thickness of about 30 to 60 .mu.m is required. Since the thickness of the aluminum wiring 9'has to be made thicker as the operating current becomes larger, it becomes a hindrance in the chip layout, and there is a drawback that the chip area is increased and the degree of freedom of layout is lowered.

Also, when such thick wiring is used, aluminum projections called hillocks are likely to occur in aluminum wiring. Therefore, in products with two or more layers, which is the current mainstream, hillocks cause a short circuit between multilayer wirings. However, there are drawbacks such as a decrease in yield and a decrease in reliability.

[Means for solving the problem]

In order to solve the drawbacks described above, the present invention has a structure in which the metal wiring connecting the drains of the P-channel and N-channel type MOS transistors forming the output buffer circuit is divided into a plurality of wirings. Have

Generally, the wiring life of aluminum wiring due to electromigration becomes minimum at a certain wiring width as shown in FIG. 6, and conversely the wiring life becomes longer when the wiring width becomes thin to some extent. However, if the wiring width becomes too thin (2 μm or less), a problem of stress migration occurs, and the reliability decreases again. In addition, the occurrence of hillocks in multi-layer wiring tends to increase in proportion to the area of the wiring. Therefore, arranging a large number of narrow-width wirings in parallel improves the reliability and yield compared to a thick-width wiring. To do.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, 1 and 2 are respective input and output terminals, 3 and 3'are P-channel MOS transistors, 4 and 4'are N-channel MOS transistors, and 5 and 6 are P ⁺ and N ⁺ diffusions. The layer, 7 is a gate electrode of polysilicon, and 8 is a contact hole.
Reference numeral 9'denotes an aluminum wiring which connects the drains of the P-channel type MOS transistors 3 and 3'and the drains of the N-channel type MOS transistors 4 and 4'to each other and leads to the bonding pad of the output terminal 2. .

Since the aluminum wiring 9'is connected not by a single thick wiring but by a plurality of thin wirings, the overall wiring width is narrower than that of the conventional example shown in FIG. In this way, the total wiring life will be longer than before because each wire is thin. Also, one, one
Since the wiring width of the book is narrow, it is possible to suppress the occurrence of hillocks. In addition, electromigration is
It is particularly likely to occur when direct currents, that is, currents flow in the same direction, and are less likely to occur when alternating currents, that is, currents flow in alternate directions. Therefore, it is the wiring between the drains of the P-channel type MOS transistors 3, 3'and the N-channel type MOS transistors 4, 4 'that electromigration is most likely to occur in the circuit of FIG. The wiring in which the thin wirings are arranged in parallel can be extended not only between the P-channel type MOS transistors 3 and 3'and the N-channel type MOS transistors 4 and 4 ', but also to the output terminal (bonding pad) 2. The width of the thin wiring 9 ′ is optimally around 10 μm in consideration of the life.

FIG. 2 shows another embodiment of the present invention. In this embodiment, only the drains of the P-channel type MOS transistors 3 and 3'and the drains of the N-channel type MOS transistors 4 and 4'are connected by aluminum wiring 9 "in which thin wirings are arranged in parallel. The contact holes 8 in the drain region are connected by a wide aluminum wiring, which makes it possible to more evenly equalize the currents flowing in the respective thin wirings, thereby achieving a more uniform wiring life. Further, since each drain region is covered with the aluminum wiring 9 ″, the contact hole 8 and the adjacent contact hole 8 can be arranged side by side with each other, so that the equivalent diffusion layer resistance and contact resistance can be reduced. Therefore, there is an advantage that the output current and the like are improved.

Further, since each of these thin wirings has the same potential, the yield reliability does not decrease even if the distance between the thin wirings is reduced. Therefore, the wiring area is smaller than that of the layout of FIG. It is possible to

〔The invention's effect〕

As described above, according to the present invention, by finely dividing the wiring, it is possible to realize an output buffer having an improved wiring life and improved reliability.

[Brief description of the drawings]

FIG. 1 is a plane pattern diagram showing a layout example of an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a plane pattern diagram showing a layout example of an output buffer circuit according to another embodiment of the present invention, and FIG. Is an equivalent circuit diagram of an output buffer circuit, FIG. 4 is a plan pattern diagram showing a layout example of a conventional output buffer circuit, FIG. 5 is a partial plan schematic diagram showing a chip layout example, and FIG. 6 is a wiring width. It is a graph which shows the relationship between wiring life. 1 ... Input terminal, 2 ... Output terminal, 3 ... P-channel type MOS transistor, 4 ... N-channel type MOS transistor, 5 ... P ⁺ diffusion layer, 6 ... N ⁺ diffusion layer, 7 ... Polysilicon gate , 8 ... Contact hole, 9,9 ', 9 "... Aluminum wiring, 10 ... Power supply, 11 ... Grounding, 20 ... I / O
Cell, 21 …… Internal cell.

Claims (1)

(57) [Claims] 1. A first conductivity type MOS transistor and a second conductivity type M.
In a semiconductor integrated circuit device having an output buffer circuit configured by connecting an OS transistor in series between power supply lines, a distance between the drain of the first conductivity type MOS transistor and the drain of the second conductivity type MOS transistor is 15 μm.
A semiconductor integrated circuit device having an output buffer circuit, which is connected by at least two or more metal wirings arranged in parallel with a width of m or less.