JPH0245975A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a noise from being left over on a signal for a wiring for signals effectively by extending a shielding supply wiring along the wiring for signals on both side of the wiring for signals. CONSTITUTION:Power supply wirings 7A and 7B for shielding are located along a wiring 7C for input signals. The wiring 7C, which is formed in a wiring formation process for the first layer, is extended in the direction of a line in a wiring formation area 6. The wiring 7A is connected to a power supply voltage wiring VCC of a main power supply wiring 8 and is extended along one side of the wiring 7C. The wirings 7C, 7A and 7B are formed by the same conductive layer (the wiring formation process of the first layer). The wirings 7A and 7B are separated from the wiring 7C by the minimum distance required for wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device that employs a gate array method.

[Conventional technology]

A semiconductor integrated circuit device employing a gate array method can configure a desired logic circuit by connecting regularly arranged basic cells and between basic cells using multiple layers of connection wiring. Furthermore, a semiconductor integrated circuit device employing a gate array method can configure various logic circuits other than those described above simply by changing the connection pattern of the connection wiring. This type of semiconductor integrated circuit device is characterized by the ability to construct a wide variety of products in a short period of time.

A semiconductor integrated circuit device employing a gate array system, which is currently being developed by the present inventor, has a plurality of input/output buffer circuits arranged in its peripheral portion. A plurality of basic cells are arranged in a matrix in a region surrounded by the input/output buffer circuit. The basic cell is formed of a plurality of complementary MISFETs (CMO8), and a plurality of basic cells are arranged in the column direction to form a basic cell column. A wiring formation region (wiring channel region) is provided between these basic cell columns arranged in the row direction.

In a semiconductor integrated circuit device employing this gate array method, the connection wiring is formed of two layers of aluminum alloy wiring. The first-layer connection wiring is formed as a wiring that connects basic cells that extend in the column direction in the basic cell internal wiring and the wiring formation area. The second layer connection wiring is formed as a wiring that connects basic cells extending in the row direction in the wiring formation region. This connection wiring is usually done using an automatic wiring system (DA: Desig) that uses a computer.
nA auto[l1ation).

The semiconductor integrated circuit device employing the gate array method is described, for example, in Nikkei McGraw-Hill, Nikkei Microdevices, September 1986 issue, pages 65 to 72.

[Problem to be solved by the invention]

The present inventor discovered that the following problem occurred during the development of the gate array type semiconductor integrated circuit device.

In a semiconductor integrated circuit device employing a gate array method, the pattern of signal wiring varies depending on the logic circuit to be incorporated. For example, the input signal wiring connecting the input buffer circuit and the first-stage logic circuit may extend close to the output signal wiring.

In addition, the input signal wiring may intersect with the output signal wiring. Each of these input signal wiring and output signal wiring extends independently. In such a case, noise is induced by the output signal of the output signal wiring and is added to the input signal of the input signal wiring.

This causes the first stage logic circuit to malfunction.

The electrical reliability of the gate array type semiconductor integrated circuit device decreases.

An object of the present invention is to provide a technique that can reduce malfunctions of logic circuits and improve electrical reliability in a semiconductor integrated circuit device that employs a gate array method.

Another object of the present invention is to reduce noise on signals of the signal wiring, regardless of the layout of the signal wiring and other signal wiring, in a semiconductor integrated circuit device adopting the gate array method. The goal is to provide technology that enables

Another object of the present invention is to provide a technique capable of efficiently reducing noise added to the signal of the signal wiring.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a gate array type semiconductor integrated circuit device, shielding power supply wiring is extended along both sides of the signal wiring along the signal wiring.

[For production]

According to the above-mentioned means, since the signal shadow* (noise) of other signal wirings extending around the signal wiring is shielded by the shielding power supply wiring, noise does not appear on the signal of the signal wiring. It is possible to prevent malfunctions of logic circuits. As a result, the electrical reliability of a semiconductor integrated circuit device employing the gate array method can be improved.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device employing a gate array method.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 2 (chip layout diagram) shows a basic schematic configuration of a semiconductor integrated circuit device that employs a gate array system, which is an embodiment of the present invention.

As shown in FIG. 2, a semiconductor integrated circuit device 1 employing a gate array method is composed of a chip (for example, a single-crystal silicon substrate) having a rectangular plane. Semiconductor integrated circuit device
has multiple external terminals (
(pounding pad) 2 is placed. Inside the external terminals 2, a plurality of human output buffer circuits 3 are arranged along the arrangement of the external terminals 2.

The semiconductor integrated circuit device 1 of this embodiment has a logic circuit formed by two layers of connection wiring, and the external terminals 2 are connected to the connection wiring formed in the second layer (or first layer) wiring formation process. They are formed in the same manufacturing process.

The connection wiring is formed of aluminum wiring or aluminum alloy wiring. The aluminum alloy wiring is made by adding Cu or Si to aluminum. Cu can reduce electromigration or stress migration.

Si can reduce the alloy spike phenomenon at the connection portion with Si (semiconductor region).

As shown in FIG. 2 and FIG. 1 (enlarged plan view of main parts), the crowd cover sofa circuit 3 has one (or a plurality of) external terminals 2.
is placed in a position corresponding to Although the structure of the human output buffer circuit 3 is not shown in detail, it is composed of input buffer circuit cells and output buffer circuit cells.

The cell for the input cover sofa circuit is, for example, a complementary MISFET (
0MO8). This input buffer circuit cell can form an input buffer circuit by connecting each semiconductor element with a connection wiring formed in a wiring formation process.

In addition, the input buffer circuit cell has a protective resistance element and a clamp MI5F so that an electrostatic damage prevention circuit can be configured.
ET is in place. The output buffer circuit cells are composed of complementary MISFETs or bipolar transistors. This output buffer circuit cell can constitute an output buffer circuit by connecting each semiconductor element with a connection wiring formed in a wiring formation process.

The connections between the semiconductor elements of the input buffer circuit cell and the output buffer circuit cell are mainly made using connection wiring formed in the first layer wiring formation process. In other words, the human output buffer circuit 3 can form an input buffer circuit or an output buffer circuit using the connection wiring formed in the first layer wiring formation process.

A main power supply wiring (main power supply wiring) 8 extends above the input/output buffer circuit 3 . The main power supply wiring 8 is the second
It is formed in the wiring formation process for each layer. Main power wiring 8
are the power supply voltage wiring Vcc, for example, the circuit operating voltage 5 [V] and the reference voltage wiring V. For example, the ground potential of the circuit is 0 [V]. Although not limited thereto, the power supply voltage wiring vcc extends parallel to the outer periphery of the reference voltage wiring V□.

Semiconductor integrated circuit device 1 surrounded by human output buffer 7 circuit 3
The central part is a logic circuit section forming a logic circuit. In this logic circuit section, as shown in FIG. 2, a plurality of basic cells 4 are regularly arranged in rows and columns. A plurality of basic cells 4 arranged in the column direction form a basic cell column 5.

A plurality of basic cell columns 5 are arranged in the row direction at constant intervals of f. The space between the basic cell rows 5 is used as a wiring formation region (wiring channel region) 6 in which connection wiring connecting between the basic cells 4 (between logic circuits) is formed.

The basic cell 4 is 4 as shown in FIG. 3 (main part plan view).
It is composed of one p-channel MISFETQp and four n-channel MISFETQn.

In other words, the basic cell 4 is a complementary MISFET (0MO8
). p channel MI S FETQp
is formed on the main surface of an n-type well region (not shown) in a region surrounded by field insulating film 4A.

The p-channel MI 5FETQp mainly consists of an n-type well region (channel formation region), a gate insulating film, and a gate electrode 4.
B, a pair of p+ type semiconductor regions 4C which are a source region and a drain region. Similarly, n-channel M
ISFETQn is formed on the main surface of a p-type well region (not shown) in a region surrounded by field insulating film 4A. The n-channel MISFETQn is mainly
p-type well region (channel formation region), gate insulating film,
It is composed of a gate electrode 4B and a pair of square-shaped semiconductor regions 4D which are a source region and a drain region. The gate electrode 4B is formed of, for example, a single layer of a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or a composite film thereof.

The four MISFETs Qp of the basic cell 4 integrally constitute one semiconductor region 4C adjacent to each other in the gate length direction, and are connected in series.

Similarly, the four M I S F E T Q n integrally constitute one semiconductor region 4D adjacent to each other in the gate length direction, and are connected in series. Namely.

This basic cell 4 can constitute a four-man power NAND gate circuit. Note that the basic cell 4 is not limited to the aforementioned four-manpower NAND gate circuit, but may be configured to form a two-manpower NAND gate circuit or a three-manpower NAND gate circuit.

The respective electrodes (terminals) of the MISFETs Qp and Qn of this basic cell 4 are connected mainly by connection wiring formed in the first layer wiring formation process.

The wiring within the basic cell 4 constitutes a predetermined logic circuit or a part thereof. Further, on the basic cell 4, a power supply wiring 7 extends in the column direction as shown in a simplified manner by a solid line in FIG. This power supply wiring 7 is formed in the first layer wiring formation process.

The part of the power supply wiring 7 extending over the p-channel MISFET Qp is the power supply voltage wiring Vcc. Power supply wiring 7.
Of these, the one extending over the n-channel M I S F E T Q n is the reference voltage line Vss. The power supply voltage wiring Vcc of the power supply wiring 7 is connected to the power supply voltage wiring Vcc of the main power supply wiring 8 either directly or indirectly through an auxiliary power wiring (not shown).

Similarly, the reference voltage line Vss of the power supply line 7 is directly or indirectly connected to the reference voltage line Vss of the main power supply line 8.

Between the power supply voltage wiring Vcc and the reference voltage wiring Vss of the power supply wiring 7 extending on the basic cell 4, there is a first layer of several to several dozen water lines in the minimum wiring separation dimension (minimum pitch between wirings). The connection wiring formed in the second wiring formation step is configured to extend in the column direction. The semiconductor integrated circuit device 1 employing the gate array method of this embodiment is configured so that about 6 to 10 connection wires can be extended.

In the wiring formation region 6 between the basic cell rows 5 shown in FIG. 2, connection wirings are mainly formed to connect between the basic cells 4 or between logic circuits formed by the basic cells 4. There is. That is, similar to the wiring within the basic cell 4, the connection wiring connects each electrode of each MISFET Qp, Qn of the basic cell 4 to each electrode of another basic cell 4. The wiring formation region 6 includes connection wirings extending in the column direction formed in the first layer wiring formation process and connection wirings extending in the row direction formed in the second layer wiring formation process. is formed. The connection wires formed in each of the first layer wiring forming step and the second layer wiring forming step are automatically arranged by an automatic wiring system (DA) using a computer. Additionally, connection wires that cannot be placed automatically using the automatic wiring system are placed manually.

Semiconductor integrated circuit device 1 adopting this gate array method
As shown in FIG. 1, shielding power supply wiring extends along both sides of at least some of the signal wiring. In the semiconductor integrated circuit device 1 shown in FIG. 1, a human output buffer circuit (input buffer circuit) 3 and a first stage logic circuit (inverter circuit) formed of basic cells 4 are connected by an input signal wiring 7c. Shielding power supply wirings 7A and 7B are arranged along the input signal wiring 7C. The input signal wiring 7C is formed in the first layer wiring formation process and extends in the wiring formation region 6 in the column direction.

The shielding power supply wiring 7A is connected to the power supply voltage wiring Vcc of the main power supply wiring 8, and extends along one side of the input signal wiring 7C. The shielding power supply wiring 7B is connected to the base voltage wiring Vss of the main power supply wiring 8, and extends along the other side of the input signal wiring 7C and the shielding power supply wiring 7A. , 7B are formed using the same conductive layer (first layer wiring formation step). Each of the shielding power supply wirings 7A and 7B is arranged at a position separated from the input signal wiring 7C by a minimum wiring separation dimension (minimum wiring pitch).

Each of the shielding power supply wirings 7A and 7B is incorporated into computer software so that they can be automatically arranged by an automatic wiring system (DA) using a computer. In other words, the automatic wiring system uses input signal wiring 7C.
When a layout pattern (though not limited to this wiring) is determined, shielding power supply wirings 7A and 7B are automatically placed along both sides of the human signal wiring 7C. .

The input signal wiring 7C intersects (or may extend to a position close to) the output signal wirings 7D, 8A, and 7E. Output signal wirings 7D, 8A, and 7E connect the human output buffer circuit (output buffer circuit) 3 to a final stage logic circuit, such as an inverter circuit. The output signal wirings 7D and 7E are formed in the first layer wiring formation process. The output signal wiring 8A is formed in the second layer wiring formation process. Output signal wiring? D.

Connections between each of 7E and βA are made through connection holes (indicated by * in FIG. 1), which are not shown.

The input signal wiring 7C does not necessarily need to have the shielding power supply wirings 7A and 7B on both sides of its entire extended area, and at least the part where it intersects with the output signal wiring 8A (
or a portion where other output signal wiring is close).

Further, each of the shielding power supply wirings 7A and 7B may be arranged not only on the input signal wiring 7C but also on both sides of the output signal wirings 7D, 8A and 7E. In addition, the shielding power supply wiring 7
Although each of A and 7B is formed in the first layer wiring forming process, the shielding power supply wiring may be formed in the second layer wiring forming process.

Further, the input signal wiring 7C has a power supply voltage wiring Vcc and a reference voltage wiring Vss arranged on both sides.
may be placed.

Further, shielding power supply wiring may be arranged on both sides of input signal wiring and output signal wiring that connect between basic cells or between logic circuits.

In this way, in the semiconductor integrated circuit device 1 adopting the gate array method, the shielding power supply wirings 7A and 7B are extended along the input signal wiring 7C on both sides of the input signal wiring 7C, so that the input signal Since the influence (noise) of the signals of the other output signal wirings 7D, 8A and 7E extending around the input signal wiring 7C is shielded by the shielding power supply wirings 7A and 7B, the signal of the input signal wiring 7C is It is possible to reduce noise and prevent malfunction of logic circuits. As a result, the electrical reliability of the semiconductor integrated circuit device 1 employing the gate array method can be improved.

In addition, the automatic wiring system has software built in so that the shielding power supply wirings 7A and 7B are always placed on both sides of the input signal wiring 7C, so even if the connection pattern of the input signal wiring 7C is changed. Shielding power supply wirings 7A and 7B can be arranged on both sides of the constant input signal wiring 7C.

In addition, since each of the shielding power supply wirings 7A and 7B is arranged at a position separated from the input signal wiring 7C by the minimum wiring separation dimension, the shielding power supply wirings 7A and 7B are arranged in a position that is separated from the input signal wiring 7C by the minimum wiring distance, so that the shielding power supply wirings 7A and 7B can be connected to other signal wirings most efficiently and to the maximum extent possible. It is possible to reduce the noise from

Also, power wiring for shielding? Since each of A and 7B can be formed of the same conductive layer as the input signal wiring 7C, they can be used as shielding power supply wiring. There is no need to add conductive layers to form each of A and 7B in the manufacturing process. In other words, the semiconductor integrated circuit device 1 employing the gate array method requires a step corresponding to the step of forming the shielding power supply wirings 7A and 7B.
The number of manufacturing steps can be reduced.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is formed with three or more wiring layers for connection. It can be applied to a semiconductor integrated circuit device that employs a gate array method.

Further, the present invention can be applied to a semiconductor integrated circuit device that employs a gate array method in which basic cells are spread over the entire surface without providing a wiring formation region between basic cell columns. In this laying method, basic cells or basic cell rows between logic circuits are used as wiring formation regions.

Furthermore, the present invention may be applied to a semiconductor integrated circuit device that employs a gate array method in which basic cells are constructed of bipolar transistors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device that employs a gate array method, malfunctions of logic circuits can be reduced, so electrical reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is an enlarged plan view of essential parts showing the basic schematic configuration of a semiconductor integrated circuit device employing a gate array method, which is an embodiment of the present invention; FIG. 2 is a chip layout diagram of the semiconductor integrated circuit device; FIG. 3 is a plan view of essential parts of the basic cell of the semiconductor integrated circuit device. In the figure, 1... Semiconductor integrated circuit device, 4... Basic cell, 5... Basic cell column, 6... Wiring formation region, 7, 8
・Power wiring, 7A, 7B...Shielding power wiring, 7c,
7D, 7E, 8A...Signal wiring, Qp, Qn-MI
It is an S FET.

Claims (1)

[Scope of Claims] 1. In a gate array type semiconductor integrated circuit device in which a predetermined logic circuit is formed by changing the wiring pattern within a basic cell and between basic cells, both sides of a signal wiring in the wiring pattern A gate array type semiconductor integrated circuit device, characterized in that a shielding power supply wiring is extended along the signal wiring. 2. The gate array type semiconductor integrated circuit according to claim 1, wherein the shielding power supply wiring extends at a position separated from the signal wiring by a minimum wiring interval. Device. 3. The gate array according to claim 1 or 2, wherein the signal wiring and the shielding power supply wiring extending along both sides thereof are formed of the same conductive layer. type semiconductor integrated circuit device.