JPH0245957A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of freedom in connection wiring and decrease alternative wiring and then, improve a packaging rate of a circuit by forming diagnostic signal wiring by using a conduction layer that is different from a connection wiring layer for connecting between electrodes of standard cells. CONSTITUTION:As to a semiconductor integrated circuit device 1 having self- diagnostic functions, diagnostic wiring regions 4b are disposed in wiring formation regions 6. The above wiring regions 4b form a part on diagnostic signal wiring regions 11 and 12 connecting between a logic circuit which is formed and diagnosed in the device 1 and an external tester. The wiring regions 4b extend in the direction of rows so that they may pass over the wiring formation regions 6 and a plurality of them are disposed in the direction of columns. The first and second connection wiring regions 7 and 8 extend on the upper layer of wiring 4b. The wiring regions 7 are formed in standand cells and further, are formed so that each region 6 may extend in the direction of columns. Such a configuration improves the degree of freedom of the wiring regions 7 and 8 and decreases alternative wiring and further, improves a packaging rate of a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device that employs a gate array method with a self-diagnosis function. It is something.

[Conventional technology]

A semiconductor integrated circuit device employing a gate array method can configure a desired logic circuit by connecting regularly arranged basic cells and between basic cells using multiple layers of connection wiring. Furthermore, a semiconductor integrated circuit device employing a gate array method can configure various logic circuits other than those described above simply by changing the connection pattern of the connection wiring. This type of semiconductor integrated circuit device is characterized by the ability to construct a wide variety of products in a short period of time.

The semiconductor integrated circuit device which adopts the gate array method currently being developed by the present inventor has a basic cell as a plurality of complementary MI SFETs.
(CMO8). Further, the connection wiring is formed of two layers of aluminum alloy wiring. Among these, the wiring for connection between basic cells is a wiring formation area (wiring channel formation area) between a basic cell column in which a plurality of basic cells are arranged in the column direction and another basic cell column adjacent in the row direction.
It has been extended to The semiconductor integrated circuit device that employs this gate array method under development is equipped with a self-diagnosis function.

The self-diagnosis function is a function for indirectly diagnosing (testing) the characteristics of a predetermined logic circuit formed by connecting with the connection wiring. This diagnosis is performed by an external tester.

A semiconductor integrated circuit device employing this gate array system has a diagnostic signal wiring that connects a predetermined logic circuit formed inside the device and to be diagnosed to the external tester. The diagnostic signal wiring is formed of the same conductive layer as the connection wiring.

This connection wiring is done using an automatic wiring system (DA: Design Automation) that uses a computer.
Since the wiring is automatically connected in step n), the diagnostic signal wiring is similarly formed automatically. In other words, the connection wiring is automatically arranged by the automatic wiring system, and the diagnostic signal wiring is automatically arranged by the automatic wiring system along the logic circuit to be diagnosed so as not to short-circuit with the connection wiring. . The diagnostic signal wiring pattern is determined by inputting connection wiring pattern data for forming a logic circuit into pattern data stored in advance in a computer program and matching the two.

Regarding gate array type semiconductor integrated circuit devices equipped with a self-diagnosis function, for example, Japanese Patent Laid-Open No. 63-0166
It is described in Publication No. 36.

[Problem to be solved by the invention]

In the semiconductor integrated circuit device that employs the gate array method that the present inventor is developing, the connection wiring and the diagnostic signal wiring are formed of the same conductive layer, so the diagnostic signal wiring and the connection wiring are free. degree is restricted. For this reason, the connection wiring often bypasses the diagnostic signal wiring, so the gate array type semiconductor integrated circuit device reduces the number of logic circuits per unit area (the mounting rate decreases or the degree of integration decreases). There was a problem with this.

An object of the present invention is to provide a technique that can improve the circuit mounting rate (integration degree) in a semiconductor integrated circuit device that employs a gate array system and has a self-diagnosis function.

Another object of the present invention is to achieve the above object by independently and automatically arranging connection wiring for the diagnostic signal wiring of the self-diagnosis function and improving the degree of freedom of the connection wiring. Our goal is to provide technology that makes it possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device employing a gate array system with a self-diagnosis function, at least a part of a diagnostic signal wiring connecting an external tester and a predetermined circuit to be diagnosed is formed of the same conductive layer as the electrode of a basic cell. . That is, a part of one diagnostic signal wiring is formed of a conductive layer different from the wiring for connecting within the basic cell and between the basic cells. As part of this diagnostic signal wiring, the MISFE that constitutes the basic cell
The gate electrode, source region, or drain region of T is formed.

[For production]

According to the above-described means, the diagnostic signal wiring is formed of a different conductive layer from the connection wiring that connects between the electrodes of the basic cell, and the arrangement of the connection wiring is independent of the diagnostic signal wiring. Since the flexibility of connection wiring can be increased, detour wiring can be reduced and the circuit mounting rate can be improved.

Further, since the number of detours of the connection wiring can be reduced, signal delay can be reduced and operation speed can be increased.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device that employs a gate array method.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Embodiment 2) FIG. 2 (chip layout diagram) shows a basic schematic configuration of a semiconductor integrated circuit device that employs a gate array system with a self-diagnosis function, which is Embodiment 2 of the present invention.

As shown in FIG. 2, a semiconductor integrated circuit bag w1 employing a gate array method is composed of chips (for example, a single crystal silicon substrate) having a rectangular plane. Semiconductor integrated circuit device 1
has multiple external terminals (
(pounding pad) 2 is placed. A plurality of input/output buffer circuits 3 are arranged inside the external terminals 2 along the arrangement of the external terminals 2.

The semiconductor integrated circuit device 1 of this embodiment has a logic circuit formed by two layers of connection wiring, and the external terminals 2 are connected to the connection wiring formed in the second layer (or first layer) wiring formation process. They are formed in the same manufacturing process.

The connection wiring is formed of aluminum wiring or aluminum alloy wiring (to which Cu or Si is added).

The input/output buffer circuit 3 has one (or more) external terminals 2
is placed in a position corresponding to Although the structure of the input/output buffer circuit 3 is not shown in detail, it is composed of cells for an input buffer circuit and cells for an output buffer circuit 7.

The input buffer circuit cell is, for example, a complementary MISFET (
C, MOS). This cell for a human-powered buffer circuit can form an input buffer circuit by connecting each semiconductor element with a connection wiring formed in a wiring formation process.

In addition, the cells for the input buffer circuit are equipped with a protective resistance element and a MISFE for clamping so that an electrostatic damage prevention circuit can be constructed.
T is placed. Output buffer circuit cells are complementary type M
It is composed of an ISFET or a bipolar transistor. This output buffer circuit cell can constitute an output buffer circuit by connecting each semiconductor element with a connection wiring formed in a wiring formation process.

Connections between the semiconductor elements of the input buffer circuit cell and the output buffer circuit cell are mainly made using connection wiring formed in the first layer wiring formation process. Although not shown, the power supply wiring formed in the second layer wiring formation process is configured to extend above the human output buffer circuit 3. The power supply wiring is composed of a power supply voltage wiring Vcc, for example, a circuit operating voltage of 5 [V], and a reference voltage wiring Vg1, for example, a circuit ground potential of 0 [V].

Semiconductor integrated circuit device 1 surrounded by input/output buffer circuit 3
The central part is a logic circuit section forming a logic circuit. In this logic circuit section, a plurality of basic cells 4 are regularly arranged in a matrix. A plurality of basic cells 4 arranged in the column direction form a basic cell column 5. A plurality of basic cell columns 5 are arranged in the row direction at predetermined intervals. The area between basic cell rows 5 is a wiring formation area (wiring channel formation area) where connection wiring is formed to connect between basic cells 4 (between logic circuits).
It is used as 6.

The basic cell 4 is 3 as shown in FIG. 3 (main part plan view).
It consists of one p-channel MISFETQP and four n-channel MISFETQn.

In other words, the basic cell 4 is a complementary MISFET (0MO8
). The p-channel MISFET Qp is formed on the main surface of an n-type well region (not shown) in a region surrounded by a field insulating film 4A. The p-channel MISFET Qp mainly consists of an n-type well region (
channel formation region), gate insulating film, gate electrode 4B,
It is composed of a pair of p' type semiconductor regions 4C which are a source region and a drain region. Similarly, n-channel MIS
FET Q n is formed on the main surface of a p-type well region (not shown) in a region surrounded by field insulating film 4A. The n-channel MISFETQn is mainly
p-type well region (channel formation region), gate insulating film,
It is composed of a gate electrode 4B and a pair of n-type half-grave regions 4D which are a source region and a drain region.

The three MISFETs Qp of the basic cell 4 integrally constitute one semiconductor region 4C adjacent to each other in the gate length direction, and are connected in series.

Similarly, three of the four MISFETQn integrally constitute one semiconductor region 4D adjacent to each other in the gate length direction, and are connected in series.

In other words, this basic cell 4 can constitute a three-man power NAND gate circuit. In addition, the basic cell 4 is
The present invention is not limited to the three-man powered NAND gate circuit described above, but may be configured to form a two-man powered NAND gate circuit or a four-man powered NAND gate circuit.

The interior of the basic cell 4 is connected mainly by connection wiring formed in the first layer wiring formation process, and the basic cell 4 is configured to constitute a predetermined logic circuit or a part thereof. Specifically, the connection wiring is provided between each electrode of the basic cell 4, that is, between the gate electrodes 4B, between the gate electrode 4B and the semiconductor region 4C or 4D, between the semiconductor regions 40, and between the semiconductor regions 4
D or between semiconductor regions 4C and 4D. Further, on the basic cell 4, a power supply wiring (not shown) formed in the first layer wiring forming step is configured to extend in the column direction (gate length direction). The power supply wiring is a power supply voltage wiring (7: Vcc) extending over the p-channel MISFET Q p and the n-channel MISF
It is composed of a reference voltage wiring (7: Vss) extending over ETQn.

The wiring formation region 6 between the basic cell rows 5 shown in FIG.
Wiring for connection is mainly formed to connect between the basic cells 4, between logic circuits formed by the basic cells 4, etc. That is, similar to the wiring within the basic cell 4, the connection wiring connects the electrode of the basic cell 4 and the electrode of another basic cell 4. In the wiring formation region 6, connection wirings extending in the column direction formed in the first layer wiring formation step,
A connection wiring extending in the row direction formed in the second layer wiring forming step is formed. The connection wiring formed in each of the first layer wiring formation process and the second layer wiring formation process is performed using an automatic wiring system (DA) using a computer.
) are automatically placed.

Semiconductor integrated circuit device 1 adopting this gate array method
has a self-diagnosis function. This self-diagnosis function is for diagnosing (testing) the characteristics of a logic circuit formed by providing a predetermined pattern of connection wiring within and between the basic cells 4 of the semiconductor integrated circuit device 1. This diagnosis is performed by an external tester (not shown) placed outside the semiconductor integrated circuit device 1 (or a built-in internal tester).

This diagnosis is not a direct method in which a regular input signal is input to a logic circuit and a regular output signal is detected, but a predetermined output signal can be detected by inputting a diagnostic signal to the logic circuit or a part thereof. It is an indirect method that determines whether or not.

This semiconductor integrated circuit device 1 having a self-diagnosis function has a first
As shown in the figure (schematic enlarged plan view of the main part), the wiring formation area 6
Diagnostic wiring 4b is arranged at.

The diagnostic wiring 4b forms at least a part of the diagnostic signal wiring (11, 12) that connects the logic circuit formed in the semiconductor integrated circuit device 1 to be diagnosed and an external tester. The diagnostic wiring 4b extends in the row direction so as to cross the wiring formation region 6, and a plurality of diagnostic wirings 4b are arranged in the column direction. This diagnostic wiring 4b connects each electrode of the basic cell 4, that is, p-channel MISFETQp, n-channel MISFET
It is formed of the same conductive layer (same manufacturing process) as each gate electrode 4B of ETQn. The above-described first-layer connection wiring 7 and second-layer connection wiring 8 extend above the diagnostic wiring 4b. As described above, the connection wiring 7 is formed to extend in the column direction within the basic cell 4 and the wiring formation region 6. Basic cell 4 of connection wiring 7
The connection wiring 7 extending above in the column direction is a power supply wiring (power supply voltage wiring Vcc and reference voltage wiring Vss).The connection wiring 8 is formed to extend in the row direction in the wiring formation region 6. There is. The diagnostic wiring 4b, like the connection wiring 7.8, is arranged by an automatic wiring system using a computer. Therefore, the diagnostic wiring 4b is appropriately arranged within the wiring coordinates used in the computer, taking into consideration the mounting rate of logic circuits and the like. As mentioned above, the diagnostic wiring 4b is formed of the gate material which is the same conductive layer as the gate electrode 4B, so it has a higher resistance value than the connection wirings 7 and 8. However, when diagnosing a logic circuit, Diagnostic wiring 4 does not require that much operating speed.
There are no problems with forming b with the gate material.

When the logic circuit Logic shown in FIG. 4 (logic circuit diagram) is formed by providing predetermined connection wirings 7 and 8 within the basic cell 4 and between the basic cells 4, the logic circuit shown in FIG. Signal wires 9 and 10 connected to the circuit Logic are formed by connection wires 7 (or and 8). This logic circuit Logic is a static type D flip-flop circuit, and is formed by combining an inverter circuit, a transmission circuit, and a NOR circuit. D of the signal wiring 9 is an input signal of the logic circuit Logic, CL and GK are input clock signals, and PR is a pre-reset signal. Q of signal wiring 10.

Q is an output signal of the logic circuit Logic. φ and φ are internal clock signals generated by input clock signal GK.

A self-diagnosis circuit is incorporated in the logic circuit Logic as shown in FIG. 1 and FIG.
It is configured to be able to diagnose whether or not GIC or a part thereof is operating normally. The self-diagnosis circuit is formed along the logic circuit Logic using the semiconductor elements of the basic cells 4 around it. Diagnostic signal wirings 11 and 12 are connected to this self-diagnosis circuit. C1 and C2 of the diagnostic signal wiring 11 are diagnostic manual clock signals, W is a diagnostic write signal, and R is a diagnostic read signal. TD of the 5 diagnostic signal wiring 12 is a diagnostic output signal.

Each of the diagnostic signal wirings 11 and 12 is configured to connect the self-diagnosis circuit (logic circuit) and an external tester by combining the diagnostic wiring 4b and the connection wiring 7 or the connection wiring 8. ing. That is, each of the diagnostic signal wirings 11 and 12 uses the diagnostic wiring 4b of a conductive layer different from that of the connection wirings 7 and 8 in at least a portion thereof.

As described above, in the semiconductor integrated circuit device 1 which employs the gate array method having a self-diagnosis function.

At least a part of each of the diagnostic signal wirings 11 and 12 connecting an external tester and a predetermined logic circuit to be diagnosed is a diagnostic wire formed of the same conductive layer as the electrode (gate electrode 4B) of the basic cell 4. By configuring the wiring 4b, each of the diagnostic signal wiring 11 and 12 is connected to the connection wiring 7.
．． 8, each of the connection wirings 7 and 8 is arranged independently with respect to each of the diagnostic signal wirings 11 and 12, and each of the connection wirings 7 and 8 is free. (The diagnostic wiring 4b and the connection wiring 7.8 can freely cross each other.) Therefore, the detour wiring of each of the connection wiring 7.8 can be reduced, and the logic circuit L og
The IC mounting rate (integration degree) can be improved. Each of the gate electrode 4B and the diagnostic wiring 4b is formed of a gate material consisting of, for example, a single layer of a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or a composite film thereof.

Further, since the number of detours for each of the connection wirings 7 and 8 can be reduced, signal delay can be reduced and the operation speed of the gate array type semiconductor integrated circuit device 1 can be increased.

(Embodiment 2) This embodiment 2 is a second embodiment of the present invention in which the diagnostic wiring 4b is arranged in a shape different from that of the embodiment I.

FIG. 6 (a schematic enlarged plan view of the main parts) shows a basic schematic configuration of a semiconductor integrated circuit device that employs a gate array system with a self-diagnosis function, which is Embodiment (2) of the present invention.

As shown in FIG. 6, the diagnostic wiring 4b of the gate array type semiconductor integrated circuit device 1 of the present embodiment
The wiring formation region 6 along the periphery of the basic cell row 5 has a ring-shaped planar shape surrounding the basic cell row 5. Same as Example I above.

The diagnostic wiring 4b is adapted to form at least a portion of each of the diagnostic signal wiring 11, 12.

The other portions of each of the diagnostic signal wirings 11 and 12 are formed by connection wirings 7 and 8, respectively.

Furthermore, the diagnostic wiring 4b is not limited to a ring shape that extends continuously with no cut points, but may be formed in a ring shape that is cut (divided) into predetermined dimensions.

The semiconductor integrated circuit device 1 employing the gate array method including the self-diagnosis circuit configured as described above is similar to the embodiment (1) described above.
Substantially the same effect can be achieved.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments. However, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to a semiconductor integrated circuit device that employs a gate array method and is formed of three or more interconnection layers.

Furthermore, the present invention can be applied to a semiconductor integrated circuit device that employs a gate array method in which basic cells are spread over the entire surface without providing a wiring formation region between basic cell columns. In the case of this laying method, the basic cells or basic cell rows between the logic circuits are used as the wiring formation area, so the present invention provides a method for making the gate electrodes of the MISFETs forming the basic cells part of the diagnostic signal wiring. It can be used as is for wiring.

Further, in the present invention, the diagnostic wiring that becomes part of the diagnostic signal wiring may be formed in the source region or drain region (electrode of the basic cell) of the MISFET of the basic cell.

Furthermore, the present invention can be applied to a semiconductor integrated circuit device that employs a gate array system in which basic cells are configured with bipolar transistors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

It is possible to improve the circuit mounting rate of a semiconductor integrated circuit device that employs a gate array method with a self-diagnosis function.

[Brief explanation of the drawing]

FIG. 1 is a schematic enlarged plan view of the main parts showing the basic schematic configuration of a semiconductor integrated circuit device adopting a gate array system with a self-diagnosis function, which is Embodiment I of the present invention, and FIG. Chip layout diagram of circuit device. FIG. 3 is a plan view of a main part of a basic cell of the semiconductor integrated circuit device. FIG. 4 is an example logic circuit diagram formed by the basic cells. FIG. 5 is a logic circuit diagram when a self-diagnosis circuit is added to the logic circuit, and FIG. 6 is a semiconductor integrated circuit employing a gate array system with a self-diagnosis function, which is an embodiment (1) of the present invention. FIG. 2 is a schematic enlarged plan view of main parts showing the basic schematic configuration of the device. In the figure, 1... Semiconductor integrated circuit device, 2... External terminal, 3... Human output buffer circuit, 4... Basic cell, 4
B...Gate electrode, 4C, 4D...Semiconductor region, 4
b... Diagnosis wiring, 5... Basic cell row, 6... Wiring formation area, 7.8... Connection wiring, 9, 10...
Signal wiring, 11.12...Diagnostic signal wiring, Qp, Q
n...MISFET.

Claims (1)

[Claims] 1. A gate array method is adopted in which a predetermined circuit is formed by changing the wiring pattern connecting between each electrode of a basic cell and between an electrode of a basic cell and an electrode of another basic cell, In a semiconductor integrated circuit device having a self-diagnosis function in which a predetermined circuit is diagnosed by an external tester or an internal tester, at least a part of the diagnostic signal wiring connecting the external tester or internal tester and the predetermined circuit to be diagnosed is A semiconductor integrated circuit device characterized in that it is formed of the same conductive layer as an electrode of a basic cell. 2. The basic cell is composed of a plurality of MISFETs, and at least a part of the diagnostic signal wiring is connected to the MISFET.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed of the same conductive layer as the gate electrode, source region, or drain region of the FET. 3. The semiconductor according to claim 1 or 2, wherein a part of the diagnostic signal wiring extends over a wiring formation region between adjacent basic cells in a predetermined direction. Integrated circuit device. 4. Each of the semiconductor integrated circuit devices according to claims 1 to 3, wherein a part of the diagnostic signal wiring extends along the periphery of the basic cell.