JP2000252363A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a power-supply noise generated by an output buffer circuit which outputs a signal to the outside while an increase in a chip size and a drop in an integration degree are being suppressed and to reduce a power-supply noise, at a time when outputs of especially a plurality of output buffer circuits are toggled simultaneously or nearly simultaneously. SOLUTION: At least one power-supply pad VDD1 and one ground pad GND1 as well as a signal pad S1 which inputs/outputs a signal from and to the outside are arranged in a row on an IO buffer region in the direction perpendicular to a scribing line in the outer circumferential part of a chip which in the closest to the IO buffer region. The number of bonding wires of a power supply and a ground can be increased while a space is not expanded in the parallel direction in the outer circumference of the scribing line 1 and the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of IOs used for inputting / outputting signals to / from external sources and for taking in power from outside around a core region in which a desired circuit is formed.
The present invention relates to a semiconductor integrated circuit having a layout provided with a buffer region.In particular, it can reduce power supply noise generated in an output buffer circuit that outputs a signal to the outside while suppressing an increase in chip size and a decrease in the degree of integration. The present invention relates to a semiconductor integrated circuit capable of reducing power supply noise when the output of the output buffer circuit toggles simultaneously or almost simultaneously.

[0002]

2. Description of the Related Art FIG. 1 is a circuit diagram including a partial equivalent circuit of a conventional semiconductor integrated circuit.

FIG. 1 shows an output buffer for outputting a signal to the outside, or a wiring for receiving power from the outside, around a core region in which a desired circuit is formed. In the semiconductor integrated circuit, a plurality of IO buffer areas used for inputting / outputting signals to / from the outside and for receiving power from the outside are provided around a core area in which a desired circuit is formed.

Conventionally, the power supply state is such that a plurality of output buffer circuits and, in some cases, input buffer circuits are covered by one bonding wire of the power supply VDD or one bonding wire of the ground GND. State. In FIG. 1, the symbol L represents the inductance component of the bonding wire. The bonding wire is also called a package lead wire or a lead wire.

[0005] Assuming that the power supply current is i, the voltage Enoise of the power supply noise due to the power supply current i is expressed by the following equation.

Enoise = −L (di / dt) (1)

FIG. 2 is a graph showing power supply noise.

In FIG. 2, a signal output from the output buffer circuit is shown by a solid line. Next, the voltage of the power supply VDD is indicated by a chain line. The voltage of the ground GND is indicated by a two-dot chain line.

First, in the voltage of the power supply VDD indicated by the alternate long and short dash line, there is power supply noise in a portion denoted by reference numeral P1. Further, in the voltage of the ground GND indicated by the two-dot chain line, there is power supply noise in the portion indicated by the symbol P2.

[0010]

Conventionally, for example, in FIG. 1, power supply currents i1 to i3 of a plurality of output buffer circuits B1 to B3 flow through one inductance L.
The power supply currents i4 to i6 are flowing through one inductance L. For this reason, when there is one of the output buffer circuits B1 to B3 whose output toggles at the same time, the change of the power supply current in one inductance component L becomes severe due to the simultaneous toggle, and the power supply noise increases.

Due to the power supply noise, the voltage of the output signal of another output buffer circuit that is stationary changes, and there is a possibility that a logic circuit that receives the output signal may malfunction.

The problem of power supply noise can be reduced by increasing the number of bonding wires of the power supply VDD and the number of bonding wires of the ground GND. However, when the number of bonding wires is increased, it is necessary to increase the number of pads on the semiconductor integrated circuit chip for fusing these bonding wires. Then, there arises a problem of the degree of integration such as an increase in the area of the semiconductor integrated circuit chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and suppresses power supply noise generated in an output buffer circuit for outputting a signal to the outside while suppressing an increase in chip size and a decrease in the degree of integration. It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing power supply noise when the outputs of a plurality of output buffer circuits toggle simultaneously or almost simultaneously.

[0014]

According to the present invention, a plurality of IO buffer areas are provided around a core area in which a desired circuit is formed, for use in inputting / outputting a signal to / from the outside or receiving power from the outside. In the semiconductor integrated circuit having the layout described above, at least one of a power supply pad and a ground pad and a signal pad for inputting / outputting a signal to / from an external device are arranged in a direction perpendicular to a scribe line on a chip outer peripheral portion closest to the IO buffer region. The above problem has been solved by arranging in a line in the IO buffer area.

Hereinafter, the operation of the present invention will be briefly described.

According to the present invention, a semiconductor integrated circuit having a layout in which a plurality of IO buffer regions used for inputting / outputting signals to / from the outside and receiving power from the outside is provided around a core region in which a desired circuit is formed. In the circuit, the device is devised in the IO buffer area and its periphery.

In the present invention, at least one of a power supply pad and a ground pad is provided for each signal input / output to and from the outside using an IO buffer, and power supply or ground wiring by a bonding wire is provided for each signal as required. Is connected to the outside of the semiconductor integrated circuit chip. In this way, since the connection is made with a larger number of bonding wires than in the past, power supply noise generated in an output buffer circuit or the like that outputs a signal to the outside can be reduced,
In particular, it is possible to reduce power supply noise when the outputs of the plurality of output buffer circuits toggle at the same time or almost at the same time.

Further, according to the present invention, as described above, at least one of a power supply pad and a ground pad, and a pad for a signal input / output from the IO buffer area to the outside, which are increased as compared with the related art, are provided in the IO buffer area. In the direction perpendicular to the scribe line on the outer peripheral portion of the chip that comes closest, the IO
Place them in a line in the buffer area. Therefore, the number of pads arranged in the direction parallel to the scribe line, that is, the direction parallel to the outer periphery of the semiconductor integrated circuit chip does not increase. Therefore, there is no need to enlarge the outer shape of the semiconductor integrated circuit chip, and it is possible to suppress an increase in chip size and a decrease in the degree of integration.

The present invention does not limit the detailed arrangement of the pads arranged in a line in this manner. The disposition position is preferably on the scribe line side in the IO buffer area.

The pads arranged in a row may be a pad for signals input / output from the IO buffer area to the outside and a power supply pad. Alternatively, the signal pad and the ground pad may be used. Alternatively, these signal pads, power supply pads, and ground pads may be used. Further, in such a one-row arrangement, the order of the one-row pads is not limited.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 shows the IO of the portion of the semiconductor integrated circuit chip according to the first embodiment to which the present invention is applied.
FIG. 2 is an integrated circuit layout diagram centering on a buffer area. FIG. 4 is a circuit diagram around the IO buffer area. FIG. 5 is a cross-sectional view around the IO buffer region in the semiconductor integrated circuit.

First, in FIG. 3, the dashed line 1 is a scribe line of the semiconductor integrated circuit chip of the present embodiment. The right side of the scribe line 1 is the inside of the semiconductor integrated circuit chip, and the area surrounded by the dashed line 3 is the IO buffer area. An area is provided. In the present embodiment, the element region A and the pad arrangement portion are separated, but the pad arrangement portion may overlap the element region. That is, pads may be arranged on the element region A. On the right side of the IO buffer area, there is a core area in which a desired circuit is formed. The semiconductor integrated circuit according to the present embodiment has a layout in which a plurality of IO buffer regions used for inputting / outputting signals to / from external devices and receiving power from the external devices are provided around a core region in which a desired circuit is formed. is there.

The left side of the scribe line 1 is outside the semiconductor integrated circuit chip, and the leads GND2, S2, and VDD2 of the package for sealing the semiconductor integrated circuit chip are arranged. Via these leads,
It is electrically connected to pins outside the package.

4 and 5, the P channel M
The OS transistor T1 and the N-channel MOS transistor T2 form an output buffer in the IO buffer area.

The output signal S of the output buffer is shown in FIGS.
The signal is output to the outside of the package of the semiconductor integrated circuit chip via the signal wiring W2, the pad S1 in the semiconductor integrated circuit chip, the bonding wire connecting the pad S1 and the above-mentioned lead S2, and the lead S2. In supplying power to the output buffer, first, the power supply VD
As for D, from the outside of the package,
D2, a bonding wire connecting the lead VDD2 and the pad VDD1 in the semiconductor integrated circuit chip, a P-channel MOS via the pad VDD1, and the power supply wiring W1.
Connected to the source of transistor T1. As for the power supply GND, the above-mentioned lead GND is supplied from outside the package.
2. Bonding wires for connecting the leads GND2 and the pads GND1 in the semiconductor integrated circuit chip, the pads GND1, and the power supply wiring W3.

In this embodiment, a power supply pad and a ground pad are provided for each signal to be output to the outside using the IO buffer, and the power supply and ground wiring by bonding wires is connected to the outside of the chip for each signal. Like that. As described above, since the connection is made with a larger number of bonding wires than in the related art, power supply noise generated in an output buffer circuit or the like that outputs a signal to the outside can be reduced. In particular, the outputs of a plurality of the output buffer circuits are simultaneously or almost simultaneously. Power supply noise when toggling can be reduced.

A power supply pad VDD1, a ground pad GND1, and a pad S1 for outputting a signal from the IO buffer area to the outside are arranged in a line in the left-right direction in FIG. The direction is a direction perpendicular to the scribe line 1 in the outer peripheral portion of the chip closest to the IO buffer area. Therefore, the number of pads arranged in the direction parallel to the scribe line 1, that is, the direction parallel to the outer periphery of the semiconductor integrated circuit chip does not increase. Therefore, there is no need to enlarge the outer shape of the semiconductor integrated circuit chip, and it is possible to suppress an increase in chip size and a decrease in the degree of integration.

Next, in FIG. 5, as in FIG.
Is a scribe line. The area surrounded by the dashed line 3 is the IO buffer area. Within the IO buffer area, a power supply pad VDD1 and a ground pad GND1
And a pad S1 for a signal to be output from the IO buffer area to the outside.

Further, in FIG. 5, M1 to M5 denote a first metal wiring layer to a fifth metal wiring layer, respectively. As described above, in the present embodiment, the metal wiring layer has a five-layer structure. However, the present invention is not limited to this, and the pads S1, VDD
1, GND1 and any number of layers may be used as long as wiring to these pads is possible. If the conditions of performance and other factors are satisfied, a wiring layer other than the metal wiring layer may be used.

FIG. 6 is a layout diagram of a chip of a semiconductor integrated circuit according to a second embodiment of the present invention and its periphery.

In FIG. 6, a scribe line 1 shown by a broken line shows the outer periphery of the semiconductor integrated circuit chip of this embodiment, and also shows a layout of a part of a package for sealing the semiconductor integrated circuit chip. . The semiconductor integrated circuit chip of the present embodiment is the same as that of the first embodiment described above. This embodiment is different from the first embodiment in a package for sealing a semiconductor integrated circuit chip.

That is, in the second embodiment, in the package of the semiconductor integrated circuit, a ring-shaped wiring VDD3 used as a power supply VDD lead is provided around the semiconductor integrated circuit chip to be mounted. Similarly, a ring-shaped wiring GND3 used as a ground GND lead is provided around the semiconductor integrated circuit chip to be mounted. Note that the ring-shaped wiring GND3 is a ring-shaped wiring V
Although it is outside DD3, it may be provided inside.

Further, a number of leads S3 for inputting and outputting signals to and from the IO buffer area are provided outside the ring-shaped wiring VDD3 and the ring-shaped wiring GND3. A part of the lead S3 is used to output a signal from the output buffer in the IO buffer area to the outside of the package of the semiconductor integrated circuit chip. The lead S3 is laid almost in a radial direction in FIG.

In the semiconductor integrated circuit chip whose outer shape is indicated by the scribe line 1, a large number of the above-mentioned IO buffer areas are formed adjacent to the hatched area of the reference numeral 7. Reference numeral 5 in the shaded portion indicates a core region in which a desired circuit is formed.

FIG. 7 is an integrated circuit layout diagram of the semiconductor integrated circuit according to the present embodiment, focusing on the IO buffer region of the portion to which the present invention is applied.

FIG. 7 corresponds to FIG. 3 of the first embodiment, and the difference can be clearly grasped by comparing. In addition,
7, the lower side of the dashed line scribe line 1 is inside the semiconductor integrated circuit chip, and the scribe line 1, the dashed line 3, the pads S1, VDD1, GND1 and the like are the same as in the first embodiment.

In this embodiment, FIG. 7, FIG. 4 and FIG.
, The output signal S of the output buffer is
2. Pad S1 in the semiconductor integrated circuit chip;
A bonding wire connecting the lead 1 and the lead S3 is output to the outside of the package of the semiconductor integrated circuit via the lead S3. In the power supply to the output buffer, first, the power supply VDD is supplied from the outside of the package to the aforementioned lead VDD3, a bonding wire connecting the lead VDD3 to the pad VDD1 in the semiconductor integrated circuit chip, the pad VDD1, the power supply wiring. W1
Connected via As for the power supply GND, the above-described lead GND3, the lead GND,
3 and a bonding wire connecting the pad GND1 in the semiconductor integrated circuit chip, the pad GND1, and the power supply wiring W3.

In this embodiment, in the package of the semiconductor integrated circuit, the wiring VDD3 used as a lead is used.
Since the wiring GND3 is ring-shaped, the signal lead S
It is easier to form than in the first embodiment provided for every two. In addition, it is easier to provide a common power supply VDD or ground GND pin for a plurality of signals S3 as compared with the first embodiment. Effective utilization is easy.

FIG. 8 is a circuit diagram including a partially equivalent circuit of the semiconductor integrated circuits of the first and second embodiments described above.

This figure is different from the above-described conventional example shown in FIG. 1, in which an output buffer for outputting a signal to the outside or a power supply from the outside is provided around a core region in which a desired circuit is formed. The wiring to be taken is shown. FIG.
, L represents an inductance component of the package lead and the bonding wire.

In FIG. 1 of the conventional example described above, the power supply VDD
In this state, a plurality of output buffer circuits and, in some cases, an input buffer circuit are covered by one bonding wire or one bonding wire of the ground GND. Therefore, a plurality of output buffer circuits B
Power supply currents i1 to i3 of 1 to B3 flow through one inductance L. The power supply currents i4 to i6 are flowing through one inductance L.

On the other hand, as shown in FIG. 8, in these embodiments, the bonding wire of the power supply VDD, the ground GND, and the like are provided to each of the plurality of output buffer circuits and, in some cases, each of the plurality of input buffer circuits.
D bonding wires are provided. Therefore, the power supply currents i1 to i3 of the output buffer circuits B1 to B3 are flowing to another inductance L. Also, the power supply current i4
i6 is flowing through another inductance L.

Therefore, in these embodiments, even in the case where there are output buffer circuits B1 to B3 whose outputs toggle at the same time, the power supply noise Enoise expressed by the above equation (1) is reduced.

As described above, the present invention can be effectively applied to the first embodiment and the second embodiment. Therefore, while suppressing an increase in chip size and a decrease in the degree of integration, power supply noise generated in an output buffer circuit for outputting a signal to the outside is reduced, and in particular, the outputs of a plurality of the output buffer circuits are simultaneously or almost simultaneously toggled. The power supply noise at the time of performing can be reduced.

[0046]

According to the present invention, while suppressing an increase in chip size and a decrease in the degree of integration, it is possible to reduce power supply noise generated in an output buffer circuit or the like for outputting a signal to the outside. Power supply noise when the output of the circuit toggles at or almost simultaneously can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram including a partial equivalent circuit of a conventional semiconductor integrated circuit.

FIG. 2 is a graph showing power supply noise.

FIG. 3 is an integrated circuit layout diagram of the semiconductor integrated circuit according to the first embodiment to which the present invention is applied, focusing on an IO buffer region to which the present invention is applied;

FIG. 4 is a circuit diagram around the IO buffer area.

FIG. 5 shows the IO in the semiconductor integrated circuit of the embodiment.
Sectional view around buffer area

FIG. 6 is a layout diagram of a chip of a semiconductor integrated circuit according to a second embodiment to which the present invention is applied and the periphery thereof;

FIG. 7 is an integrated circuit layout diagram centering on an IO buffer region of a portion to which the present invention is applied in the semiconductor integrated circuit of the embodiment.

FIG. 8 is a circuit diagram including a partially equivalent circuit of the semiconductor integrated circuit according to the first embodiment and the second embodiment;

[Explanation of symbols]

1: Scribe line VDD: Power supply GND: Ground W1 to W3: Wiring VDD1, GND1, S1 ... Pads VDD2, VDD3, GND2, GND3, S2, S3
... Leads B1 to B3 ... Output buffer circuit L ... Inductance

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a layout in which a plurality of IO buffer regions used for inputting / outputting a signal to / from an external device and receiving power from an external device are provided around a core region in which a desired circuit is formed. At least one of a power supply pad and a ground pad, and a signal pad for inputting / outputting a signal to / from the outside are arranged in a line in the IO buffer area in a direction perpendicular to a scribe line on a chip outer peripheral portion closest to the IO buffer area. A semiconductor integrated circuit characterized in that: